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My (planned) graduate project on invertible computation.
Verilog
tree: 3cc2ba489f

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talk
.gitignore
BaseLib.v
Janus.v
Janus0.v
Janus1.v
Makefile
MemMonad.v
Memory.v
NOTES
TODO
W32Store.v
Word32.v
ZStore.v
coqdoc.sty
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