Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Start Final Report Draft on Google Docs #8

Closed
jmoles opened this issue Jun 9, 2013 · 0 comments
Closed

Start Final Report Draft on Google Docs #8

jmoles opened this issue Jun 9, 2013 · 0 comments
Assignees
Milestone

Comments

@jmoles
Copy link
Owner

jmoles commented Jun 9, 2013

Need to start final project write-up. From Lecture 13 Handout, this is the deliverable requirements:

  • Write-up
    • Overview of your project including an English description of the circuit’s
      function
    • Block diagram of your circuit
      *Design details, including a theory of operation, state transition
      diagrams or equivalent, etc.
    • Results (good and bad)
    • Contributions of individual team members
    • No more than 10 pages please
  • Source Code
    • Listings of all of your Verilog files - including test benches
    • Listings of your program source code
    • Your .mhs, .mss, and .ucf files if using Xilinx/Microblaze
    • Your code should be liberally commented and use descriptive signal
      and/or variables names
    • .bit, .bmm and .elf files – We may try running your project
@ghost ghost assigned TejashreeC Jun 9, 2013
@jmoles jmoles closed this as completed Jun 12, 2013
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

2 participants