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Implementation of a simple RISC style processor for on an Altera DE0 board. Created using VHDL and Altera Quartus II.
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Simulation_Pictures
db
greybox_tmp
incremental_db
output_files
simulation/modelsim
.DS_Store
512_Mem.vhd.bak
ALU_Toplevel.vhd
ALU_Toplevel.vhd.bak
ALU_tb.vhd
ALU_tb.vhd.bak
Bus.bdf
Bus.vhd
CPU_Bus.bdf
CPU_Bus.vhd
CPU_Bus_Redesign.vhd
CPU_Bus_Redesign.vhd.bak
CPU_Bus_tb.vhd
CPU_Bus_tb.vhd.bak
ConFF.vhd
ConFF.vhd.bak
DE0_board.vhd
DE0_board.vhd.bak
Decoder2to4.cmp
Decoder2to4.qip
Decoder2to4.vhd
FA.cmp
FA.qip
FA.vhd
FA.vhd.bak
IRreg.vhd
IRreg.vhd.bak
MDR_Unit.bdf
MDR_Unit.bsf
MDR_Unit.vhd
MDR_Unit.vhd.bak
PCincr.cmp
PCincr.qip
PCincr.vhd
README.md
REG32.bsf
REG32.vhd
REG32.vhd.bak
REG64.vhd
REG64.vhd.bak
RegSpecial0.vhd
RegSpecial0.vhd.bak
SRC_CPU.qpf
SRC_CPU.qsf
SRC_CPU.qws
SRC_CPU.tis_db_list.ddb
SRC_CPU_nativelink_simulation.rpt
Seven_Segment.vhd
Seven_Segment.vhd.bak
add.cmp
add.qip
add.vhd
add_sub.cmp
add_sub.qip
add_sub.vhd
add_tb.vhd
add_tb.vhd.bak
and_tb.vhd
and_tb.vhd.bak
array_mult.vhd
array_mult.vhd.bak
boothJohu.vhd
boothJohu.vhd.bak
bus_tb.vhd
bus_tb.vhd.bak
common.vhd
common.vhd.bak
control_unit.vhd
control_unit.vhd.bak
datapath.vhd
datapath.vhd.bak
datapath_tb.vhd
datapath_tb.vhd.bak
decoder.bdf
decoder.vhd
decoder4to16.vhd
decoder4to16.vhd.bak
div_tb.vhd
div_tb.vhd.bak
fa1.bsf
fa1.cmp
fa1.qip
fa1.vhd
fa1.vhd.bak
iplauncher_debug.log
lpm_decode0.bsf
lpm_decode0.cmp
lpm_decode0.qip
lpm_decode0.vhd
lpm_encoder.bsf
lpm_encoder.vhd
lpm_encoder.vhd.bak
lpm_mux0.bsf
lpm_mux0.cmp
lpm_mux0.qip
lpm_mux0.vhd
lpm_mux1.bsf
lpm_mux1.cmp
lpm_mux1.qip
lpm_mux1.vhd
marReg.vhd
marReg.vhd.bak
megaRAM.cmp
megaRAM.qip
megaRAM.vhd
mem_tb.vhd
mem_tb.vhd.bak
memory.vhd
memory.vhd.bak
miffile.mif
miffile.mif.bak
mul_tb.vhd
mul_tb.vhd.bak
mulbooth_tb.vhd
mulbooth_tb.vhd.bak
mult32bit.cmp
mult32bit.qip
mult32bit.vhd
multi_bit_ALU.vhd
multi_bit_ALU.vhd.bak
neg_tb.vhd
neg_tb.vhd.bak
negate.cmp
negate.qip
negate.vhd
nonRestor_division.vhd
not_tb.vhd
not_tb.vhd.bak
one_bit_ALU.vhd
one_bit_ALU.vhd.bak
or_tb.vhd
or_tb.vhd.bak
overall_tb.vhd
overall_tb.vhd.bak
phase2_tb.vhd
phase2_tb.vhd.bak
phase3_tb.vhd
phase3_tb.vhd.bak
random_tb.vhd
random_tb.vhd.bak
reg32_tb.vhd
reg32_tb.vhd.bak
rol_tb.vhd
rol_tb.vhd.bak
ror_tb.vhd
ror_tb.vhd.bak
rotate_left.cmp
rotate_left.qip
rotate_left.vhd
rotate_right.cmp
rotate_right.qip
rotate_right.vhd
selAndEncode.vhd
selAndEncode.vhd.bak
shift.cmp
shift.qip
shift.vhd
shiftL64.vhd
shift_left.cmp
shift_left.qip
shift_left.vhd
shift_right.cmp
shift_right.qip
shift_right.vhd
shift_right.vhd.bak
shift_tb.vhd
shift_tb.vhd.bak
shl_tb.vhd
shl_tb.vhd.bak
shr_tb.vhd
shr_tb.vhd.bak
signed_division.cmp
signed_division.qip
signed_division.vhd
sub.cmp
sub.qip
sub.vhd
sub_tb.vhd
sub_tb.vhd.bak
the_tb.vhd.bak
workingBooth.vhd
workingBooth.vhd.bak
workingBoothTB.vhd
workingBoothTB.vhd.bak

README.md

CPUDesignProject

Implementation of a simple RISC style processor for on an Altera DE0 Cyclone III board. Created using VHDL and Altera Quartus II. Project created for course project in ELEC 374 Computer Architecture course at Queen's University.

Getting Started

These instructions will get you a copy of the project up and running on your local machine for development and testing purposes. See deployment for notes on how to deploy the project on a live system.

Prerequisites

What things you need to install the software and how to install them

Altera Quartus II
Model Sim Altera Quartus Addon
Altera DE0 board (not required for only simulation activities)

How to open project

  1. Start Altera Quartus II
  2. Open SRC_CPU.qpf project file
  3. Investigate VHDL contents for each component of the CPU.
    1. Example, workingBooth.vhd implements the Booth's multiplication algorithm.
    2. Another example, datapath.vhd combines all components required for the CPU's datapath.
  4. Use ModelSim to simulate various CPU functions. Image below shows a shift right register simulation (Other screenshots can be found in Simulation_Pictures directory).

alt text

Authors

  • Madeline Van Der Paelt
  • Maytha Nassor
  • Johan Cornelissen

Acknowledgments

  • Prof. Ahmad Afsahi, Instructor of ELEC 374 Computer Architecture during Winter 2016.
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