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Apparently there are democoders who enable VGA Mode X but also accide…

…ntally enable Chain odd/even mode. I prefer that DOSBox-X accurately emulate the mistake and the effects on VGA display, however add dosbox.conf option to compensate by ignoring odd/even chain mode in non-CGA compatible modes.
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joncampbell123 committed Jun 23, 2018
1 parent c0386a8 commit 570693494c515ef1a034af768ca692cbc00ca6da
Showing with 19 additions and 5 deletions.
  1. +5 −0 src/dosbox.cpp
  2. +3 −0 src/hardware/vga.cpp
  3. +11 −5 src/hardware/vga_memory.cpp
@@ -1406,6 +1406,11 @@ void DOSBOX_SetupConfigSections(void) {
Pbool = secprop->Add_bool("enable pci bus",Property::Changeable::OnlyAtStart,true);
Pbool->Set_help("Enable PCI bus emulation");
Pbool = secprop->Add_bool("ignore odd-even mode in non-cga modes",Property::Changeable::Always,false);
Pbool->Set_help("Some demoscene productions use VGA Mode X but accidentally enable odd/even mode.\n"
"Setting this option can correct for that and render the demo properly.\n"
"This option forces VGA emulation to ignore odd/even mode except in text and CGA modes.");
secprop=control->AddSection_prop("render",&Null_Init,true);
Pint = secprop->Add_int("frameskip",Property::Changeable::Always,0);
Pint->SetMinMax(0,10);
@@ -181,6 +181,8 @@ bool vga_sierra_lock_565 = false;
bool enable_vga_resize_delay = false;
bool vga_ignore_hdispend_change_if_smaller = false;
bool ignore_vblank_wraparound = false;
bool non_cga_ignore_oddeven = false;
bool non_cga_ignore_oddeven_engage = false;
bool vga_double_buffered_line_compare = false;
bool pc98_allow_scanline_effect = true;
bool pc98_allow_4_display_partitions = false;
@@ -587,6 +589,7 @@ void VGA_Reset(Section*) {
ignore_vblank_wraparound = section->Get_bool("ignore vblank wraparound");
vga_enable_hretrace_effects = section->Get_bool("allow hretrace effects");
enable_page_flip_debugging_marker = section->Get_bool("page flip debug line");
non_cga_ignore_oddeven = section->Get_bool("ignore odd-even mode in non-cga modes");
enable_vretrace_poll_debugging_marker = section->Get_bool("vertical retrace poll debug line");
vga_double_buffered_line_compare = section->Get_bool("double-buffered line compare");
hack_lfb_yadjust = section->Get_int("vesa lfb base scanline adjust");
@@ -32,6 +32,9 @@
#include "pc98_cg.h"
#include "pc98_gdc.h"
extern bool non_cga_ignore_oddeven;
extern bool non_cga_ignore_oddeven_engage;
#ifndef C_VGARAM_CHECKED
#define C_VGARAM_CHECKED 1
#endif
@@ -161,7 +164,7 @@ static inline Bitu VGA_Generic_Read_Handler(PhysPt planeaddr,PhysPt rawaddr,unsi
* bits[1:1] = Extended memory (when EGA cards have > 64KB of RAM)
*
* NTS: Real hardware experience says that despite the name, the Odd/Even bit affects reading as well */
if (!(vga.seq.memory_mode&4))/* Odd Even Host Memory Write Addressing Disable (is not set) */
if (!(vga.seq.memory_mode&4) && !non_cga_ignore_oddeven_engage)/* Odd Even Host Memory Write Addressing Disable (is not set) */
plane = (plane & ~1u) + (rawaddr & 1u);
/* Graphics Controller: Miscellaneous Graphics Register register (06h)
@@ -174,7 +177,7 @@ static inline Bitu VGA_Generic_Read_Handler(PhysPt planeaddr,PhysPt rawaddr,unsi
* When enabled, address bit A0 (bit 0) becomes bit 0 of the plane index.
* Then when addressing VRAM A0 is replaced by a "higher order bit", which is
* probably A14 or A16 depending on Extended Memory bit 1 in Sequencer register 04h memory mode */
if (vga.gfx.miscellaneous&2) {/* Odd/Even enable */
if ((vga.gfx.miscellaneous&2) && !non_cga_ignore_oddeven_engage) {/* Odd/Even enable */
const PhysPt mask = (1u << hobit_n) - 2u;
const PhysPt hobit = (planeaddr >> hobit_n) & 1u;
/* 1 << 14 = 0x4000
@@ -212,13 +215,13 @@ template <const bool chained> static inline void VGA_Generic_Write_Handler(PhysP
*
* NTS: Real hardware experience says that despite the name, the Odd/Even bit affects reading as well */
if (chained) {
if (!(vga.seq.memory_mode&4))/* Odd Even Host Memory Write Addressing Disable (is not set) */
if (!(vga.seq.memory_mode&4) && !non_cga_ignore_oddeven_engage)/* Odd Even Host Memory Write Addressing Disable (is not set) */
mask &= 0xFF00FFu << ((rawaddr & 1u) * 8u);
else
mask &= 0xFFu << ((rawaddr & 3u) * 8u);
}
else {
if (!(vga.seq.memory_mode&4))/* Odd Even Host Memory Write Addressing Disable (is not set) */
if (!(vga.seq.memory_mode&4) && !non_cga_ignore_oddeven_engage)/* Odd Even Host Memory Write Addressing Disable (is not set) */
mask &= 0xFF00FFu << ((rawaddr & 1u) * 8u);
}
@@ -232,7 +235,7 @@ template <const bool chained> static inline void VGA_Generic_Write_Handler(PhysP
* When enabled, address bit A0 (bit 0) becomes bit 0 of the plane index.
* Then when addressing VRAM A0 is replaced by a "higher order bit", which is
* probably A14 or A16 depending on Extended Memory bit 1 in Sequencer register 04h memory mode */
if (vga.gfx.miscellaneous&2) {/* Odd/Even enable */
if ((vga.gfx.miscellaneous&2) && !non_cga_ignore_oddeven_engage) {/* Odd/Even enable */
const PhysPt mask = (1u << hobit_n) - 2u;
const PhysPt hobit = (planeaddr >> hobit_n) & 1u;
/* 1 << 14 = 0x4000
@@ -2394,6 +2397,9 @@ void VGA_SetupHandlers(void) {
}
if(svgaCard == SVGA_S3Trio && (vga.s3.ext_mem_ctrl & 0x10))
MEM_SetPageHandler(VGA_PAGE_A0, 16, &vgaph.mmio);
non_cga_ignore_oddeven_engage = (non_cga_ignore_oddeven && !(vga.mode == M_TEXT || vga.mode == M_CGA2 || vga.mode == M_CGA4));
range_done:
PAGING_ClearTLB();
}

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