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A merge sorter IP based on hCODE 2.0 platform, which is implemented with Vivado HLS.
ip-mergesorter-32bit is an hardware merge sorter IP. It use Vivado_HLS for the high-level synthesis. It can generate verilog codes of a merge sorter tree of any given size.
ip-loopback-32bit is a simple circuit which reads input data, adds a value from memory port, and writes back to output port. It use Vivado_HLS for the high-level synthesis.
Forked from hCODE-FPGA/hCODE
A merge sorter IP that can generate specified depth and data-width mergesorter tree with ap_fifo interface implemented in Vivado HLS
A hCODE shell based on RIFFA2.2.1 (VC707_Gen2x8If128) PCIe module.