Block or report user

Popular repositories

  1. ip-kvsorter

    A merge sorter IP based on hCODE 2.0 platform, which is implemented with Vivado HLS.

    C 1

  2. ip-mergesorter-32bit

    ip-mergesorter-32bit is an hardware merge sorter IP. It use Vivado_HLS for the high-level synthesis. It can generate verilog codes of a merge sorter tree of any given size.

    Java

  3. ip-loopback

    ip-loopback-32bit is a simple circuit which reads input data, adds a value from memory port, and writes back to output port. It use Vivado_HLS for the high-level synthesis.

    C++

  4. hCODE

    Forked from hCODE-FPGA/hCODE

    Ruby

  5. ip-mergesorter

    A merge sorter IP that can generate specified depth and data-width mergesorter tree with ap_fifo interface implemented in Vivado HLS

    Java

  6. shell-vc707-riffa2-ap_fifo32

    A hCODE shell based on RIFFA2.2.1 (VC707_Gen2x8If128) PCIe module.

    Verilog

18 contributions in the last year

Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Mon Wed Fri

Contribution activity

April - June 2018

jonsonxp has no activity yet for this period.

March 2018

Seeing something unexpected? Take a look at the GitHub profile guide.