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OS-6409 import Pluribus bhyve port

Authored by: Krupal Joshi <krupal.joshi@pluribusnetworks.com>
Contributed by: Pluribus Networks Inc.
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Dan McDonald <danmcd@joyent.com>
Reviewed by: Mike Gerdts <mike.gerdts@joyent.com>
Reviewed by: Patrick Mooney <patrick.mooney@joyent.com>
Approved by: Mike Gerdts <mike.gerdts@joyent.com>
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tychon-pluribus authored and pfmooney committed Sep 26, 2017
1 parent 44db5f1 commit 43f85cd4da7e7860e4d240f14e6b5dd45700c7b6
Showing with 52,310 additions and 2 deletions.
  1. +6 −0 usr/contrib/freebsd/amd64/machine/_types.h
  2. +6 −0 usr/contrib/freebsd/amd64/machine/psl.h
  3. +6 −0 usr/contrib/freebsd/amd64/machine/specialreg.h
  4. +54 −0 usr/contrib/freebsd/amd64/machine/timerreg.h
  5. +45 −0 usr/contrib/freebsd/amd64/machine/vm.h
  6. +67 −0 usr/contrib/freebsd/dev/acpica/acpi_hpet.h
  7. +78 −0 usr/contrib/freebsd/dev/ic/i8253reg.h
  8. +86 −0 usr/contrib/freebsd/dev/ic/i8259.h
  9. +240 −0 usr/contrib/freebsd/dev/ic/ns16550.h
  10. +922 −0 usr/contrib/freebsd/dev/pci/pcireg.h
  11. +70 −0 usr/contrib/freebsd/isa/isareg.h
  12. +93 −0 usr/contrib/freebsd/lib/libutil/expand_number.c
  13. +635 −0 usr/contrib/freebsd/sys/ata.h
  14. +119 −0 usr/contrib/freebsd/sys/linker_set.h
  15. +765 −0 usr/contrib/freebsd/sys/tree.h
  16. +455 −0 usr/contrib/freebsd/x86/apicreg.h
  17. +204 −0 usr/contrib/freebsd/x86/mptable.h
  18. +92 −0 usr/contrib/freebsd/x86/psl.h
  19. +839 −0 usr/contrib/freebsd/x86/specialreg.h
  20. +41 −0 usr/src/cmd/bhyve/Makefile
  21. +94 −0 usr/src/cmd/bhyve/Makefile.com
  22. +54 −0 usr/src/cmd/bhyve/acpi.h
  23. +304 −0 usr/src/cmd/bhyve/ahci.h
  24. +21 −0 usr/src/cmd/bhyve/amd64/Makefile
  25. +576 −0 usr/src/cmd/bhyve/atkbdc.c
  26. +38 −0 usr/src/cmd/bhyve/atkbdc.h
  27. +86 −0 usr/src/cmd/bhyve/bhyve_sol_glue.c
  28. +78 −0 usr/src/cmd/bhyve/bhyvegc.c
  29. +44 −0 usr/src/cmd/bhyve/bhyvegc.h
  30. +820 −0 usr/src/cmd/bhyve/bhyverun.c
  31. +73 −0 usr/src/cmd/bhyve/bhyverun.h
  32. +625 −0 usr/src/cmd/bhyve/block_if.c
  33. +70 −0 usr/src/cmd/bhyve/block_if.h
  34. +101 −0 usr/src/cmd/bhyve/console.c
  35. +50 −0 usr/src/cmd/bhyve/console.h
  36. +155 −0 usr/src/cmd/bhyve/consport.c
  37. +34 −0 usr/src/cmd/bhyve/dbgport.h
  38. +297 −0 usr/src/cmd/bhyve/inout.c
  39. +91 −0 usr/src/cmd/bhyve/inout.h
  40. +74 −0 usr/src/cmd/bhyve/ioapic.c
  41. +39 −0 usr/src/cmd/bhyve/ioapic.h
  42. +291 −0 usr/src/cmd/bhyve/mem.c
  43. +61 −0 usr/src/cmd/bhyve/mem.h
  44. +377 −0 usr/src/cmd/bhyve/mptbl.c
  45. +35 −0 usr/src/cmd/bhyve/mptbl.h
  46. +2,009 −0 usr/src/cmd/bhyve/pci_ahci.c
  47. +2,103 −0 usr/src/cmd/bhyve/pci_emul.c
  48. +283 −0 usr/src/cmd/bhyve/pci_emul.h
  49. +70 −0 usr/src/cmd/bhyve/pci_hostbridge.c
  50. +351 −0 usr/src/cmd/bhyve/pci_irq.c
  51. +45 −0 usr/src/cmd/bhyve/pci_irq.h
  52. +433 −0 usr/src/cmd/bhyve/pci_lpc.c
  53. +72 −0 usr/src/cmd/bhyve/pci_lpc.h
  54. +392 −0 usr/src/cmd/bhyve/pci_virtio_block.c
  55. +870 −0 usr/src/cmd/bhyve/pci_virtio_net.c
  56. +706 −0 usr/src/cmd/bhyve/pci_virtio_viona.c
  57. +333 −0 usr/src/cmd/bhyve/pm.c
  58. +212 −0 usr/src/cmd/bhyve/pmtmr.c
  59. +53 −0 usr/src/cmd/bhyve/post.c
  60. +418 −0 usr/src/cmd/bhyve/ps2kbd.c
  61. +39 −0 usr/src/cmd/bhyve/ps2kbd.h
  62. +371 −0 usr/src/cmd/bhyve/ps2mouse.c
  63. +39 −0 usr/src/cmd/bhyve/ps2mouse.h
  64. +420 −0 usr/src/cmd/bhyve/rfb.c
  65. +36 −0 usr/src/cmd/bhyve/rfb.h
  66. +380 −0 usr/src/cmd/bhyve/rtc.c
  67. +34 −0 usr/src/cmd/bhyve/rtc.h
  68. +827 −0 usr/src/cmd/bhyve/smbiostbl.c
  69. +36 −0 usr/src/cmd/bhyve/smbiostbl.h
  70. +104 −0 usr/src/cmd/bhyve/spinup_ap.c
  71. +34 −0 usr/src/cmd/bhyve/spinup_ap.h
  72. +1,042 −0 usr/src/cmd/bhyve/uart_emul.c
  73. +45 −0 usr/src/cmd/bhyve/uart_emul.h
  74. +1,289 −0 usr/src/cmd/bhyve/vga.c
  75. +160 −0 usr/src/cmd/bhyve/vga.h
  76. +755 −0 usr/src/cmd/bhyve/virtio.c
  77. +475 −0 usr/src/cmd/bhyve/virtio.h
  78. +237 −0 usr/src/cmd/bhyve/xmsr.c
  79. +36 −0 usr/src/cmd/bhyve/xmsr.h
  80. +41 −0 usr/src/cmd/bhyveconsole/Makefile
  81. +360 −0 usr/src/cmd/bhyveconsole/bhyveconsole.c
  82. +43 −0 usr/src/cmd/bhyveconsole/i386/Makefile
  83. +41 −0 usr/src/cmd/bhyvectl/Makefile
  84. +48 −0 usr/src/cmd/bhyvectl/Makefile.com
  85. +21 −0 usr/src/cmd/bhyvectl/amd64/Makefile
  86. +1,523 −0 usr/src/cmd/bhyvectl/bhyvectl.c
  87. +41 −0 usr/src/cmd/bhyveload-uefi/Makefile
  88. +52 −0 usr/src/cmd/bhyveload-uefi/Makefile.com
  89. +21 −0 usr/src/cmd/bhyveload-uefi/amd64/Makefile
  90. +190 −0 usr/src/cmd/bhyveload-uefi/bhyveload-uefi.c
  91. +18 −0 usr/src/cmd/bhyveload-uefi/i386/Makefile
  92. +20 −0 usr/src/cmd/mdb/intel/amd64/vmm/Makefile
  93. +32 −0 usr/src/cmd/mdb/intel/amd64/vmm/amd64/Makefile
  94. +238 −0 usr/src/cmd/mdb/intel/amd64/vmm/vmm.c
  95. +28 −0 usr/src/compat/freebsd/amd64/machine/asmacros.h
  96. +244 −0 usr/src/compat/freebsd/amd64/machine/atomic.h
  97. +23 −0 usr/src/compat/freebsd/amd64/machine/clock.h
  98. +165 −0 usr/src/compat/freebsd/amd64/machine/cpufunc.h
  99. +29 −0 usr/src/compat/freebsd/amd64/machine/fpu.h
  100. +24 −0 usr/src/compat/freebsd/amd64/machine/md_var.h
  101. +39 −0 usr/src/compat/freebsd/amd64/machine/param.h
  102. +21 −0 usr/src/compat/freebsd/amd64/machine/pcb.h
  103. +44 −0 usr/src/compat/freebsd/amd64/machine/pmap.h
  104. +21 −0 usr/src/compat/freebsd/amd64/machine/segments.h
  105. +19 −0 usr/src/compat/freebsd/amd64/machine/smp.h
  106. +21 −0 usr/src/compat/freebsd/amd64/machine/vmm.h
  107. +21 −0 usr/src/compat/freebsd/amd64/machine/vmm_dev.h
  108. +21 −0 usr/src/compat/freebsd/amd64/machine/vmm_instruction_emul.h
  109. +19 −0 usr/src/compat/freebsd/amd64/machine/vmparam.h
  110. +21 −0 usr/src/compat/freebsd/libutil.h
  111. +21 −0 usr/src/compat/freebsd/net/ethernet.h
  112. +21 −0 usr/src/compat/freebsd/paths.h
  113. +28 −0 usr/src/compat/freebsd/pthread_np.h
  114. +26 −0 usr/src/compat/freebsd/string.h
  115. +23 −0 usr/src/compat/freebsd/strings.h
  116. +24 −0 usr/src/compat/freebsd/sys/_iovec.h
  117. +19 −0 usr/src/compat/freebsd/sys/_pthreadtypes.h
  118. +22 −0 usr/src/compat/freebsd/sys/_types.h
  119. +70 −0 usr/src/compat/freebsd/sys/callout.h
  120. +58 −0 usr/src/compat/freebsd/sys/cdefs.h
  121. +44 −0 usr/src/compat/freebsd/sys/cpuset.h
  122. +19 −0 usr/src/compat/freebsd/sys/disk.h
  123. +125 −0 usr/src/compat/freebsd/sys/endian.h
  124. +27 −0 usr/src/compat/freebsd/sys/errno.h
  125. +23 −0 usr/src/compat/freebsd/sys/fcntl.h
  126. +22 −0 usr/src/compat/freebsd/sys/ioctl.h
  127. +25 −0 usr/src/compat/freebsd/sys/kernel.h
  128. +27 −0 usr/src/compat/freebsd/sys/ktr.h
  129. +25 −0 usr/src/compat/freebsd/sys/libkern.h
  130. +19 −0 usr/src/compat/freebsd/sys/limits.h
  131. +44 −0 usr/src/compat/freebsd/sys/malloc.h
  132. +19 −0 usr/src/compat/freebsd/sys/module.h
  133. +81 −0 usr/src/compat/freebsd/sys/mutex.h
  134. +48 −0 usr/src/compat/freebsd/sys/param.h
  135. +21 −0 usr/src/compat/freebsd/sys/pcpu.h
  136. +19 −0 usr/src/compat/freebsd/sys/sched.h
  137. +23 −0 usr/src/compat/freebsd/sys/select.h
  138. +28 −0 usr/src/compat/freebsd/sys/smp.h
  139. +27 −0 usr/src/compat/freebsd/sys/sysctl.h
  140. +53 −0 usr/src/compat/freebsd/sys/systm.h
  141. +104 −0 usr/src/compat/freebsd/sys/time.h
  142. +74 −0 usr/src/compat/freebsd/sys/types.h
  143. +26 −0 usr/src/compat/freebsd/sys/uio.h
  144. +23 −0 usr/src/compat/freebsd/termios.h
  145. +55 −0 usr/src/compat/freebsd/uuid.h
  146. +21 −0 usr/src/compat/freebsd/vm/pmap.h
  147. +39 −0 usr/src/compat/freebsd/vm/vm.h
  148. +49 −0 usr/src/compat/freebsd/x86/_types.h
  149. +28 −0 usr/src/compat/freebsd/x86/segments.h
  150. +25 −0 usr/src/head/bhyve.h
  151. +49 −0 usr/src/lib/libvmmapi/Makefile
  152. +53 −0 usr/src/lib/libvmmapi/Makefile.com
  153. +21 −0 usr/src/lib/libvmmapi/amd64/Makefile
  154. +2 −0 usr/src/lib/libvmmapi/common/llib-lvmmapi
  155. +77 −0 usr/src/lib/libvmmapi/common/mapfile-vers
  156. +1,257 −0 usr/src/lib/libvmmapi/common/vmmapi.c
  157. +159 −0 usr/src/lib/libvmmapi/common/vmmapi.h
  158. +31 −0 usr/src/tools/scripts/gensetdefs.pl
  159. +1,404 −0 usr/src/uts/i86pc/io/viona/viona.c
  160. +14 −0 usr/src/uts/i86pc/io/viona/viona.conf
  161. +271 −0 usr/src/uts/i86pc/io/vmm/amd/amdv.c
  162. +452 −0 usr/src/uts/i86pc/io/vmm/intel/ept.c
  163. +43 −0 usr/src/uts/i86pc/io/vmm/intel/ept.h
  164. +597 −0 usr/src/uts/i86pc/io/vmm/intel/vmcs.c
  165. +410 −0 usr/src/uts/i86pc/io/vmm/intel/vmcs.h
  166. +2,842 −0 usr/src/uts/i86pc/io/vmm/intel/vmx.c
  167. +156 −0 usr/src/uts/i86pc/io/vmm/intel/vmx.h
  168. +96 −0 usr/src/uts/i86pc/io/vmm/intel/vmx_controls.h
  169. +245 −0 usr/src/uts/i86pc/io/vmm/intel/vmx_cpufunc.h
  170. +445 −0 usr/src/uts/i86pc/io/vmm/intel/vmx_msr.c
  171. +70 −0 usr/src/uts/i86pc/io/vmm/intel/vmx_msr.h
  172. +271 −0 usr/src/uts/i86pc/io/vmm/intel/vmx_support.s
  173. +809 −0 usr/src/uts/i86pc/io/vmm/io/vatpic.c
  174. +57 −0 usr/src/uts/i86pc/io/vmm/io/vatpic.h
  175. +458 −0 usr/src/uts/i86pc/io/vmm/io/vatpit.c
  176. +45 −0 usr/src/uts/i86pc/io/vmm/io/vatpit.h
  177. +282 −0 usr/src/uts/i86pc/io/vmm/io/vdev.c
  178. +96 −0 usr/src/uts/i86pc/io/vmm/io/vdev.h
  179. +821 −0 usr/src/uts/i86pc/io/vmm/io/vhpet.c
  180. +44 −0 usr/src/uts/i86pc/io/vmm/io/vhpet.h
  181. +514 −0 usr/src/uts/i86pc/io/vmm/io/vioapic.c
  182. +66 −0 usr/src/uts/i86pc/io/vmm/io/vioapic.h
  183. +1,687 −0 usr/src/uts/i86pc/io/vmm/io/vlapic.c
  184. +109 −0 usr/src/uts/i86pc/io/vmm/io/vlapic.h
  185. +190 −0 usr/src/uts/i86pc/io/vmm/io/vlapic_priv.h
  186. +72 −0 usr/src/uts/i86pc/io/vmm/offsets.in
  187. +1,894 −0 usr/src/uts/i86pc/io/vmm/vmm.c
  188. +1 −0 usr/src/uts/i86pc/io/vmm/vmm.conf
  189. +160 −0 usr/src/uts/i86pc/io/vmm/vmm_host.c
  190. +119 −0 usr/src/uts/i86pc/io/vmm/vmm_host.h
  191. +2,370 −0 usr/src/uts/i86pc/io/vmm/vmm_instruction_emul.c
  192. +174 −0 usr/src/uts/i86pc/io/vmm/vmm_ioport.c
  193. +37 −0 usr/src/uts/i86pc/io/vmm/vmm_ioport.h
  194. +37 −0 usr/src/uts/i86pc/io/vmm/vmm_ipi.h
  195. +69 −0 usr/src/uts/i86pc/io/vmm/vmm_ktr.h
  196. +256 −0 usr/src/uts/i86pc/io/vmm/vmm_lapic.c
  197. +87 −0 usr/src/uts/i86pc/io/vmm/vmm_lapic.h
  198. +49 −0 usr/src/uts/i86pc/io/vmm/vmm_mem.h
  199. +1,040 −0 usr/src/uts/i86pc/io/vmm/vmm_sol_dev.c
  200. +779 −0 usr/src/uts/i86pc/io/vmm/vmm_sol_glue.c
  201. +111 −0 usr/src/uts/i86pc/io/vmm/vmm_sol_mem.c
  202. +127 −0 usr/src/uts/i86pc/io/vmm/vmm_stat.h
  203. +125 −0 usr/src/uts/i86pc/io/vmm/vmm_util.c
  204. +40 −0 usr/src/uts/i86pc/io/vmm/vmm_util.h
  205. +1 −0 usr/src/uts/i86pc/io/vmm/vmx_assym.s
  206. +276 −0 usr/src/uts/i86pc/io/vmm/x86.c
  207. +65 −0 usr/src/uts/i86pc/io/vmm/x86.h
  208. +12 −2 usr/src/uts/i86pc/sys/Makefile
  209. +45 −0 usr/src/uts/i86pc/sys/viona_io.h
  210. +565 −0 usr/src/uts/i86pc/sys/vmm.h
  211. +334 −0 usr/src/uts/i86pc/sys/vmm_dev.h
  212. +86 −0 usr/src/uts/i86pc/sys/vmm_impl.h
  213. +126 −0 usr/src/uts/i86pc/sys/vmm_instruction_emul.h
  214. +72 −0 usr/src/uts/i86pc/viona/Makefile
  215. +94 −0 usr/src/uts/i86pc/vmm/Makefile
@@ -0,0 +1,6 @@
/*-
* This file is in the public domain.
*/
/* $FreeBSD: head/sys/amd64/include/_types.h 232261 2012-02-28 18:15:28Z tijl $ */
#include <x86/_types.h>
@@ -0,0 +1,6 @@
/*-
* This file is in the public domain.
*/
/* $FreeBSD: head/sys/amd64/include/psl.h 233204 2012-03-19 21:29:57Z tijl $ */
#include <x86/psl.h>
@@ -0,0 +1,6 @@
/*-
* This file is in the public domain.
*/
/* $FreeBSD: head/sys/amd64/include/specialreg.h 233207 2012-03-19 21:34:11Z tijl $ */
#include <x86/specialreg.h>
@@ -0,0 +1,54 @@
/*-
* Copyright (C) 2005 TAKAHASHI Yoshihiro. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: head/sys/amd64/include/timerreg.h 177642 2008-03-26 20:09:21Z phk $
*/
/*
* The outputs of the three timers are connected as follows:
*
* timer 0 -> irq 0
* timer 1 -> dma chan 0 (for dram refresh)
* timer 2 -> speaker (via keyboard controller)
*
* Timer 0 is used to call hardclock.
* Timer 2 is used to generate console beeps.
*/
#ifndef _MACHINE_TIMERREG_H_
#define _MACHINE_TIMERREG_H_
#ifdef _KERNEL
#include <dev/ic/i8253reg.h>
#define IO_TIMER1 0x40 /* 8253 Timer #1 */
#define TIMER_CNTR0 (IO_TIMER1 + TIMER_REG_CNTR0)
#define TIMER_CNTR1 (IO_TIMER1 + TIMER_REG_CNTR1)
#define TIMER_CNTR2 (IO_TIMER1 + TIMER_REG_CNTR2)
#define TIMER_MODE (IO_TIMER1 + TIMER_REG_MODE)
#endif /* _KERNEL */
#endif /* _MACHINE_TIMERREG_H_ */
@@ -0,0 +1,45 @@
/*-
* Copyright (c) 2009 Advanced Computing Technologies LLC
* Written by: John H. Baldwin <jhb@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: head/sys/amd64/include/vm.h 233671 2012-03-29 16:51:22Z jhb $
*/
#ifndef _MACHINE_VM_H_
#define _MACHINE_VM_H_
#include <machine/specialreg.h>
/* Memory attributes. */
#define VM_MEMATTR_UNCACHEABLE ((vm_memattr_t)PAT_UNCACHEABLE)
#define VM_MEMATTR_WRITE_COMBINING ((vm_memattr_t)PAT_WRITE_COMBINING)
#define VM_MEMATTR_WRITE_THROUGH ((vm_memattr_t)PAT_WRITE_THROUGH)
#define VM_MEMATTR_WRITE_PROTECTED ((vm_memattr_t)PAT_WRITE_PROTECTED)
#define VM_MEMATTR_WRITE_BACK ((vm_memattr_t)PAT_WRITE_BACK)
#define VM_MEMATTR_WEAK_UNCACHEABLE ((vm_memattr_t)PAT_UNCACHED)
#define VM_MEMATTR_DEFAULT VM_MEMATTR_WRITE_BACK
#endif /* !_MACHINE_VM_H_ */
@@ -0,0 +1,67 @@
/*-
* Copyright (c) 2005 Poul-Henning Kamp
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: head/sys/dev/acpica/acpi_hpet.h 224919 2011-08-16 21:51:29Z mav $
*/
#ifndef __ACPI_HPET_H__
#define __ACPI_HPET_H__
#define HPET_MEM_WIDTH 0x400 /* Expected memory region size */
/* General registers */
#define HPET_CAPABILITIES 0x0 /* General capabilities and ID */
#define HPET_CAP_VENDOR_ID 0xffff0000
#define HPET_CAP_LEG_RT 0x00008000
#define HPET_CAP_COUNT_SIZE 0x00002000 /* 1 = 64-bit, 0 = 32-bit */
#define HPET_CAP_NUM_TIM 0x00001f00
#define HPET_CAP_REV_ID 0x000000ff
#define HPET_PERIOD 0x4 /* Period (1/hz) of timer */
#define HPET_CONFIG 0x10 /* General configuration register */
#define HPET_CNF_LEG_RT 0x00000002
#define HPET_CNF_ENABLE 0x00000001
#define HPET_ISR 0x20 /* General interrupt status register */
#define HPET_MAIN_COUNTER 0xf0 /* Main counter register */
/* Timer registers */
#define HPET_TIMER_CAP_CNF(x) ((x) * 0x20 + 0x100)
#define HPET_TCAP_INT_ROUTE 0xffffffff00000000
#define HPET_TCAP_FSB_INT_DEL 0x00008000
#define HPET_TCNF_FSB_EN 0x00004000
#define HPET_TCNF_INT_ROUTE 0x00003e00
#define HPET_TCNF_32MODE 0x00000100
#define HPET_TCNF_VAL_SET 0x00000040
#define HPET_TCAP_SIZE 0x00000020 /* 1 = 64-bit, 0 = 32-bit */
#define HPET_TCAP_PER_INT 0x00000010 /* Supports periodic interrupts */
#define HPET_TCNF_TYPE 0x00000008 /* 1 = periodic, 0 = one-shot */
#define HPET_TCNF_INT_ENB 0x00000004
#define HPET_TCNF_INT_TYPE 0x00000002 /* 1 = level triggered, 0 = edge */
#define HPET_TIMER_COMPARATOR(x) ((x) * 0x20 + 0x108)
#define HPET_TIMER_FSB_VAL(x) ((x) * 0x20 + 0x110)
#define HPET_TIMER_FSB_ADDR(x) ((x) * 0x20 + 0x114)
#define HPET_MIN_CYCLES 128 /* Period considered reliable. */
#endif /* !__ACPI_HPET_H__ */
@@ -0,0 +1,78 @@
/*-
* Copyright (c) 1993 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp
* $FreeBSD: head/sys/dev/ic/i8253reg.h 146215 2005-05-14 10:26:31Z nyan $
*/
/*
* Register definitions for the Intel 8253 Programmable Interval Timer.
*
* This chip has three independent 16-bit down counters that can be
* read on the fly. There are three mode registers and three countdown
* registers. The countdown registers are addressed directly, via the
* first three I/O ports. The three mode registers are accessed via
* the fourth I/O port, with two bits in the mode byte indicating the
* register. (Why are hardware interfaces always so braindead?).
*
* To write a value into the countdown register, the mode register
* is first programmed with a command indicating the which byte of
* the two byte register is to be modified. The three possibilities
* are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then
* msb (TMR_MR_BOTH).
*
* To read the current value ("on the fly") from the countdown register,
* you write a "latch" command into the mode register, then read the stable
* value from the corresponding I/O port. For example, you write
* TMR_MR_LATCH into the corresponding mode register. Presumably,
* after doing this, a write operation to the I/O port would result
* in undefined behavior (but hopefully not fry the chip).
* Reading in this manner has no side effects.
*/
/*
* Macros for specifying values to be written into a mode register.
*/
#define TIMER_REG_CNTR0 0 /* timer 0 counter port */
#define TIMER_REG_CNTR1 1 /* timer 1 counter port */
#define TIMER_REG_CNTR2 2 /* timer 2 counter port */
#define TIMER_REG_MODE 3 /* timer mode port */
#define TIMER_SEL0 0x00 /* select counter 0 */
#define TIMER_SEL1 0x40 /* select counter 1 */
#define TIMER_SEL2 0x80 /* select counter 2 */
#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */
#define TIMER_ONESHOT 0x02 /* mode 1, one shot */
#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */
#define TIMER_SQWAVE 0x06 /* mode 3, square wave */
#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */
#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */
#define TIMER_LATCH 0x00 /* latch counter for reading */
#define TIMER_LSB 0x10 /* r/w counter LSB */
#define TIMER_MSB 0x20 /* r/w counter MSB */
#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */
#define TIMER_BCD 0x01 /* count in BCD */
@@ -0,0 +1,86 @@
/*-
* Copyright (c) 2003 Peter Wemm
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: head/sys/dev/ic/i8259.h 151580 2005-10-23 09:05:51Z glebius $
*/
/*
* Register defintions for the i8259A programmable interrupt controller.
*/
#ifndef _DEV_IC_I8259_H_
#define _DEV_IC_I8259_H_
/* Initialization control word 1. Written to even address. */
#define ICW1_IC4 0x01 /* ICW4 present */
#define ICW1_SNGL 0x02 /* 1 = single, 0 = cascaded */
#define ICW1_ADI 0x04 /* 1 = 4, 0 = 8 byte vectors */
#define ICW1_LTIM 0x08 /* 1 = level trigger, 0 = edge */
#define ICW1_RESET 0x10 /* must be 1 */
/* 0x20 - 0x80 - in 8080/8085 mode only */
/* Initialization control word 2. Written to the odd address. */
/* No definitions, it is the base vector of the IDT for 8086 mode */
/* Initialization control word 3. Written to the odd address. */
/* For a master PIC, bitfield indicating a slave 8259 on given input */
/* For slave, lower 3 bits are the slave's ID binary id on master */
/* Initialization control word 4. Written to the odd address. */
#define ICW4_8086 0x01 /* 1 = 8086, 0 = 8080 */
#define ICW4_AEOI 0x02 /* 1 = Auto EOI */
#define ICW4_MS 0x04 /* 1 = buffered master, 0 = slave */
#define ICW4_BUF 0x08 /* 1 = enable buffer mode */
#define ICW4_SFNM 0x10 /* 1 = special fully nested mode */
/* Operation control words. Written after initialization. */
/* Operation control word type 1 */
/*
* No definitions. Written to the odd address. Bitmask for interrupts.
* 1 = disabled.
*/
/* Operation control word type 2. Bit 3 (0x08) must be zero. Even address. */
#define OCW2_L0 0x01 /* Level */
#define OCW2_L1 0x02
#define OCW2_L2 0x04
/* 0x08 must be 0 to select OCW2 vs OCW3 */
/* 0x10 must be 0 to select OCW2 vs ICW1 */
#define OCW2_EOI 0x20 /* 1 = EOI */
#define OCW2_SL 0x40 /* EOI mode */
#define OCW2_R 0x80 /* EOI mode */
/* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */
#define OCW3_RIS 0x01 /* 1 = read IS, 0 = read IR */
#define OCW3_RR 0x02 /* register read */
#define OCW3_P 0x04 /* poll mode command */
/* 0x08 must be 1 to select OCW3 vs OCW2 */
#define OCW3_SEL 0x08 /* must be 1 */
/* 0x10 must be 0 to select OCW3 vs ICW1 */
#define OCW3_SMM 0x20 /* special mode mask */
#define OCW3_ESMM 0x40 /* enable SMM */
#endif /* !_DEV_IC_I8259_H_ */
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