234 usr/src/uts/common/io/bge/bge_chip2.c
View file
@@ -24,7 +24,7 @@
*/

/*
* Copyright 2011 Nexenta Systems, Inc. All rights reserved.
* Copyright 2011, 2012 Nexenta Systems, Inc. All rights reserved.
*/

#include "bge_impl.h"
@@ -363,7 +363,34 @@ bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
if (DEVICE_5717_SERIES_CHIPSETS(bgep))
pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK;
cidp->asic_rev = (mhcr & MHCR_CHIP_REV_MASK) >> MHCR_CHIP_REV_SHIFT;
if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_PRODID) {
uint32_t reg;
switch (cidp->device) {
case DEVICE_ID_5717:
case DEVICE_ID_5718:
case DEVICE_ID_5719:
case DEVICE_ID_5720:
reg = PCI_CONF_GEN2_PRODID_ASICREV;
break;
case DEVICE_ID_57781:
case DEVICE_ID_57785:
case DEVICE_ID_57761:
case DEVICE_ID_57765:
case DEVICE_ID_57791:
case DEVICE_ID_57795:
case DEVICE_ID_57762:
case DEVICE_ID_57766:
case DEVICE_ID_57782:
case DEVICE_ID_57786:
reg = PCI_CONF_GEN15_PRODID_ASICREV;
break;
default:
reg = PCI_CONF_PRODID_ASICREV;
break;
}
cidp->asic_rev = pci_config_get32(handle, reg);
}
cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
cidp->command = pci_config_get16(handle, PCI_CONF_COMM);

@@ -386,6 +413,45 @@ bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
cidp->clsize, cidp->latency, cidp->command));

cidp->chip_type = 0;
if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5717 ||
MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5719 ||
MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5720)
cidp->chip_type |= CHIP_TYPE_5717_PLUS;

if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_57765 ||
MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_57766)
cidp->chip_type |= CHIP_TYPE_57765_CLASS;

if (cidp->chip_type & CHIP_TYPE_57765_CLASS ||
cidp->chip_type & CHIP_TYPE_5717_PLUS)
cidp->chip_type |= CHIP_TYPE_57765_PLUS;

/* Intentionally exclude ASIC_REV_5906 */
if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5755 ||
MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5787 ||
MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5784 ||
MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5761 ||
MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5785 ||
MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_57780 ||
cidp->chip_type & CHIP_TYPE_57765_PLUS)
cidp->chip_type |= CHIP_TYPE_5755_PLUS;

if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5780 ||
MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5714)
cidp->chip_type |= CHIP_TYPE_5780_CLASS;

if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5750 ||
MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5752 ||
MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5906 ||
cidp->chip_type & CHIP_TYPE_5755_PLUS ||
cidp->chip_type & CHIP_TYPE_5780_CLASS)
cidp->chip_type |= CHIP_TYPE_5750_PLUS;

if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5705 ||
cidp->chip_type & CHIP_TYPE_5750_PLUS)
cidp->chip_type |= CHIP_TYPE_5705_PLUS;

/*
* Step 2 (also step 6): disable and clear interrupts.
* Steps 11-13: configure PIO endianness options, and enable
@@ -445,8 +511,9 @@ bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
* see whether the host is truly up to date, and regenerate
* its interrupt if not.
*/
mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
MHCR_ENABLE_TAGGED_STATUS_MODE |
MHCR_ENABLE_PCI_STATE_WRITE |
MHCR_MASK_INTERRUPT_MODE |
MHCR_CLEAR_INTERRUPT_INTA;

@@ -1896,10 +1963,16 @@ bge_nvmem_id(bge_t *bgep)
case DEVICE_ID_5705_2:
case DEVICE_ID_5717:
case DEVICE_ID_5718:
case DEVICE_ID_5719:
case DEVICE_ID_5720:
case DEVICE_ID_5724:
case DEVICE_ID_57760:
case DEVICE_ID_57780:
case DEVICE_ID_57788:
case DEVICE_ID_57790:
case DEVICE_ID_5780:
case DEVICE_ID_5782:
case DEVICE_ID_5784M:
case DEVICE_ID_5785:
case DEVICE_ID_5787:
case DEVICE_ID_5787M:
@@ -1918,6 +1991,8 @@ bge_nvmem_id(bge_t *bgep)
case DEVICE_ID_5723:
case DEVICE_ID_5761:
case DEVICE_ID_5761E:
case DEVICE_ID_5761S:
case DEVICE_ID_5761SE:
case DEVICE_ID_5764:
case DEVICE_ID_5714C:
case DEVICE_ID_5714S:
@@ -2023,14 +2098,35 @@ bge_chip_id_init(bge_t *bgep)

cidp->msi_enabled = B_FALSE;

if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) >
MHCR_CHIP_ASIC_REV_PRODID ||
MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5906 ||
MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5700 ||
MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5701 ||
MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5750)
/*
* Just a plain reset; the "check" code breaks these chips
*/
cidp->flags |= CHIP_FLAG_NO_CHECK_RESET;

switch (cidp->device) {
case DEVICE_ID_5717:
case DEVICE_ID_5718:
case DEVICE_ID_5719:
case DEVICE_ID_5720:
case DEVICE_ID_5724:
if (cidp->device == DEVICE_ID_5717)
cidp->chip_label = 5717;
else if (cidp->device == DEVICE_ID_5718)
cidp->chip_label = 5718;
else if (cidp->device == DEVICE_ID_5719)
cidp->chip_label = 5719;
else if (cidp->device == DEVICE_ID_5720)
cidp->chip_label = 5720;
else
cidp->chip_label = 5724;
cidp->msi_enabled = bge_enable_msi;
@@ -2044,7 +2140,7 @@ bge_chip_id_init(bge_t *bgep)
cidp->mbuf_hi_water = MBUF_HIWAT_5717;
cidp->mbuf_base = bge_mbuf_pool_base_5705;
cidp->mbuf_length = bge_mbuf_pool_len_5705;
cidp->recv_slots = BGE_RECV_SLOTS_5705;
cidp->recv_slots = BGE_RECV_SLOTS_5717;
cidp->bge_mlcr_default = MLCR_DEFAULT_5717;
cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
@@ -2220,7 +2316,13 @@ bge_chip_id_init(bge_t *bgep)
case DEVICE_ID_5723:
case DEVICE_ID_5761:
case DEVICE_ID_5761E:
case DEVICE_ID_5761S:
case DEVICE_ID_5761SE:
case DEVICE_ID_5784M:
case DEVICE_ID_57760:
case DEVICE_ID_57780:
case DEVICE_ID_57788:
case DEVICE_ID_57790:
cidp->msi_enabled = bge_enable_msi;
/*
* We don't use MSI for BCM5764 and BCM5785, as the
@@ -2234,10 +2336,18 @@ bge_chip_id_init(bge_t *bgep)
cidp->chip_label = 5723;
else if (cidp->device == DEVICE_ID_5764)
cidp->chip_label = 5764;
else if (cidp->device == DEVICE_ID_5784M)
cidp->chip_label = 5784;
else if (cidp->device == DEVICE_ID_5785)
cidp->chip_label = 5785;
else if (cidp->device == DEVICE_ID_57760)
cidp->chip_label = 57760;
else if (cidp->device == DEVICE_ID_57780)
cidp->chip_label = 57780;
else if (cidp->device == DEVICE_ID_57788)
cidp->chip_label = 57788;
else if (cidp->device == DEVICE_ID_57790)
cidp->chip_label = 57790;
else
cidp->chip_label = 5761;
cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
@@ -3401,18 +3511,27 @@ bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
MHCR_ENABLE_TAGGED_STATUS_MODE |
MHCR_MASK_INTERRUPT_MODE |
MHCR_MASK_PCI_INT_OUTPUT |
MHCR_CLEAR_INTERRUPT_INTA |
MHCR_ENABLE_ENDIAN_WORD_SWAP |
MHCR_ENABLE_ENDIAN_BYTE_SWAP;

if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
mhcr |= MHCR_MASK_PCI_INT_OUTPUT;

if (DEVICE_5717_SERIES_CHIPSETS(bgep))
pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR,
0);
#else
mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
MHCR_ENABLE_TAGGED_STATUS_MODE |
MHCR_MASK_INTERRUPT_MODE |
MHCR_MASK_PCI_INT_OUTPUT |
MHCR_CLEAR_INTERRUPT_INTA;
#endif
pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) |
MEMORY_ARBITER_ENABLE);
#endif
if (asf_mode == ASF_MODE_INIT) {
bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
} else if (asf_mode == ASF_MODE_SHUTDOWN) {
@@ -3436,9 +3555,13 @@ bge_chip_reset(bge_t *bgep, boolean_t enable_dma)

mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
MHCR_ENABLE_TAGGED_STATUS_MODE |
MHCR_ENABLE_PCI_STATE_WRITE |
MHCR_MASK_INTERRUPT_MODE |
MHCR_MASK_PCI_INT_OUTPUT |
MHCR_CLEAR_INTERRUPT_INTA;

if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
mhcr |= MHCR_MASK_PCI_INT_OUTPUT;

#ifdef _BIG_ENDIAN
mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
#endif /* _BIG_ENDIAN */
@@ -3449,6 +3572,12 @@ bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
if (bgep->asf_enabled)
bgep->asf_wordswapped = B_FALSE;
#endif

if (DEVICE_IS_5755_PLUS(bgep) ||
MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5752)
bge_reg_put32(bgep, GRC_FASTBOOT_PC, 0);

/*
* NVRAM Corruption Workaround
*/
@@ -3508,6 +3637,11 @@ bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
#else
modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME;
#endif /* _BIG_ENDIAN */
if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5720)
modeflags |=
MODE_BYTE_SWAP_B2HRX_DATA | MODE_WORD_SWAP_B2HRX_DATA |
MODE_B2HRX_ENABLE | MODE_HTX2B_ENABLE;
#ifdef BGE_IPMI_ASF
if (bgep->asf_enabled)
modeflags |= MODE_HOST_STACK_UP;
@@ -3592,6 +3726,13 @@ bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
*/
bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);

if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5720) {
uint32_t regval = bge_reg_get32(bgep, CPMU_CLCK_ORIDE_REG);
bge_reg_put32(bgep, CPMU_CLCK_ORIDE_REG,
regval & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
}

/*
* Step 21: restore cache-line-size, latency timer, and
* subsystem ID registers to their original values (not
@@ -3818,8 +3959,17 @@ bge_chip_start(bge_t *bgep, boolean_t reset_phys)
/*
* Steps 34-36: enable buffer manager & internal h/w queues
*/
if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG,
STATE_MACHINE_ATTN_ENABLE_BIT))

regval = STATE_MACHINE_ATTN_ENABLE_BIT;
if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5719)
regval |= BUFF_MGR_NO_TX_UNDERRUN;
if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5717 ||
bgep->chipid.asic_rev == MHCR_CHIP_REV_5719_A0 ||
bgep->chipid.asic_rev == MHCR_CHIP_REV_5720_A0)
regval |= BUFF_MGR_MBUF_LOW_ATTN_ENABLE;
if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, regval))
retval = DDI_FAILURE;
if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0))
retval = DDI_FAILURE;
@@ -3913,7 +4063,13 @@ bge_chip_start(bge_t *bgep, boolean_t reset_phys)
/*
* Step 50: configure the IPG et al
*/
bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
regval = MAC_TX_LENGTHS_DEFAULT;
if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)
== MHCR_CHIP_ASIC_REV_5720)
regval |= bge_reg_get32(bgep, MAC_TX_LENGTHS_REG) &
(MAC_TX_LENGTHS_JMB_FRM_LEN_MSK |
MAC_TX_LENGTHS_CNT_DWN_VAL_MSK);
bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, regval);

/*
* Step 51: configure the default Rx Return Ring
@@ -4068,22 +4224,45 @@ bge_chip_start(bge_t *bgep, boolean_t reset_phys)
retval = DDI_FAILURE;
dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) |
ALL_DMA_ATTN_BITS;
if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5755) ||
(MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5723) ||
(MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5906)) {
if (DEVICE_IS_5755_PLUS(bgep))
dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384;
}
if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
dma_wrprio))
retval = DDI_FAILURE;
if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5761 ||
MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5784 ||
MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5785 ||
MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_57780 ||
DEVICE_IS_57765_PLUS(bgep)) {
regval = bge_reg_get32(bgep, READ_DMA_RESERVED_CONTROL_REG);
if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5719 ||
MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5720) {
regval &= ~(RDMA_RSRVCTRL_TXMRGN_MASK |
RDMA_RSRVCTRL_FIFO_LWM_MASK |
RDMA_RSRVCTRL_FIFO_HWM_MASK);
regval |= RDMA_RSRVCTRL_TXMRGN_320B |
RDMA_RSRVCTRL_FIFO_LWM_1_5K |
RDMA_RSRVCTRL_FIFO_HWM_1_5K;
}
bge_reg_put32(bgep, READ_DMA_RESERVED_CONTROL_REG,
regval | RDMA_RSRVCTRL_FIFO_OFLW_FIX);
}
if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
DEVICE_5717_SERIES_CHIPSETS(bgep))
bge_dma_rdprio = 0;
regval = bge_dma_rdprio << DMA_PRIORITY_SHIFT;
if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5720)
regval |= bge_reg_get32(bgep, READ_DMA_MODE_REG) &
DMA_H2BNC_VLAN_DET;
if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
(bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
regval | ALL_DMA_ATTN_BITS))
retval = DDI_FAILURE;
if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
STATE_MACHINE_ATTN_ENABLE_BIT))
@@ -4116,7 +4295,23 @@ bge_chip_start(bge_t *bgep, boolean_t reset_phys)
* Step 88: download firmware -- doesn't apply
* Steps 89-90: enable Transmit & Receive MAC Engines
*/
if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
if (DEVICE_IS_5755_PLUS(bgep) ||
MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5906) {
regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
regval |= TRANSMIT_MODE_MBUF_LOCKUP_FIX;
} else {
regval = 0;
}
if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5720) {
regval &= ~(TRANSMIT_MODE_HTX2B_JMB_FRM_LEN |
TRANSMIT_MODE_HTX2B_CNT_DN_MODE);
regval |= bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG) &
(TRANSMIT_MODE_HTX2B_JMB_FRM_LEN |
TRANSMIT_MODE_HTX2B_CNT_DN_MODE);
}
if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, regval))
retval = DDI_FAILURE;
#ifdef BGE_IPMI_ASF
if (!bgep->asf_enabled) {
@@ -4219,7 +4414,6 @@ bge_chip_start(bge_t *bgep, boolean_t reset_phys)
if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR,
bgep->chipid.mask_pci_int);

/*
* All done!
*/
218 usr/src/uts/common/io/bge/bge_hw.h
View file
@@ -23,6 +23,10 @@
* Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
*/

/*
* Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/

#ifndef _BGE_HW_H
#define _BGE_HW_H

@@ -68,9 +72,12 @@ extern "C" {
#define DEVICE_ID_5724 0x165c
#define DEVICE_ID_5705M 0x165d
#define DEVICE_ID_5705MA3 0x165e
#define DEVICE_ID_5719 0x1657
#define DEVICE_ID_5720 0x165f
#define DEVICE_ID_5705F 0x166e
#define DEVICE_ID_5780 0x166a
#define DEVICE_ID_5782 0x1696
#define DEVICE_ID_5784M 0x1698
#define DEVICE_ID_5785 0x1699
#define DEVICE_ID_5787 0x169b
#define DEVICE_ID_5787M 0x1693
@@ -92,12 +99,27 @@ extern "C" {
#define DEVICE_ID_5714S 0x1669
#define DEVICE_ID_5715C 0x1678
#define DEVICE_ID_5715S 0x1679
#define DEVICE_ID_5761E 0x1680
#define DEVICE_ID_5761 0x1681
#define DEVICE_ID_5761E 0x1680
#define DEVICE_ID_5761S 0x1688
#define DEVICE_ID_5761SE 0x1689
#define DEVICE_ID_5764 0x1684
#define DEVICE_ID_5906 0x1712
#define DEVICE_ID_5906M 0x1713
#define DEVICE_ID_57760 0x1690
#define DEVICE_ID_57780 0x1692
#define DEVICE_ID_57788 0x1691
#define DEVICE_ID_57790 0x1694
#define DEVICE_ID_57781 0x16b1
#define DEVICE_ID_57785 0x16b5
#define DEVICE_ID_57761 0x16b0
#define DEVICE_ID_57765 0x16b4
#define DEVICE_ID_57791 0x16b2
#define DEVICE_ID_57795 0x16b6
#define DEVICE_ID_57762 0x1682
#define DEVICE_ID_57766 0x1686
#define DEVICE_ID_57786 0x16b3
#define DEVICE_ID_57782 0x16b7

#define REVISION_ID_5700_B0 0x10
#define REVISION_ID_5700_B2 0x12
@@ -189,15 +211,23 @@ extern "C" {
#define DEVICE_5717_SERIES_CHIPSETS(bgep) \
(bgep->chipid.device == DEVICE_ID_5717) ||\
(bgep->chipid.device == DEVICE_ID_5718) ||\
(bgep->chipid.device == DEVICE_ID_5719) ||\
(bgep->chipid.device == DEVICE_ID_5720) ||\
(bgep->chipid.device == DEVICE_ID_5724)

#define DEVICE_5723_SERIES_CHIPSETS(bgep) \
((bgep->chipid.device == DEVICE_ID_5723) ||\
(bgep->chipid.device == DEVICE_ID_5761) ||\
(bgep->chipid.device == DEVICE_ID_5761E) ||\
(bgep->chipid.device == DEVICE_ID_5761S) ||\
(bgep->chipid.device == DEVICE_ID_5761SE) ||\
(bgep->chipid.device == DEVICE_ID_5764) ||\
(bgep->chipid.device == DEVICE_ID_5784M) ||\
(bgep->chipid.device == DEVICE_ID_5785) ||\
(bgep->chipid.device == DEVICE_ID_57780))
(bgep->chipid.device == DEVICE_ID_57760) ||\
(bgep->chipid.device == DEVICE_ID_57780) ||\
(bgep->chipid.device == DEVICE_ID_57788) ||\
(bgep->chipid.device == DEVICE_ID_57790))

#define DEVICE_5714_SERIES_CHIPSETS(bgep) \
((bgep->chipid.device == DEVICE_ID_5714C) ||\
@@ -209,6 +239,20 @@ extern "C" {
((bgep->chipid.device == DEVICE_ID_5906) ||\
(bgep->chipid.device == DEVICE_ID_5906M))


#define CHIP_TYPE_5705_PLUS (1 << 0)
#define CHIP_TYPE_5750_PLUS (1 << 1)
#define CHIP_TYPE_5780_CLASS (1 << 2)
#define CHIP_TYPE_5755_PLUS (1 << 3)
#define CHIP_TYPE_57765_CLASS (1 << 4)
#define CHIP_TYPE_57765_PLUS (1 << 5)
#define CHIP_TYPE_5717_PLUS (1 << 6)

#define DEVICE_IS_57765_PLUS(bgep) \
(bgep->chipid.chip_type & CHIP_TYPE_57765_PLUS)
#define DEVICE_IS_5755_PLUS(bgep) \
(bgep->chipid.chip_type & CHIP_TYPE_5755_PLUS)

/*
* Second section:
* Offsets of important registers & definitions for bits therein
@@ -225,6 +269,7 @@ extern "C" {
*/
#define PCI_CONF_BGE_MHCR 0x68
#define MHCR_CHIP_REV_MASK 0xffff0000
#define MHCR_CHIP_REV_SHIFT 16
#define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200
#define MHCR_MASK_INTERRUPT_MODE 0x00000100
#define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080
@@ -236,95 +281,38 @@ extern "C" {
#define MHCR_MASK_PCI_INT_OUTPUT 0x00000002
#define MHCR_CLEAR_INTERRUPT_INTA 0x00000001

#define MHCR_CHIP_REV_5700_B0 0x71000000
#define MHCR_CHIP_REV_5700_B2 0x71020000
#define MHCR_CHIP_REV_5700_B3 0x71030000
#define MHCR_CHIP_REV_5700_C0 0x72000000
#define MHCR_CHIP_REV_5700_C1 0x72010000
#define MHCR_CHIP_REV_5700_C2 0x72020000

#define MHCR_CHIP_REV_5701_A0 0x00000000
#define MHCR_CHIP_REV_5701_A2 0x00020000
#define MHCR_CHIP_REV_5701_A3 0x00030000
#define MHCR_CHIP_REV_5701_A5 0x01050000

#define MHCR_CHIP_REV_5702_A0 0x10000000
#define MHCR_CHIP_REV_5702_A1 0x10010000
#define MHCR_CHIP_REV_5702_A2 0x10020000

#define MHCR_CHIP_REV_5703_A0 0x10000000
#define MHCR_CHIP_REV_5703_A1 0x10010000
#define MHCR_CHIP_REV_5703_A2 0x10020000
#define MHCR_CHIP_REV_5703_B0 0x11000000
#define MHCR_CHIP_REV_5703_B1 0x11010000

#define MHCR_CHIP_REV_5704_A0 0x20000000
#define MHCR_CHIP_REV_5704_A1 0x20010000
#define MHCR_CHIP_REV_5704_A2 0x20020000
#define MHCR_CHIP_REV_5704_A3 0x20030000
#define MHCR_CHIP_REV_5704_B0 0x21000000

#define MHCR_CHIP_REV_5705_A0 0x30000000
#define MHCR_CHIP_REV_5705_A1 0x30010000
#define MHCR_CHIP_REV_5705_A2 0x30020000
#define MHCR_CHIP_REV_5705_A3 0x30030000
#define MHCR_CHIP_REV_5705_A5 0x30050000

#define MHCR_CHIP_REV_5782_A0 0x30030000
#define MHCR_CHIP_REV_5782_A1 0x30030088

#define MHCR_CHIP_REV_5788_A1 0x30050000

#define MHCR_CHIP_REV_5751_A0 0x40000000
#define MHCR_CHIP_REV_5751_A1 0x40010000

#define MHCR_CHIP_REV_5721_A0 0x41000000
#define MHCR_CHIP_REV_5721_A1 0x41010000

#define MHCR_CHIP_REV_5714_A0 0x50000000
#define MHCR_CHIP_REV_5714_A1 0x90010000

#define MHCR_CHIP_REV_5715_A0 0x50000000
#define MHCR_CHIP_REV_5715_A1 0x90010000

#define MHCR_CHIP_REV_5715S_A0 0x50000000
#define MHCR_CHIP_REV_5715S_A1 0x90010000

#define MHCR_CHIP_REV_5754_A0 0xb0000000
#define MHCR_CHIP_REV_5754_A1 0xb0010000

#define MHCR_CHIP_REV_5787_A0 0xb0000000
#define MHCR_CHIP_REV_5787_A1 0xb0010000
#define MHCR_CHIP_REV_5787_A2 0xb0020000

#define MHCR_CHIP_REV_5755_A0 0xa0000000
#define MHCR_CHIP_REV_5755_A1 0xa0010000

#define MHCR_CHIP_REV_5906_A0 0xc0000000
#define MHCR_CHIP_REV_5906_A1 0xc0010000
#define MHCR_CHIP_REV_5906_A2 0xc0020000

#define MHCR_CHIP_REV_5723_A0 0xf0000000
#define MHCR_CHIP_REV_5723_A1 0xf0010000
#define MHCR_CHIP_REV_5723_A2 0xf0020000
#define MHCR_CHIP_REV_5723_B0 0xf1000000

#define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000)
#define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28)
#define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28)
#define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28)
#define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28)
#define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28)
#define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28)
#define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28)
#define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28)
#define MHCR_CHIP_ASIC_REV_5754 (0xb << 28)
#define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28)
#define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28)
#define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28)
#define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28)
#define MHCR_CHIP_ASIC_REV_5723 ((uint32_t)0xf << 28)

#define MHCR_CHIP_REV_5703_A0 0x1000
#define MHCR_CHIP_REV_5704_A0 0x2000
#define MHCR_CHIP_REV_5751_A0 0x4000
#define MHCR_CHIP_REV_5721_A0 0x4100
#define MHCR_CHIP_REV_5755_A0 0xa000
#define MHCR_CHIP_REV_5755_A1 0xa001
#define MHCR_CHIP_REV_5719_A0 0x05719000
#define MHCR_CHIP_REV_5720_A0 0x05720000

#define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) >> 12)
#define MHCR_CHIP_ASIC_REV_5700 0x07
#define MHCR_CHIP_ASIC_REV_5701 0x00
#define MHCR_CHIP_ASIC_REV_5703 0x01
#define MHCR_CHIP_ASIC_REV_5704 0x02
#define MHCR_CHIP_ASIC_REV_5705 0x03
#define MHCR_CHIP_ASIC_REV_5750 0x04
#define MHCR_CHIP_ASIC_REV_5752 0x06
#define MHCR_CHIP_ASIC_REV_5780 0x08
#define MHCR_CHIP_ASIC_REV_5714 0x09
#define MHCR_CHIP_ASIC_REV_5755 0x0a
#define MHCR_CHIP_ASIC_REV_5787 0x0b
#define MHCR_CHIP_ASIC_REV_5906 0x0c
#define MHCR_CHIP_ASIC_REV_PRODID 0x0f
#define MHCR_CHIP_ASIC_REV_5784 0x5784
#define MHCR_CHIP_ASIC_REV_5761 0x5761
#define MHCR_CHIP_ASIC_REV_5785 0x5785
#define MHCR_CHIP_ASIC_REV_5717 0x5717
#define MHCR_CHIP_ASIC_REV_5719 0x5719
#define MHCR_CHIP_ASIC_REV_5720 0x5720
#define MHCR_CHIP_ASIC_REV_57780 0x57780
#define MHCR_CHIP_ASIC_REV_57765 0x57785
#define MHCR_CHIP_ASIC_REV_57766 0x57766

/*
* PCI DMA read/write Control Register, in PCI config space
@@ -466,6 +454,10 @@ extern "C" {
#define PCI_CONF_DEV_STUS_5723 0xd6
#define DEVICE_ERROR_STUS 0xf

#define PCI_CONF_PRODID_ASICREV 0x000000bc
#define PCI_CONF_GEN2_PRODID_ASICREV 0x000000f4
#define PCI_CONF_GEN15_PRODID_ASICREV 0x000000fc

#define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */

/*
@@ -541,6 +533,7 @@ extern "C" {
#define MEMORY_ARBITER_MODE_REG 0x4000
#define BUFFER_MANAGER_MODE_REG 0x4400
#define READ_DMA_MODE_REG 0x4800
#define READ_DMA_RESERVED_CONTROL_REG 0x4900
#define WRITE_DMA_MODE_REG 0x4c00
#define DMA_COMPLETION_MODE_REG 0x6400

@@ -552,6 +545,9 @@ extern "C" {
* Transmit MAC Mode Register
* (TRANSMIT_MAC_MODE_REG, 0x045c)
*/
#define TRANSMIT_MODE_HTX2B_CNT_DN_MODE 0x00800000
#define TRANSMIT_MODE_HTX2B_JMB_FRM_LEN 0x00400000
#define TRANSMIT_MODE_MBUF_LOCKUP_FIX 0x00000100
#define TRANSMIT_MODE_LONG_PAUSE 0x00000040
#define TRANSMIT_MODE_BIG_BACKOFF 0x00000020
#define TRANSMIT_MODE_FLOW_CONTROL 0x00000010
@@ -619,12 +615,14 @@ extern "C" {
*/
#define BUFF_MGR_TEST_MODE 0x00000008
#define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010
#define BUFF_MGR_NO_TX_UNDERRUN 0x80000000

#define BUFF_MGR_ALL_ATTN_BITS 0x00000014

/*
* Read and Write DMA Mode Registers (READ_DMA_MODE_REG,
* 0x4800 and WRITE_DMA_MODE_REG, 0x4c00)
* 0x4800, READ_DMA_RESERVED_CONTROL_REG, 0x4900,
* WRITE_DMA_MODE_REG, 0x4c00)
*
* These registers each contain a 2-bit priority field, which controls
* the relative priority of that type of DMA (read vs. write vs. MSI),
@@ -635,6 +633,15 @@ extern "C" {
#define DMA_PRIORITY_SHIFT 30
#define ALL_DMA_ATTN_BITS 0x000003fc

#define RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
#define RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
#define RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
#define RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
#define RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
#define RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
#define RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000


/*
* BCM5755, 5755M, 5906, 5906M only
* 1 - Enable Fix. Device will send out the status block before
@@ -644,6 +651,10 @@ extern "C" {
*/
#define DMA_STATUS_TAG_FIX_CQ12384 0x20000000

/* 5720 only */
#define DMA_H2BNC_VLAN_DET 0x20000000


/*
* End of state machine control register definitions
*/
@@ -781,6 +792,8 @@ extern "C" {
#define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */
#define MAC_TX_LENGTHS_REG 0x0464
#define MAC_TX_LENGTHS_DEFAULT 0x00002620
#define MAC_TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
#define MAC_TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000

/*
* MII access registers
@@ -1069,10 +1082,16 @@ extern "C" {
#define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */

/*
* CPMU registers (5717/5718 only)
* CPMU registers (5717/5718/5719/5720 only)
*/
#define CPMU_STATUS_REG 0x362c
#define CPMU_STATUS_FUN_NUM 0x20000000
#define CPMU_CLCK_ORIDE_REG 0x3624
#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000

#define CPMU_STATUS_REG 0x362c
#define CPMU_STATUS_FUN_NUM_5717 0x20000000
#define CPMU_STATUS_FUN_NUM_5719 0xc0000000
#define CPMU_STATUS_FUN_NUM_5719_SHIFT 30


/*
* Host Coalescing Engine Control Registers
@@ -1191,6 +1210,8 @@ extern "C" {
#define VCPU_EXT_CTL 0x6890
#define VCPU_EXT_CTL_HALF 0x00400000

#define GRC_FASTBOOT_PC 0x6894

#define FTQ_RESET_REG 0x5c00

#define MSI_MODE_REG 0x6000
@@ -1210,14 +1231,18 @@ extern "C" {
#define MODE_INT_ON_TXRISC_ATTN 0x01000000
#define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000
#define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000
#define MODE_HTX2B_ENABLE 0x00040000
#define MODE_HOST_SEND_BDS 0x00020000
#define MODE_HOST_STACK_UP 0x00010000
#define MODE_FORCE_32_BIT_PCI 0x00008000
#define MODE_B2HRX_ENABLE 0x00008000
#define MODE_NO_INT_ON_RECV 0x00004000
#define MODE_NO_INT_ON_SEND 0x00002000
#define MODE_ALLOW_BAD_FRAMES 0x00000800
#define MODE_NO_CRC 0x00000400
#define MODE_NO_FRAME_CRACKING 0x00000200
#define MODE_WORD_SWAP_B2HRX_DATA 0x00000080
#define MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
#define MODE_WORD_SWAP_FRAME 0x00000020
#define MODE_BYTE_SWAP_FRAME 0x00000010
#define MODE_WORD_SWAP_NONFRAME 0x00000004
@@ -1246,7 +1271,7 @@ extern "C" {
*/
#define CORE_CLOCK_MHZ 66
#define MISC_CONFIG_REG 0x6804
#define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000
#define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000
#define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000
#define MISC_CONFIG_POWERDOWN 0x00100000
#define MISC_CONFIG_POWER_STATE 0x00060000
@@ -1567,6 +1592,7 @@ extern "C" {
#define BGE_MINI_SLOTS_MAX 1024
#define BGE_RECV_SLOTS_MAX 2048
#define BGE_RECV_SLOTS_5705 512
#define BGE_RECV_SLOTS_5717 1024
#define BGE_RECV_SLOTS_5782 512
#define BGE_RECV_SLOTS_5721 512

14 usr/src/uts/common/io/bge/bge_impl.h
View file
@@ -23,6 +23,10 @@
* Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
*/

/*
* Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/

#ifndef _BGE_IMPL_H
#define _BGE_IMPL_H

@@ -605,6 +609,7 @@ typedef struct {
uint8_t latency; /* latency-timer */

uint8_t flags;
uint32_t chip_type; /* see CHIP_TYPE_ in bge_hw.h */
uint16_t chip_label; /* numeric part only */
/* (e.g. 5703/5794/etc) */
uint32_t mbuf_base; /* Mbuf pool parameters */
@@ -640,10 +645,11 @@ typedef struct {
uint32_t mask_pci_int;
} chip_id_t;

#define CHIP_FLAG_SUPPORTED 0x80
#define CHIP_FLAG_SERDES 0x40
#define CHIP_FLAG_PARTIAL_CSUM 0x20
#define CHIP_FLAG_NO_JUMBO 0x1
#define CHIP_FLAG_SUPPORTED 0x80
#define CHIP_FLAG_SERDES 0x40
#define CHIP_FLAG_PARTIAL_CSUM 0x20
#define CHIP_FLAG_NO_CHECK_RESET 0x2
#define CHIP_FLAG_NO_JUMBO 0x1

/*
* Collection of physical-layer functions to:
14 usr/src/uts/common/io/bge/bge_main2.c
View file
@@ -23,6 +23,10 @@
* Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
*/

/*
* Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/

#include "bge_impl.h"
#include <sys/sdt.h>
#include <sys/mac_provider.h>
@@ -3211,13 +3215,17 @@ bge_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
*/
if (DEVICE_5717_SERIES_CHIPSETS(bgep))
pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 0);
#else
mhcrValue = MHCR_ENABLE_INDIRECT_ACCESS |
MHCR_ENABLE_TAGGED_STATUS_MODE |
MHCR_MASK_INTERRUPT_MODE |
MHCR_MASK_PCI_INT_OUTPUT |
MHCR_CLEAR_INTERRUPT_INTA;
#endif
pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcrValue);
bge_ind_put32(bgep, MEMORY_ARBITER_MODE_REG,
bge_ind_get32(bgep, MEMORY_ARBITER_MODE_REG) |
MEMORY_ARBITER_ENABLE);
#else
mhcrValue = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR);
#endif
if (mhcrValue & MHCR_ENABLE_ENDIAN_WORD_SWAP) {
bgep->asf_wordswapped = B_TRUE;
} else {
71 usr/src/uts/common/io/bge/bge_mii.c
View file
@@ -23,6 +23,10 @@
* Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
*/

/*
* Copyright 2012 Nexenta Systems, Inc. All rights reserved.
*/

#include "bge_impl.h"

/*
@@ -207,6 +211,7 @@ bge_phy_reset(bge_t *bgep)
{
uint16_t control;
uint_t count;
boolean_t ret = B_FALSE;

BGE_TRACE(("bge_phy_reset($%p)", (void *)bgep));

@@ -221,22 +226,26 @@ bge_phy_reset(bge_t *bgep)
}

/*
* Set the PHY RESET bit, then wait up to 5 ms for it to self-clear
* Set the PHY RESET bit, then wait up to 50 ms for it to self-clear
*/
bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET);
for (count = 0; ++count < 1000; ) {
drv_usecwait(5);
for (count = 0; ++count < 5000; ) {
control = bge_mii_get16(bgep, MII_CONTROL);
if (BIC(control, MII_CONTROL_RESET))
return (B_TRUE);
if (BIC(control, MII_CONTROL_RESET)) {
drv_usecwait(40);
ret = B_TRUE;
break;
}
drv_usecwait(10);
}

if (DEVICE_5906_SERIES_CHIPSETS(bgep))
if (ret == B_TRUE && DEVICE_5906_SERIES_CHIPSETS(bgep))
(void) bge_adj_volt_5906(bgep);

BGE_DEBUG(("bge_phy_reset: FAILED, control now 0x%x", control));
if (ret == B_FALSE)
BGE_DEBUG(("bge_phy_reset: FAILED, control now 0x%x", control));

return (B_FALSE);
return (ret);
}

/*
@@ -541,34 +550,14 @@ bge_restart_copper(bge_t *bgep, boolean_t powerdown)

ASSERT(mutex_owned(bgep->genlock));

switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
default:
/*
* Shouldn't happen; it means we don't recognise this chip.
* It's probably a new one, so we'll try our best anyway ...
*/
case MHCR_CHIP_ASIC_REV_5703:
case MHCR_CHIP_ASIC_REV_5704:
case MHCR_CHIP_ASIC_REV_5705:
case MHCR_CHIP_ASIC_REV_5752:
case MHCR_CHIP_ASIC_REV_5714:
case MHCR_CHIP_ASIC_REV_5715:
reset_ok = bge_phy_reset_and_check(bgep);
break;

case MHCR_CHIP_ASIC_REV_5906:
case MHCR_CHIP_ASIC_REV_5700:
case MHCR_CHIP_ASIC_REV_5701:
case MHCR_CHIP_ASIC_REV_5723:
case MHCR_CHIP_ASIC_REV_5721_5751:
/*
* Just a plain reset; the "check" code breaks these chips
*/
if (bgep->chipid.flags & CHIP_FLAG_NO_CHECK_RESET) {
reset_ok = bge_phy_reset(bgep);
if (!reset_ok)
bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
break;
} else {
reset_ok = bge_phy_reset_and_check(bgep);
}

if (!reset_ok) {
BGE_REPORT((bgep, "PHY failed to reset correctly"));
return (DDI_FAILURE);
@@ -590,7 +579,7 @@ bge_restart_copper(bge_t *bgep, boolean_t powerdown)

switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
case MHCR_CHIP_ASIC_REV_5705:
case MHCR_CHIP_ASIC_REV_5721_5751:
case MHCR_CHIP_ASIC_REV_5750:
bge_phy_bit_err_fix(bgep);
break;
}
@@ -1507,14 +1496,22 @@ bge_phys_init(bge_t *bgep)
*/
bgep->phy_mii_addr = 1;
if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
int regval = bge_reg_get32(bgep, CPMU_STATUS_REG);
if (regval & CPMU_STATUS_FUN_NUM)
bgep->phy_mii_addr += 1;
uint32_t regval = bge_reg_get32(bgep, CPMU_STATUS_REG);
if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5719 ||
MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
MHCR_CHIP_ASIC_REV_5720) {
bgep->phy_mii_addr +=
(regval & CPMU_STATUS_FUN_NUM_5719) >>
CPMU_STATUS_FUN_NUM_5719_SHIFT;
} else {
bgep->phy_mii_addr +=
(regval & CPMU_STATUS_FUN_NUM_5717) ? 1 : 0;
}
regval = bge_reg_get32(bgep, SGMII_STATUS_REG);
if (regval & MEDIA_SELECTION_MODE)
bgep->phy_mii_addr += 7;
}

if (bge_phy_probe(bgep)) {
bgep->chipid.flags &= ~CHIP_FLAG_SERDES;
bgep->physops = &copper_ops;