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68396ea @rmustacc Initial commit of d32e8d0b8d9e0ef7cf7ab2e74548982972789dfc from qemu-kvm
rmustacc authored
1 /*
2 * Qemu PowerPC 440 chip emulation
3 *
4 * Copyright 2007 IBM Corporation.
5 * Authors:
6 * Jerone Young <jyoung5@us.ibm.com>
7 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
8 * Hollis Blanchard <hollisb@us.ibm.com>
9 *
10 * This work is licensed under the GNU GPL license version 2 or later.
11 *
12 */
13
14 #include "hw.h"
15 #include "pc.h"
16 #include "isa.h"
17 #include "ppc.h"
18 #include "ppc4xx.h"
19 #include "ppc440.h"
20 #include "ppc405.h"
21 #include "sysemu.h"
22 #include "kvm.h"
23 #include "qemu-kvm.h"
24
25 #define PPC440EP_PCI_CONFIG 0xeec00000
26 #define PPC440EP_PCI_INTACK 0xeed00000
27 #define PPC440EP_PCI_SPECIAL 0xeed00000
28 #define PPC440EP_PCI_REGS 0xef400000
29 #define PPC440EP_PCI_IO 0xe8000000
30 #define PPC440EP_PCI_IOLEN 0x00010000
31
32 #define PPC440EP_SDRAM_NR_BANKS 4
33
34 static const unsigned int ppc440ep_sdram_bank_sizes[] = {
35 256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
36 };
37
38 CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
39 const unsigned int pci_irq_nrs[4], int do_init,
40 const char *cpu_model)
41 {
42 target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
43 target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
44 CPUState *env;
45 qemu_irq *pic;
46 qemu_irq *irqs;
47 qemu_irq *pci_irqs;
48
49 if (cpu_model == NULL)
50 cpu_model = "405"; // XXX: should be 440EP
51 env = cpu_init(cpu_model);
52 if (!env) {
53 fprintf(stderr, "Unable to initialize CPU!\n");
54 exit(1);
55 }
56
57 ppc_dcr_init(env, NULL, NULL);
58
59 /* interrupt controller */
60 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
61 irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
62 irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
63 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
64
65 /* SDRAM controller */
66 memset(ram_bases, 0, sizeof(ram_bases));
67 memset(ram_sizes, 0, sizeof(ram_sizes));
68 *ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS,
69 ram_bases, ram_sizes,
70 ppc440ep_sdram_bank_sizes);
71 /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
72 ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_bases,
73 ram_sizes, do_init);
74
75 /* PCI */
76 pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4);
77 pci_irqs[0] = pic[pci_irq_nrs[0]];
78 pci_irqs[1] = pic[pci_irq_nrs[1]];
79 pci_irqs[2] = pic[pci_irq_nrs[2]];
80 pci_irqs[3] = pic[pci_irq_nrs[3]];
81 *pcip = ppc4xx_pci_init(env, pci_irqs,
82 PPC440EP_PCI_CONFIG,
83 PPC440EP_PCI_INTACK,
84 PPC440EP_PCI_SPECIAL,
85 PPC440EP_PCI_REGS);
86 if (!*pcip)
87 printf("couldn't create PCI controller!\n");
88
89 isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
90
91 if (serial_hds[0] != NULL) {
92 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
93 serial_hds[0], 1, 1);
94 }
95 if (serial_hds[1] != NULL) {
96 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
97 serial_hds[1], 1, 1);
98 }
99
100 return env;
101 }
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