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68396ea @rmustacc Initial commit of d32e8d0b8d9e0ef7cf7ab2e74548982972789dfc from qemu-kvm
rmustacc authored
1 /*
2 * ARM RealView Baseboard System emulation.
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licenced under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "arm-misc.h"
12 #include "primecell.h"
13 #include "devices.h"
14 #include "pci.h"
15 #include "usb-ohci.h"
16 #include "net.h"
17 #include "sysemu.h"
18 #include "boards.h"
19 #include "bitbang_i2c.h"
20 #include "sysbus.h"
21 #include "blockdev.h"
22
23 #define SMP_BOOT_ADDR 0xe0000000
24
25 typedef struct {
26 SysBusDevice busdev;
27 bitbang_i2c_interface *bitbang;
28 int out;
29 int in;
30 } RealViewI2CState;
31
32 static uint32_t realview_i2c_read(void *opaque, target_phys_addr_t offset)
33 {
34 RealViewI2CState *s = (RealViewI2CState *)opaque;
35
36 if (offset == 0) {
37 return (s->out & 1) | (s->in << 1);
38 } else {
39 hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset);
40 return -1;
41 }
42 }
43
44 static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
45 uint32_t value)
46 {
47 RealViewI2CState *s = (RealViewI2CState *)opaque;
48
49 switch (offset) {
50 case 0:
51 s->out |= value & 3;
52 break;
53 case 4:
54 s->out &= ~value;
55 break;
56 default:
57 hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset);
58 }
59 bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
60 s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
61 }
62
63 static CPUReadMemoryFunc * const realview_i2c_readfn[] = {
64 realview_i2c_read,
65 realview_i2c_read,
66 realview_i2c_read
67 };
68
69 static CPUWriteMemoryFunc * const realview_i2c_writefn[] = {
70 realview_i2c_write,
71 realview_i2c_write,
72 realview_i2c_write
73 };
74
75 static int realview_i2c_init(SysBusDevice *dev)
76 {
77 RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);
78 i2c_bus *bus;
79 int iomemtype;
80
81 bus = i2c_init_bus(&dev->qdev, "i2c");
82 s->bitbang = bitbang_i2c_init(bus);
83 iomemtype = cpu_register_io_memory(realview_i2c_readfn,
84 realview_i2c_writefn, s,
85 DEVICE_NATIVE_ENDIAN);
86 sysbus_init_mmio(dev, 0x1000, iomemtype);
87 return 0;
88 }
89
90 static SysBusDeviceInfo realview_i2c_info = {
91 .init = realview_i2c_init,
92 .qdev.name = "realview_i2c",
93 .qdev.size = sizeof(RealViewI2CState),
94 };
95
96 static void realview_register_devices(void)
97 {
98 sysbus_register_withprop(&realview_i2c_info);
99 }
100
101 /* Board init. */
102
103 static struct arm_boot_info realview_binfo = {
104 .smp_loader_start = SMP_BOOT_ADDR,
105 };
106
107 static void secondary_cpu_reset(void *opaque)
108 {
109 CPUState *env = opaque;
110
111 cpu_reset(env);
112 /* Set entry point for secondary CPUs. This assumes we're using
113 the init code from arm_boot.c. Real hardware resets all CPUs
114 the same. */
115 env->regs[15] = SMP_BOOT_ADDR;
116 }
117
118 /* The following two lists must be consistent. */
119 enum realview_board_type {
120 BOARD_EB,
121 BOARD_EB_MPCORE,
122 BOARD_PB_A8,
123 BOARD_PBX_A9,
124 };
125
126 static const int realview_board_id[] = {
127 0x33b,
128 0x33b,
129 0x769,
130 0x76d
131 };
132
133 static void realview_init(ram_addr_t ram_size,
134 const char *boot_device,
135 const char *kernel_filename, const char *kernel_cmdline,
136 const char *initrd_filename, const char *cpu_model,
137 enum realview_board_type board_type)
138 {
139 CPUState *env = NULL;
140 ram_addr_t ram_offset;
141 DeviceState *dev;
142 SysBusDevice *busdev;
143 qemu_irq *irqp;
144 qemu_irq pic[64];
145 PCIBus *pci_bus;
146 NICInfo *nd;
147 i2c_bus *i2c;
148 int n;
149 int done_nic = 0;
150 qemu_irq cpu_irq[4];
151 int is_mpcore = 0;
152 int is_pb = 0;
153 uint32_t proc_id = 0;
154 uint32_t sys_id;
155 ram_addr_t low_ram_size;
156
157 switch (board_type) {
158 case BOARD_EB:
159 break;
160 case BOARD_EB_MPCORE:
161 is_mpcore = 1;
162 break;
163 case BOARD_PB_A8:
164 is_pb = 1;
165 break;
166 case BOARD_PBX_A9:
167 is_mpcore = 1;
168 is_pb = 1;
169 break;
170 }
171 for (n = 0; n < smp_cpus; n++) {
172 env = cpu_init(cpu_model);
173 if (!env) {
174 fprintf(stderr, "Unable to find CPU definition\n");
175 exit(1);
176 }
177 irqp = arm_pic_init_cpu(env);
178 cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
179 if (n > 0) {
180 qemu_register_reset(secondary_cpu_reset, env);
181 }
182 }
183 if (arm_feature(env, ARM_FEATURE_V7)) {
184 if (is_mpcore) {
185 proc_id = 0x0c000000;
186 } else {
187 proc_id = 0x0e000000;
188 }
189 } else if (arm_feature(env, ARM_FEATURE_V6K)) {
190 proc_id = 0x06000000;
191 } else if (arm_feature(env, ARM_FEATURE_V6)) {
192 proc_id = 0x04000000;
193 } else {
194 proc_id = 0x02000000;
195 }
196
197 if (is_pb && ram_size > 0x20000000) {
198 /* Core tile RAM. */
199 low_ram_size = ram_size - 0x20000000;
200 ram_size = 0x20000000;
201 ram_offset = qemu_ram_alloc(NULL, "realview.lowmem", low_ram_size);
202 cpu_register_physical_memory(0x20000000, low_ram_size,
203 ram_offset | IO_MEM_RAM);
204 }
205
206 ram_offset = qemu_ram_alloc(NULL, "realview.highmem", ram_size);
207 low_ram_size = ram_size;
208 if (low_ram_size > 0x10000000)
209 low_ram_size = 0x10000000;
210 /* SDRAM at address zero. */
211 cpu_register_physical_memory(0, low_ram_size, ram_offset | IO_MEM_RAM);
212 if (is_pb) {
213 /* And again at a high address. */
214 cpu_register_physical_memory(0x70000000, ram_size,
215 ram_offset | IO_MEM_RAM);
216 } else {
217 ram_size = low_ram_size;
218 }
219
220 sys_id = is_pb ? 0x01780500 : 0xc1400400;
221 arm_sysctl_init(0x10000000, sys_id, proc_id);
222
223 if (is_mpcore) {
224 dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
225 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
226 qdev_init_nofail(dev);
227 busdev = sysbus_from_qdev(dev);
228 if (is_pb) {
229 realview_binfo.smp_priv_base = 0x1f000000;
230 } else {
231 realview_binfo.smp_priv_base = 0x10100000;
232 }
233 sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base);
234 for (n = 0; n < smp_cpus; n++) {
235 sysbus_connect_irq(busdev, n, cpu_irq[n]);
236 }
237 } else {
238 uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
239 /* For now just create the nIRQ GIC, and ignore the others. */
240 dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
241 }
242 for (n = 0; n < 64; n++) {
243 pic[n] = qdev_get_gpio_in(dev, n);
244 }
245
246 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
247 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
248
249 sysbus_create_simple("pl011", 0x10009000, pic[12]);
250 sysbus_create_simple("pl011", 0x1000a000, pic[13]);
251 sysbus_create_simple("pl011", 0x1000b000, pic[14]);
252 sysbus_create_simple("pl011", 0x1000c000, pic[15]);
253
254 /* DMA controller is optional, apparently. */
255 sysbus_create_simple("pl081", 0x10030000, pic[24]);
256
257 sysbus_create_simple("sp804", 0x10011000, pic[4]);
258 sysbus_create_simple("sp804", 0x10012000, pic[5]);
259
260 sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);
261
262 sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
263
264 sysbus_create_simple("pl031", 0x10017000, pic[10]);
265
266 if (!is_pb) {
267 dev = sysbus_create_varargs("realview_pci", 0x60000000,
268 pic[48], pic[49], pic[50], pic[51], NULL);
269 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
270 if (usb_enabled) {
271 usb_ohci_init_pci(pci_bus, -1);
272 }
273 n = drive_get_max_bus(IF_SCSI);
274 while (n >= 0) {
275 pci_create_simple(pci_bus, -1, "lsi53c895a");
276 n--;
277 }
278 }
279 for(n = 0; n < nb_nics; n++) {
280 nd = &nd_table[n];
281
282 if ((!nd->model && !done_nic)
283 || strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0) {
284 if (is_pb) {
285 lan9118_init(nd, 0x4e000000, pic[28]);
286 } else {
287 smc91c111_init(nd, 0x4e000000, pic[28]);
288 }
289 done_nic = 1;
290 } else {
291 pci_nic_init_nofail(nd, "rtl8139", NULL);
292 }
293 }
294
295 dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL);
296 i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
297 i2c_create_slave(i2c, "ds1338", 0x68);
298
299 /* Memory map for RealView Emulation Baseboard: */
300 /* 0x10000000 System registers. */
301 /* 0x10001000 System controller. */
302 /* 0x10002000 Two-Wire Serial Bus. */
303 /* 0x10003000 Reserved. */
304 /* 0x10004000 AACI. */
305 /* 0x10005000 MCI. */
306 /* 0x10006000 KMI0. */
307 /* 0x10007000 KMI1. */
308 /* 0x10008000 Character LCD. (EB) */
309 /* 0x10009000 UART0. */
310 /* 0x1000a000 UART1. */
311 /* 0x1000b000 UART2. */
312 /* 0x1000c000 UART3. */
313 /* 0x1000d000 SSPI. */
314 /* 0x1000e000 SCI. */
315 /* 0x1000f000 Reserved. */
316 /* 0x10010000 Watchdog. */
317 /* 0x10011000 Timer 0+1. */
318 /* 0x10012000 Timer 2+3. */
319 /* 0x10013000 GPIO 0. */
320 /* 0x10014000 GPIO 1. */
321 /* 0x10015000 GPIO 2. */
322 /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */
323 /* 0x10017000 RTC. */
324 /* 0x10018000 DMC. */
325 /* 0x10019000 PCI controller config. */
326 /* 0x10020000 CLCD. */
327 /* 0x10030000 DMA Controller. */
328 /* 0x10040000 GIC1. (EB) */
329 /* 0x10050000 GIC2. (EB) */
330 /* 0x10060000 GIC3. (EB) */
331 /* 0x10070000 GIC4. (EB) */
332 /* 0x10080000 SMC. */
333 /* 0x1e000000 GIC1. (PB) */
334 /* 0x1e001000 GIC2. (PB) */
335 /* 0x1e002000 GIC3. (PB) */
336 /* 0x1e003000 GIC4. (PB) */
337 /* 0x40000000 NOR flash. */
338 /* 0x44000000 DoC flash. */
339 /* 0x48000000 SRAM. */
340 /* 0x4c000000 Configuration flash. */
341 /* 0x4e000000 Ethernet. */
342 /* 0x4f000000 USB. */
343 /* 0x50000000 PISMO. */
344 /* 0x54000000 PISMO. */
345 /* 0x58000000 PISMO. */
346 /* 0x5c000000 PISMO. */
347 /* 0x60000000 PCI. */
348 /* 0x61000000 PCI Self Config. */
349 /* 0x62000000 PCI Config. */
350 /* 0x63000000 PCI IO. */
351 /* 0x64000000 PCI mem 0. */
352 /* 0x68000000 PCI mem 1. */
353 /* 0x6c000000 PCI mem 2. */
354
355 /* ??? Hack to map an additional page of ram for the secondary CPU
356 startup code. I guess this works on real hardware because the
357 BootROM happens to be in ROM/flash or in memory that isn't clobbered
358 until after Linux boots the secondary CPUs. */
359 ram_offset = qemu_ram_alloc(NULL, "realview.hack", 0x1000);
360 cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
361 ram_offset | IO_MEM_RAM);
362
363 realview_binfo.ram_size = ram_size;
364 realview_binfo.kernel_filename = kernel_filename;
365 realview_binfo.kernel_cmdline = kernel_cmdline;
366 realview_binfo.initrd_filename = initrd_filename;
367 realview_binfo.nb_cpus = smp_cpus;
368 realview_binfo.board_id = realview_board_id[board_type];
369 realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
370 arm_load_kernel(first_cpu, &realview_binfo);
371 }
372
373 static void realview_eb_init(ram_addr_t ram_size,
374 const char *boot_device,
375 const char *kernel_filename, const char *kernel_cmdline,
376 const char *initrd_filename, const char *cpu_model)
377 {
378 if (!cpu_model) {
379 cpu_model = "arm926";
380 }
381 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
382 initrd_filename, cpu_model, BOARD_EB);
383 }
384
385 static void realview_eb_mpcore_init(ram_addr_t ram_size,
386 const char *boot_device,
387 const char *kernel_filename, const char *kernel_cmdline,
388 const char *initrd_filename, const char *cpu_model)
389 {
390 if (!cpu_model) {
391 cpu_model = "arm11mpcore";
392 }
393 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
394 initrd_filename, cpu_model, BOARD_EB_MPCORE);
395 }
396
397 static void realview_pb_a8_init(ram_addr_t ram_size,
398 const char *boot_device,
399 const char *kernel_filename, const char *kernel_cmdline,
400 const char *initrd_filename, const char *cpu_model)
401 {
402 if (!cpu_model) {
403 cpu_model = "cortex-a8";
404 }
405 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
406 initrd_filename, cpu_model, BOARD_PB_A8);
407 }
408
409 static void realview_pbx_a9_init(ram_addr_t ram_size,
410 const char *boot_device,
411 const char *kernel_filename, const char *kernel_cmdline,
412 const char *initrd_filename, const char *cpu_model)
413 {
414 if (!cpu_model) {
415 cpu_model = "cortex-a9";
416 }
417 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
418 initrd_filename, cpu_model, BOARD_PBX_A9);
419 }
420
421 static QEMUMachine realview_eb_machine = {
422 .name = "realview-eb",
423 .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
424 .init = realview_eb_init,
425 .use_scsi = 1,
426 };
427
428 static QEMUMachine realview_eb_mpcore_machine = {
429 .name = "realview-eb-mpcore",
430 .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
431 .init = realview_eb_mpcore_init,
432 .use_scsi = 1,
433 .max_cpus = 4,
434 };
435
436 static QEMUMachine realview_pb_a8_machine = {
437 .name = "realview-pb-a8",
438 .desc = "ARM RealView Platform Baseboard for Cortex-A8",
439 .init = realview_pb_a8_init,
440 };
441
442 static QEMUMachine realview_pbx_a9_machine = {
443 .name = "realview-pbx-a9",
444 .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
445 .init = realview_pbx_a9_init,
446 .use_scsi = 1,
447 .max_cpus = 4,
448 };
449
450 static void realview_machine_init(void)
451 {
452 qemu_register_machine(&realview_eb_machine);
453 qemu_register_machine(&realview_eb_mpcore_machine);
454 qemu_register_machine(&realview_pb_a8_machine);
455 qemu_register_machine(&realview_pbx_a9_machine);
456 }
457
458 machine_init(realview_machine_init);
459 device_init(realview_register_devices)
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