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68396ea9 » rmustacc
2011-06-24 Initial commit of d32e8d0 from qemu-kvm
1 /*
2 * QEMU Sparc32 DMA controller emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Modifications:
7 * 2010-Feb-14 Artyom Tarasenko : reworked irq generation
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
27
28 #include "hw.h"
29 #include "sparc32_dma.h"
30 #include "sun4m.h"
31 #include "sysbus.h"
32 #include "trace.h"
33
34 /*
35 * This is the DMA controller part of chip STP2000 (Master I/O), also
36 * produced as NCR89C100. See
37 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
38 * and
39 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
40 */
41
42 #define DMA_REGS 4
43 #define DMA_SIZE (4 * sizeof(uint32_t))
44 /* We need the mask, because one instance of the device is not page
45 aligned (ledma, start address 0x0010) */
46 #define DMA_MASK (DMA_SIZE - 1)
47 /* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */
48 #define DMA_ETH_SIZE (8 * sizeof(uint32_t))
49 #define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1)
50
51 #define DMA_VER 0xa0000000
52 #define DMA_INTR 1
53 #define DMA_INTREN 0x10
54 #define DMA_WRITE_MEM 0x100
55 #define DMA_EN 0x200
56 #define DMA_LOADED 0x04000000
57 #define DMA_DRAIN_FIFO 0x40
58 #define DMA_RESET 0x80
59
60 /* XXX SCSI and ethernet should have different read-only bit masks */
61 #define DMA_CSR_RO_MASK 0xfe000007
62
63 typedef struct DMAState DMAState;
64
65 struct DMAState {
66 SysBusDevice busdev;
67 uint32_t dmaregs[DMA_REGS];
68 qemu_irq irq;
69 void *iommu;
70 qemu_irq gpio[2];
71 uint32_t is_ledma;
72 };
73
74 enum {
75 GPIO_RESET = 0,
76 GPIO_DMA,
77 };
78
79 /* Note: on sparc, the lance 16 bit bus is swapped */
80 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
81 uint8_t *buf, int len, int do_bswap)
82 {
83 DMAState *s = opaque;
84 int i;
85
86 addr |= s->dmaregs[3];
87 trace_ledma_memory_read(addr);
88 if (do_bswap) {
89 sparc_iommu_memory_read(s->iommu, addr, buf, len);
90 } else {
91 addr &= ~1;
92 len &= ~1;
93 sparc_iommu_memory_read(s->iommu, addr, buf, len);
94 for(i = 0; i < len; i += 2) {
95 bswap16s((uint16_t *)(buf + i));
96 }
97 }
98 }
99
100 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
101 uint8_t *buf, int len, int do_bswap)
102 {
103 DMAState *s = opaque;
104 int l, i;
105 uint16_t tmp_buf[32];
106
107 addr |= s->dmaregs[3];
108 trace_ledma_memory_write(addr);
109 if (do_bswap) {
110 sparc_iommu_memory_write(s->iommu, addr, buf, len);
111 } else {
112 addr &= ~1;
113 len &= ~1;
114 while (len > 0) {
115 l = len;
116 if (l > sizeof(tmp_buf))
117 l = sizeof(tmp_buf);
118 for(i = 0; i < l; i += 2) {
119 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
120 }
121 sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
122 len -= l;
123 buf += l;
124 addr += l;
125 }
126 }
127 }
128
129 static void dma_set_irq(void *opaque, int irq, int level)
130 {
131 DMAState *s = opaque;
132 if (level) {
133 s->dmaregs[0] |= DMA_INTR;
134 if (s->dmaregs[0] & DMA_INTREN) {
135 trace_sparc32_dma_set_irq_raise();
136 qemu_irq_raise(s->irq);
137 }
138 } else {
139 if (s->dmaregs[0] & DMA_INTR) {
140 s->dmaregs[0] &= ~DMA_INTR;
141 if (s->dmaregs[0] & DMA_INTREN) {
142 trace_sparc32_dma_set_irq_lower();
143 qemu_irq_lower(s->irq);
144 }
145 }
146 }
147 }
148
149 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
150 {
151 DMAState *s = opaque;
152
153 trace_espdma_memory_read(s->dmaregs[1]);
154 sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
155 s->dmaregs[1] += len;
156 }
157
158 void espdma_memory_write(void *opaque, uint8_t *buf, int len)
159 {
160 DMAState *s = opaque;
161
162 trace_espdma_memory_write(s->dmaregs[1]);
163 sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
164 s->dmaregs[1] += len;
165 }
166
167 static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
168 {
169 DMAState *s = opaque;
170 uint32_t saddr;
171
172 if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
173 /* aliased to espdma, but we can't get there from here */
174 /* buggy driver if using undocumented behavior, just return 0 */
175 trace_sparc32_dma_mem_readl(addr, 0);
176 return 0;
177 }
178 saddr = (addr & DMA_MASK) >> 2;
179 trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);
180 return s->dmaregs[saddr];
181 }
182
183 static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
184 {
185 DMAState *s = opaque;
186 uint32_t saddr;
187
188 if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
189 /* aliased to espdma, but we can't get there from here */
190 trace_sparc32_dma_mem_writel(addr, 0, val);
191 return;
192 }
193 saddr = (addr & DMA_MASK) >> 2;
194 trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);
195 switch (saddr) {
196 case 0:
197 if (val & DMA_INTREN) {
198 if (s->dmaregs[0] & DMA_INTR) {
199 trace_sparc32_dma_set_irq_raise();
200 qemu_irq_raise(s->irq);
201 }
202 } else {
203 if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) {
204 trace_sparc32_dma_set_irq_lower();
205 qemu_irq_lower(s->irq);
206 }
207 }
208 if (val & DMA_RESET) {
209 qemu_irq_raise(s->gpio[GPIO_RESET]);
210 qemu_irq_lower(s->gpio[GPIO_RESET]);
211 } else if (val & DMA_DRAIN_FIFO) {
212 val &= ~DMA_DRAIN_FIFO;
213 } else if (val == 0)
214 val = DMA_DRAIN_FIFO;
215
216 if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) {
217 trace_sparc32_dma_enable_raise();
218 qemu_irq_raise(s->gpio[GPIO_DMA]);
219 } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) {
220 trace_sparc32_dma_enable_lower();
221 qemu_irq_lower(s->gpio[GPIO_DMA]);
222 }
223
224 val &= ~DMA_CSR_RO_MASK;
225 val |= DMA_VER;
226 s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val;
227 break;
228 case 1:
229 s->dmaregs[0] |= DMA_LOADED;
230 /* fall through */
231 default:
232 s->dmaregs[saddr] = val;
233 break;
234 }
235 }
236
237 static CPUReadMemoryFunc * const dma_mem_read[3] = {
238 NULL,
239 NULL,
240 dma_mem_readl,
241 };
242
243 static CPUWriteMemoryFunc * const dma_mem_write[3] = {
244 NULL,
245 NULL,
246 dma_mem_writel,
247 };
248
249 static void dma_reset(DeviceState *d)
250 {
251 DMAState *s = container_of(d, DMAState, busdev.qdev);
252
253 memset(s->dmaregs, 0, DMA_SIZE);
254 s->dmaregs[0] = DMA_VER;
255 }
256
257 static const VMStateDescription vmstate_dma = {
258 .name ="sparc32_dma",
259 .version_id = 2,
260 .minimum_version_id = 2,
261 .minimum_version_id_old = 2,
262 .fields = (VMStateField []) {
263 VMSTATE_UINT32_ARRAY(dmaregs, DMAState, DMA_REGS),
264 VMSTATE_END_OF_LIST()
265 }
266 };
267
268 static int sparc32_dma_init1(SysBusDevice *dev)
269 {
270 DMAState *s = FROM_SYSBUS(DMAState, dev);
271 int dma_io_memory;
272 int reg_size;
273
274 sysbus_init_irq(dev, &s->irq);
275
276 dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s,
277 DEVICE_NATIVE_ENDIAN);
278 reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;
279 sysbus_init_mmio(dev, reg_size, dma_io_memory);
280
281 qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
282 qdev_init_gpio_out(&dev->qdev, s->gpio, 2);
283
284 return 0;
285 }
286
287 static SysBusDeviceInfo sparc32_dma_info = {
288 .init = sparc32_dma_init1,
289 .qdev.name = "sparc32_dma",
290 .qdev.size = sizeof(DMAState),
291 .qdev.vmsd = &vmstate_dma,
292 .qdev.reset = dma_reset,
293 .qdev.props = (Property[]) {
294 DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu),
295 DEFINE_PROP_UINT32("is_ledma", DMAState, is_ledma, 0),
296 DEFINE_PROP_END_OF_LIST(),
297 }
298 };
299
300 static void sparc32_dma_register_devices(void)
301 {
302 sysbus_register_withprop(&sparc32_dma_info);
303 }
304
305 device_init(sparc32_dma_register_devices)
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