diff --git a/src/jpcsp/Allegrex/Instructions.java b/src/jpcsp/Allegrex/Instructions.java
index 7c9c4bfd6..823881cc2 100644
--- a/src/jpcsp/Allegrex/Instructions.java
+++ b/src/jpcsp/Allegrex/Instructions.java
@@ -4182,7 +4182,33 @@ public void interpret(Processor processor, int insn) {
 }
 @Override
 public void compile(ICompilerContext context, int insn) {
-	context.compileRTRSIMM("doLWL", true);
+	if (!context.isRtRegister0()) {
+		MethodVisitor mv = context.getMethodVisitor();
+		int simm16 = context.getImm16(true);
+		context.prepareRtForStore();
+		context.memRead32(context.getRsRegisterIndex(), simm16);
+		context.loadRs();
+		if (simm16 != 0) {
+			context.loadImm16(true);
+			mv.visitInsn(Opcodes.IADD);
+		}
+		context.loadImm(0x3);
+		mv.visitInsn(Opcodes.IAND);
+		context.loadImm(0x3);
+		mv.visitInsn(Opcodes.ISHL);
+		mv.visitInsn(Opcodes.DUP_X1);
+		context.loadImm(0x3 << 3);
+		mv.visitInsn(Opcodes.IXOR);
+		mv.visitInsn(Opcodes.ISHL);
+		mv.visitInsn(Opcodes.SWAP);
+		context.loadImm(0x00FFFFFF);
+		mv.visitInsn(Opcodes.SWAP);
+		mv.visitInsn(Opcodes.ISHR);
+		context.loadRt();
+		mv.visitInsn(Opcodes.IAND);
+		mv.visitInsn(Opcodes.IOR);
+		context.storeRt();
+	}
 }
 @Override
 public String disasm(int address, int insn) {
@@ -4213,7 +4239,33 @@ public void interpret(Processor processor, int insn) {
 }
 @Override
 public void compile(ICompilerContext context, int insn) {
-	context.compileRTRSIMM("doLWR", true);
+	if (!context.isRtRegister0()) {
+		MethodVisitor mv = context.getMethodVisitor();
+		int simm16 = context.getImm16(true);
+		context.prepareRtForStore();
+		context.memRead32(context.getRsRegisterIndex(), simm16);
+		context.loadRs();
+		if (simm16 != 0) {
+			context.loadImm16(true);
+			mv.visitInsn(Opcodes.IADD);
+		}
+		context.loadImm(0x3);
+		mv.visitInsn(Opcodes.IAND);
+		context.loadImm(0x3);
+		mv.visitInsn(Opcodes.ISHL);
+		mv.visitInsn(Opcodes.DUP_X1);
+		mv.visitInsn(Opcodes.IUSHR);
+		mv.visitInsn(Opcodes.SWAP);
+		context.loadImm(0xFFFFFF00);
+		mv.visitInsn(Opcodes.SWAP);
+		context.loadImm(0x3 << 3);
+		mv.visitInsn(Opcodes.IXOR);
+		mv.visitInsn(Opcodes.ISHL);
+		context.loadRt();
+		mv.visitInsn(Opcodes.IAND);
+		mv.visitInsn(Opcodes.IOR);
+		context.storeRt();
+	}
 }
 @Override
 public String disasm(int address, int insn) {
@@ -4402,7 +4454,33 @@ public void interpret(Processor processor, int insn) {
 }
 @Override
 public void compile(ICompilerContext context, int insn) {
-	context.compileRTRSIMM("doSWL", true);
+	if (!context.isRtRegister0()) {
+		MethodVisitor mv = context.getMethodVisitor();
+		int simm16 = context.getImm16(true);
+		context.prepareMemWrite32(context.getRsRegisterIndex(), simm16);
+		context.loadRt();
+		context.loadRs();
+		if (simm16 != 0) {
+			context.loadImm16(true);
+			mv.visitInsn(Opcodes.IADD);
+		}
+		context.loadImm(0x3);
+		mv.visitInsn(Opcodes.IAND);
+		context.loadImm(0x3);
+		mv.visitInsn(Opcodes.ISHL);
+		mv.visitInsn(Opcodes.DUP_X1);
+		context.loadImm(0x3 << 3);
+		mv.visitInsn(Opcodes.IXOR);
+		mv.visitInsn(Opcodes.IUSHR);
+		mv.visitInsn(Opcodes.SWAP);
+		context.loadImm(0xFFFFFF00);
+		mv.visitInsn(Opcodes.SWAP);
+		mv.visitInsn(Opcodes.ISHL);
+		context.memRead32(context.getRsRegisterIndex(), simm16);
+		mv.visitInsn(Opcodes.IAND);
+		mv.visitInsn(Opcodes.IOR);
+		context.memWrite32(context.getRsRegisterIndex(), simm16);
+	}
 }
 @Override
 public String disasm(int address, int insn) {
@@ -4433,7 +4511,33 @@ public void interpret(Processor processor, int insn) {
 }
 @Override
 public void compile(ICompilerContext context, int insn) {
-	context.compileRTRSIMM("doSWR", true);
+	if (!context.isRtRegister0()) {
+		MethodVisitor mv = context.getMethodVisitor();
+		int simm16 = context.getImm16(true);
+		context.prepareMemWrite32(context.getRsRegisterIndex(), simm16);
+		context.loadRt();
+		context.loadRs();
+		if (simm16 != 0) {
+			context.loadImm16(true);
+			mv.visitInsn(Opcodes.IADD);
+		}
+		context.loadImm(0x3);
+		mv.visitInsn(Opcodes.IAND);
+		context.loadImm(0x3);
+		mv.visitInsn(Opcodes.ISHL);
+		mv.visitInsn(Opcodes.DUP_X1);
+		mv.visitInsn(Opcodes.ISHL);
+		mv.visitInsn(Opcodes.SWAP);
+		context.loadImm(0x3 << 3);
+		mv.visitInsn(Opcodes.IXOR);
+		context.loadImm(0x00FFFFFF);
+		mv.visitInsn(Opcodes.SWAP);
+		mv.visitInsn(Opcodes.ISHR);
+		context.memRead32(context.getRsRegisterIndex(), simm16);
+		mv.visitInsn(Opcodes.IAND);
+		mv.visitInsn(Opcodes.IOR);
+		context.memWrite32(context.getRsRegisterIndex(), simm16);
+	}
 }
 @Override
 public String disasm(int address, int insn) {