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bring in latest KAME (as of 19991130, KAME/NetBSD141) into kame branch

just for reference purposes.
This commit includes 1.4 -> 1.4.1 sync for kame branch.

The branch does not compile at all (due to the lack of ALTQ and some other
source code).  Please do not try to modify the branch, this is just for
referenre purposes.

synchronization to latest KAME will take place on HEAD branch soon.
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1 parent 4ac1c42 commit 25a9cc3d102e477f8b854b9b324395abc75e3712 itojun committed Nov 30, 1999
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@@ -1,4 +1,4 @@
-/* $NetBSD: sram.c,v 1.1.1.1 1996/05/05 12:17:03 oki Exp $ */
+/* $NetBSD: sram.c,v 1.5.16.1 1999/11/30 13:33:16 itojun Exp $ */
/*
* Copyright (c) 1994 Kazuhisa Shimizu.
@@ -40,27 +40,32 @@
#include <machine/sram.h>
#include <x68k/dev/sramvar.h>
#include <x68k/x68k/iodevice.h>
-#include "sram.h"
struct sram_softc sram_softc;
#ifdef DEBUG
#define SRAM_DEBUG_OPEN 0x01
#define SRAM_DEBUG_CLOSE 0x02
-#define SRAM_DEBUG_IOCTL 0x03
+#define SRAM_DEBUG_IOCTL 0x04
+#define SRAM_DEBUG_DONTDOIT 0x08
int sramdebug = SRAM_DEBUG_IOCTL;
#endif
+void sramattach __P((int));
+int sramopen __P((dev_t, int));
+void sramclose __P((dev_t, int));
+int sramioctl __P((dev_t, u_long, caddr_t, int, struct proc *));
+
/*
* functions for probeing.
*/
/* ARGSUSED */
+void
sramattach(num)
int num;
{
sram_softc.flags = 0;
printf("sram0: 16k bytes accessible\n");
- return (1);
}
@@ -89,6 +94,11 @@ sramopen(dev, flags)
}
su->flags |= SRF_OPEN;
+ if (flags & FREAD)
+ su->flags |= SRF_READ;
+ if (flags & FWRITE)
+ su->flags |= SRF_WRITE;
+
return (0);
}
@@ -108,9 +118,12 @@ sramclose (dev, flags)
if (su->flags & SRF_OPEN) {
su->flags = 0;
}
+ su->flags &= ~(SRF_READ|SRF_WRITE);
}
+extern
+
/*ARGSUSED*/
int
sramioctl (dev, cmd, data, flag, p)
@@ -120,38 +133,50 @@ sramioctl (dev, cmd, data, flag, p)
int flag;
struct proc *p;
{
- struct sram_softc *su = &sram_softc;
int error = 0;
struct sram_io *sram_io;
register char *sramtop = IODEVbase->io_sram;
+ struct sram_softc *su = &sram_softc;
#ifdef DEBUG
if (sramdebug & SRAM_DEBUG_IOCTL)
- printf ("Sram ioctl cmd=%x\n",cmd);
+ printf("Sram ioctl cmd=%lx\n", cmd);
#endif
sram_io = (struct sram_io *)data;
switch (cmd) {
case SIOGSRAM:
+ if ((su->flags & SRF_READ) == 0)
+ return(EPERM);
#ifdef DEBUG
- if (sramdebug & SRAM_DEBUG_IOCTL)
- printf ("Sram ioctl SIOGSRAM address=%x\n",data);
- printf ("Sram ioctl SIOGSRAM offset=%x\n",sram_io->offset);
+ if (sramdebug & SRAM_DEBUG_IOCTL) {
+ printf("Sram ioctl SIOGSRAM address=%p\n", data);
+ printf("Sram ioctl SIOGSRAM offset=%x\n", sram_io->offset);
+ }
#endif
if (sram_io == NULL ||
sram_io->offset + SRAM_IO_SIZE > SRAM_SIZE)
return(EFAULT);
bcopy(sramtop + sram_io->offset, &(sram_io->sram), SRAM_IO_SIZE);
break;
case SIOPSRAM:
+ if ((su->flags & SRF_WRITE) == 0)
+ return(EPERM);
#ifdef DEBUG
- if (sramdebug & SRAM_DEBUG_IOCTL)
- printf ("Sram ioctl SIOSSRAM address=%x\n",data);
- printf ("Sram ioctl SIOSSRAM offset=%x\n",sram_io->offset);
+ if (sramdebug & SRAM_DEBUG_IOCTL) {
+ printf("Sram ioctl SIOPSRAM address=%p\n", data);
+ printf("Sram ioctl SIOPSRAM offset=%x\n", sram_io->offset);
+ }
#endif
if (sram_io == NULL ||
sram_io->offset + SRAM_IO_SIZE > SRAM_SIZE)
return(EFAULT);
+#ifdef DEBUG
+ if (sramdebug & SRAM_DEBUG_DONTDOIT) {
+ printf ("Sram ioctl SIOPSRAM: skipping actual write\n");
+ break;
+ }
+#endif
sysport.sramwp = 0x31;
bcopy(&(sram_io->sram), sramtop + sram_io->offset,SRAM_IO_SIZE);
sysport.sramwp = 0x00;
@@ -160,5 +185,5 @@ sramioctl (dev, cmd, data, flag, p)
error = EINVAL;
break;
}
- return(error);
+ return (error);
}
@@ -1,4 +1,4 @@
-/* $NetBSD: sramvar.h,v 1.1.1.1 1996/05/05 12:17:03 oki Exp $ */
+/* $NetBSD: sramvar.h,v 1.1.1.1.30.1 1999/11/30 13:33:16 itojun Exp $ */
/*
* Copyright (c) 1994 Kazuhisa Shimizu.
@@ -35,9 +35,13 @@ struct sram_softc {
};
enum sram_unit_flag_bits {
- SRB_OPEN
+ SRB_OPEN,
+ SRB_READ,
+ SRB_WRITE
};
enum sram_unit_flags {
- SRF_OPEN = 1<<SRB_OPEN
+ SRF_OPEN = 1<<SRB_OPEN,
+ SRF_READ = 1<<SRB_READ,
+ SRF_WRITE = 1<<SRB_WRITE
};
View
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.1.1.1 1996/05/05 12:17:03 oki Exp $ */
+/* $NetBSD: cpu.h,v 1.17.6.1 1999/11/30 13:33:19 itojun Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -50,6 +50,17 @@
*/
/*
+ * Get common m68k CPU definitions.
+ */
+#include <m68k/cpu.h>
+#define M68K_MMU_MOTOROLA
+
+/*
+ * Get interrupt glue.
+ */
+#include <machine/intr.h>
+
+/*
* definitions of cpu-dependent requirements
* referenced in generic code
*/
@@ -84,6 +95,7 @@ struct clockframe {
* Preempt the current process if in interrupt from user mode,
* or after the current trap/syscall if in system mode.
*/
+extern int want_resched; /* resched() was called */
#define need_resched() { want_resched++; aston(); }
/*
@@ -99,28 +111,9 @@ struct clockframe {
*/
#define signotify(p) aston()
+extern int astpending; /* need to trap before returning to user mode */
#define aston() (astpending++)
-int astpending; /* need to trap before returning to user mode */
-int want_resched; /* resched() was called */
-
-
-/*
- * simulated software interrupt register
- */
-extern unsigned char ssir;
-
-#define SIR_NET 0x1
-#define SIR_CLOCK 0x2
-#define SIR_SERIAL 0x4
-#define SIR_KBD 0x8
-
-#define siroff(x) ssir &= ~(x)
-#define setsoftnet() ssir |= SIR_NET
-#define setsoftclock() ssir |= SIR_CLOCK
-#define setsoftserial() ssir |= SIR_SERIAL
-#define setsoftkbd() ssir |= SIR_KBD
-
/*
* CTL_MACHDEP definitions.
*/
@@ -133,32 +126,69 @@ extern unsigned char ssir;
}
/*
- * The rest of this should probably be moved to ../x68k/x68kcpu.h,
+ * The rest of this should probably be moved to <machine/x68kcpu.h>
* although some of it could probably be put into generic 68k headers.
*/
-/* values for machineid */
+#ifdef _KERNEL
+extern int machineid;
+extern char *intiolimit;
-/* values for mmutype (assigned for quick testing) */
-#define MMU_68040 -2 /* 68040 on-chip MMU */
-#define MMU_68030 -1 /* 68030 on-chip subset of 68851 */
-#define MMU_68851 1 /* Motorola 68851 */
+/* autoconf.c functions */
+void config_console __P((void));
+
+/* fpu.c functions */
+int fpu_probe __P((void));
+
+/* machdep.c functions */
+void dumpconf __P((void));
+void dumpsys __P((void));
+
+/* locore.s functions */
+struct pcb;
+struct fpframe;
+int suline __P((caddr_t, caddr_t));
+void savectx __P((struct pcb *));
+void switch_exit __P((struct proc *));
+void proc_trampoline __P((void));
+void loadustp __P((int));
+void m68881_save __P((struct fpframe *));
+void m68881_restore __P((struct fpframe *));
+void DCIS __P((void));
+void DCIU __P((void));
+void ICIA __P((void));
+void ICPA __P((void));
+void PCIA __P((void));
+void TBIA __P((void));
+void TBIS __P((vaddr_t));
+void TBIAS __P((void));
+void TBIAU __P((void));
+#if defined(M68040) || defined(M68060)
+void DCFA __P((void));
+void DCFP __P((vaddr_t));
+void DCFL __P((vaddr_t));
+void DCPL __P((vaddr_t));
+void DCPP __P((vaddr_t));
+void ICPL __P((vaddr_t));
+void ICPP __P((vaddr_t));
+#endif
-/* values for ectype */
-#define EC_PHYS -1 /* external physical address cache */
-#define EC_NONE 0 /* no external cache */
-#define EC_VIRT 1 /* external virtual address cache */
+/* machdep.c functions */
+int badaddr __P((caddr_t));
+int badbaddr __P((caddr_t));
-/* values for cpuspeed (not really related to clock speed due to caches) */
-#define MHZ_8 1
-#define MHZ_16 2
-#define MHZ_25 3
-#define MHZ_33 4
-#define MHZ_50 6
+/* sys_machdep.c functions */
+int cachectl1 __P((unsigned long, vaddr_t, size_t, struct proc *));
+int dma_cachectl __P((caddr_t, int));
+
+/* vm_machdep.c functions */
+void physaccess __P((caddr_t, caddr_t, int, int));
+void physunaccess __P((caddr_t, int));
+int kvtop __P((caddr_t));
+
+/* trap.c functions */
+void child_return __P((void *));
-#ifdef _KERNEL
-extern int machineid, mmutype;
-extern char *intiolimit;
#endif
/* physical memory sections */
@@ -177,69 +207,4 @@ extern char *intiolimit;
#define IIOPOFF(pa) ((int)(pa)-INTIOBASE)
#define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 4mb */
-/*
- * External IO space:
- */
-
-/*
- * 68851 and 68030 MMU
- */
-#define PMMU_LVLMASK 0x0007
-#define PMMU_INV 0x0400
-#define PMMU_WP 0x0800
-#define PMMU_ALV 0x1000
-#define PMMU_SO 0x2000
-#define PMMU_LV 0x4000
-#define PMMU_BE 0x8000
-#define PMMU_FAULT (PMMU_WP|PMMU_INV)
-
-/*
- * 68040 MMU
- */
-#define MMU4_RES 0x001
-#define MMU4_TTR 0x002
-#define MMU4_WP 0x004
-#define MMU4_MOD 0x010
-#define MMU4_CMMASK 0x060
-#define MMU4_SUP 0x080
-#define MMU4_U0 0x100
-#define MMU4_U1 0x200
-#define MMU4_GLB 0x400
-#define MMU4_BE 0x800
-
-/* 680X0 function codes */
-#define FC_USERD 1 /* user data space */
-#define FC_USERP 2 /* user program space */
-#define FC_SUPERD 5 /* supervisor data space */
-#define FC_SUPERP 6 /* supervisor program space */
-#define FC_CPU 7 /* CPU space */
-
-/* fields in the 68020 cache control register */
-#define IC_ENABLE 0x0001 /* enable instruction cache */
-#define IC_FREEZE 0x0002 /* freeze instruction cache */
-#define IC_CE 0x0004 /* clear instruction cache entry */
-#define IC_CLR 0x0008 /* clear entire instruction cache */
-
-/* additional fields in the 68030 cache control register */
-#define IC_BE 0x0010 /* instruction burst enable */
-#define DC_ENABLE 0x0100 /* data cache enable */
-#define DC_FREEZE 0x0200 /* data cache freeze */
-#define DC_CE 0x0400 /* clear data cache entry */
-#define DC_CLR 0x0800 /* clear entire data cache */
-#define DC_BE 0x1000 /* data burst enable */
-#define DC_WA 0x2000 /* write allocate */
-
-#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
-#define CACHE_OFF (DC_CLR|IC_CLR)
-#define CACHE_CLR (CACHE_ON)
-#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
-#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
-
-/* 68040 cache control register */
-#define IC4_ENABLE 0x8000 /* instruction cache enable bit */
-#define DC4_ENABLE 0x80000000 /* data cache enable bit */
-
-#define CACHE4_ON (IC4_ENABLE|DC4_ENABLE)
-#define CACHE4_OFF (0)
-
#endif /* _X68K_CPU_H_ */
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