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Import Atheros HAL, from FreeBSD (revision 185521)

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commit b6bbea69010aa0dc3a28190899eb21296255bf5b 1 parent a2bca40
alc authored
Showing with 32,776 additions and 0 deletions.
  1. +885 −0 sys/external/isc/atheros_hal/dist/ah.c
  2. +899 −0 sys/external/isc/atheros_hal/dist/ah.h
  3. +49 −0 sys/external/isc/atheros_hal/dist/ah_debug.h
  4. +55 −0 sys/external/isc/atheros_hal/dist/ah_decode.h
  5. +220 −0 sys/external/isc/atheros_hal/dist/ah_desc.h
  6. +84 −0 sys/external/isc/atheros_hal/dist/ah_devid.h
  7. +133 −0 sys/external/isc/atheros_hal/dist/ah_eeprom.h
  8. +253 −0 sys/external/isc/atheros_hal/dist/ah_eeprom_v1.c
  9. +99 −0 sys/external/isc/atheros_hal/dist/ah_eeprom_v1.h
  10. +415 −0 sys/external/isc/atheros_hal/dist/ah_eeprom_v14.c
  11. +271 −0 sys/external/isc/atheros_hal/dist/ah_eeprom_v14.h
  12. +1,876 −0 sys/external/isc/atheros_hal/dist/ah_eeprom_v3.c
  13. +462 −0 sys/external/isc/atheros_hal/dist/ah_eeprom_v3.h
  14. +804 −0 sys/external/isc/atheros_hal/dist/ah_internal.h
  15. +2,861 −0 sys/external/isc/atheros_hal/dist/ah_regdomain.c
  16. +91 −0 sys/external/isc/atheros_hal/dist/ah_soc.h
  17. +278 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210.h
  18. +383 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210_attach.c
  19. +191 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210_beacon.c
  20. +134 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210_interrupts.c
  21. +156 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210_keycache.c
  22. +642 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210_misc.c
  23. +85 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210_phy.c
  24. +134 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210_power.c
  25. +266 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210_recv.c
  26. +1,003 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210_reset.c
  27. +623 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210_xmit.c
  28. +130 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210desc.h
  29. +59 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210phy.h
  30. +401 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5210reg.h
  31. +194 −0 sys/external/isc/atheros_hal/dist/ar5210/ar5k_0007.ini
  32. +308 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211.h
  33. +516 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211_attach.c
  34. +173 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211_beacon.c
  35. +160 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211_interrupts.c
  36. +178 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211_keycache.c
  37. +685 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211_misc.c
  38. +104 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211_phy.c
  39. +136 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211_power.c
  40. +245 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211_recv.c
  41. +2,138 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211_reset.c
  42. +662 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211_xmit.c
  43. +134 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211desc.h
  44. +94 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211phy.h
  45. +853 −0 sys/external/isc/atheros_hal/dist/ar5211/ar5211reg.h
  46. +358 −0 sys/external/isc/atheros_hal/dist/ar5211/boss.ini
  47. +767 −0 sys/external/isc/atheros_hal/dist/ar5212/ar2316.c
  48. +744 −0 sys/external/isc/atheros_hal/dist/ar5212/ar2317.c
  49. +759 −0 sys/external/isc/atheros_hal/dist/ar5212/ar2413.c
  50. +722 −0 sys/external/isc/atheros_hal/dist/ar5212/ar2425.c
  51. +711 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5111.c
  52. +881 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5112.c
  53. +603 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212.h
  54. +2,171 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212.ini
  55. +1,016 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212_ani.c
  56. +870 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212_attach.c
  57. +253 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212_beacon.c
  58. +50 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212_eeprom.c
  59. +124 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212_gpio.c
  60. +206 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212_interrupts.c
  61. +285 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212_keycache.c
  62. +1,074 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212_misc.c
  63. +199 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212_phy.c
  64. +175 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212_power.c
  65. +286 −0 sys/external/isc/atheros_hal/dist/ar5212/ar5212_recv.c
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885 sys/external/isc/atheros_hal/dist/ah.c
@@ -0,0 +1,885 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah.c,v 1.1.1.1 2008/12/11 04:46:22 alc Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_devid.h"
+
+/* linker set of registered chips */
+OS_SET_DECLARE(ah_chips, struct ath_hal_chip);
+
+/*
+ * Check the set of registered chips to see if any recognize
+ * the device as one they can support.
+ */
+const char*
+ath_hal_probe(uint16_t vendorid, uint16_t devid)
+{
+ struct ath_hal_chip **pchip;
+
+ OS_SET_FOREACH(pchip, ah_chips) {
+ const char *name = (*pchip)->probe(vendorid, devid);
+ if (name != AH_NULL)
+ return name;
+ }
+ return AH_NULL;
+}
+
+/*
+ * Attach detects device chip revisions, initializes the hwLayer
+ * function list, reads EEPROM information,
+ * selects reset vectors, and performs a short self test.
+ * Any failures will return an error that should cause a hardware
+ * disable.
+ */
+struct ath_hal*
+ath_hal_attach(uint16_t devid, HAL_SOFTC sc,
+ HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *error)
+{
+ struct ath_hal_chip **pchip;
+
+ OS_SET_FOREACH(pchip, ah_chips) {
+ struct ath_hal_chip *chip = *pchip;
+ struct ath_hal *ah;
+
+ /* XXX don't have vendorid, assume atheros one works */
+ if (chip->probe(ATHEROS_VENDOR_ID, devid) == AH_NULL)
+ continue;
+ ah = chip->attach(devid, sc, st, sh, error);
+ if (ah != AH_NULL) {
+ /* copy back private state to public area */
+ ah->ah_devid = AH_PRIVATE(ah)->ah_devid;
+ ah->ah_subvendorid = AH_PRIVATE(ah)->ah_subvendorid;
+ ah->ah_macVersion = AH_PRIVATE(ah)->ah_macVersion;
+ ah->ah_macRev = AH_PRIVATE(ah)->ah_macRev;
+ ah->ah_phyRev = AH_PRIVATE(ah)->ah_phyRev;
+ ah->ah_analog5GhzRev = AH_PRIVATE(ah)->ah_analog5GhzRev;
+ ah->ah_analog2GhzRev = AH_PRIVATE(ah)->ah_analog2GhzRev;
+ return ah;
+ }
+ }
+ return AH_NULL;
+}
+
+/* linker set of registered RF backends */
+OS_SET_DECLARE(ah_rfs, struct ath_hal_rf);
+
+/*
+ * Check the set of registered RF backends to see if
+ * any recognize the device as one they can support.
+ */
+struct ath_hal_rf *
+ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode)
+{
+ struct ath_hal_rf **prf;
+
+ OS_SET_FOREACH(prf, ah_rfs) {
+ struct ath_hal_rf *rf = *prf;
+ if (rf->probe(ah))
+ return rf;
+ }
+ *ecode = HAL_ENOTSUPP;
+ return AH_NULL;
+}
+
+/*
+ * Poll the register looking for a specific value.
+ */
+HAL_BOOL
+ath_hal_wait(struct ath_hal *ah, u_int reg, uint32_t mask, uint32_t val)
+{
+#define AH_TIMEOUT 1000
+ int i;
+
+ for (i = 0; i < AH_TIMEOUT; i++) {
+ if ((OS_REG_READ(ah, reg) & mask) == val)
+ return AH_TRUE;
+ OS_DELAY(10);
+ }
+ HALDEBUG(ah, HAL_DEBUG_REGIO | HAL_DEBUG_PHYIO,
+ "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
+ __func__, reg, OS_REG_READ(ah, reg), mask, val);
+ return AH_FALSE;
+#undef AH_TIMEOUT
+}
+
+/*
+ * Reverse the bits starting at the low bit for a value of
+ * bit_count in size
+ */
+uint32_t
+ath_hal_reverseBits(uint32_t val, uint32_t n)
+{
+ uint32_t retval;
+ int i;
+
+ for (i = 0, retval = 0; i < n; i++) {
+ retval = (retval << 1) | (val & 1);
+ val >>= 1;
+ }
+ return retval;
+}
+
+/*
+ * Compute the time to transmit a frame of length frameLen bytes
+ * using the specified rate, phy, and short preamble setting.
+ */
+uint16_t
+ath_hal_computetxtime(struct ath_hal *ah,
+ const HAL_RATE_TABLE *rates, uint32_t frameLen, uint16_t rateix,
+ HAL_BOOL shortPreamble)
+{
+ uint32_t bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
+ uint32_t kbps;
+
+ kbps = rates->info[rateix].rateKbps;
+ /*
+ * index can be invalid duting dynamic Turbo transitions.
+ */
+ if(kbps == 0) return 0;
+ switch (rates->info[rateix].phy) {
+
+ case IEEE80211_T_CCK:
+#define CCK_SIFS_TIME 10
+#define CCK_PREAMBLE_BITS 144
+#define CCK_PLCP_BITS 48
+ phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
+ if (shortPreamble && rates->info[rateix].shortPreamble)
+ phyTime >>= 1;
+ numBits = frameLen << 3;
+ txTime = CCK_SIFS_TIME + phyTime
+ + ((numBits * 1000)/kbps);
+ break;
+#undef CCK_SIFS_TIME
+#undef CCK_PREAMBLE_BITS
+#undef CCK_PLCP_BITS
+
+ case IEEE80211_T_OFDM:
+#define OFDM_SIFS_TIME 16
+#define OFDM_PREAMBLE_TIME 20
+#define OFDM_PLCP_BITS 22
+#define OFDM_SYMBOL_TIME 4
+
+#define OFDM_SIFS_TIME_HALF 32
+#define OFDM_PREAMBLE_TIME_HALF 40
+#define OFDM_PLCP_BITS_HALF 22
+#define OFDM_SYMBOL_TIME_HALF 8
+
+#define OFDM_SIFS_TIME_QUARTER 64
+#define OFDM_PREAMBLE_TIME_QUARTER 80
+#define OFDM_PLCP_BITS_QUARTER 22
+#define OFDM_SYMBOL_TIME_QUARTER 16
+
+ if (AH_PRIVATE(ah)->ah_curchan &&
+ IS_CHAN_QUARTER_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+ bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
+ HALASSERT(bitsPerSymbol != 0);
+
+ numBits = OFDM_PLCP_BITS + (frameLen << 3);
+ numSymbols = howmany(numBits, bitsPerSymbol);
+ txTime = OFDM_SIFS_TIME_QUARTER
+ + OFDM_PREAMBLE_TIME_QUARTER
+ + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
+ } else if (AH_PRIVATE(ah)->ah_curchan &&
+ IS_CHAN_HALF_RATE(AH_PRIVATE(ah)->ah_curchan)) {
+ bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
+ HALASSERT(bitsPerSymbol != 0);
+
+ numBits = OFDM_PLCP_BITS + (frameLen << 3);
+ numSymbols = howmany(numBits, bitsPerSymbol);
+ txTime = OFDM_SIFS_TIME_HALF +
+ OFDM_PREAMBLE_TIME_HALF
+ + (numSymbols * OFDM_SYMBOL_TIME_HALF);
+ } else { /* full rate channel */
+ bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
+ HALASSERT(bitsPerSymbol != 0);
+
+ numBits = OFDM_PLCP_BITS + (frameLen << 3);
+ numSymbols = howmany(numBits, bitsPerSymbol);
+ txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
+ + (numSymbols * OFDM_SYMBOL_TIME);
+ }
+ break;
+
+#undef OFDM_SIFS_TIME
+#undef OFDM_PREAMBLE_TIME
+#undef OFDM_PLCP_BITS
+#undef OFDM_SYMBOL_TIME
+
+ case IEEE80211_T_TURBO:
+#define TURBO_SIFS_TIME 8
+#define TURBO_PREAMBLE_TIME 14
+#define TURBO_PLCP_BITS 22
+#define TURBO_SYMBOL_TIME 4
+ /* we still save OFDM rates in kbps - so double them */
+ bitsPerSymbol = ((kbps << 1) * TURBO_SYMBOL_TIME) / 1000;
+ HALASSERT(bitsPerSymbol != 0);
+
+ numBits = TURBO_PLCP_BITS + (frameLen << 3);
+ numSymbols = howmany(numBits, bitsPerSymbol);
+ txTime = TURBO_SIFS_TIME + TURBO_PREAMBLE_TIME
+ + (numSymbols * TURBO_SYMBOL_TIME);
+ break;
+#undef TURBO_SIFS_TIME
+#undef TURBO_PREAMBLE_TIME
+#undef TURBO_PLCP_BITS
+#undef TURBO_SYMBOL_TIME
+
+ default:
+ HALDEBUG(ah, HAL_DEBUG_PHYIO,
+ "%s: unknown phy %u (rate ix %u)\n",
+ __func__, rates->info[rateix].phy, rateix);
+ txTime = 0;
+ break;
+ }
+ return txTime;
+}
+
+static __inline int
+mapgsm(u_int freq, u_int flags)
+{
+ freq *= 10;
+ if (flags & CHANNEL_QUARTER)
+ freq += 5;
+ else if (flags & CHANNEL_HALF)
+ freq += 10;
+ else
+ freq += 20;
+ return (freq - 24220) / 5;
+}
+
+static __inline int
+mappsb(u_int freq, u_int flags)
+{
+ return ((freq * 10) + (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
+}
+
+/*
+ * Convert GHz frequency to IEEE channel number.
+ */
+int
+ath_hal_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags)
+{
+ if (flags & CHANNEL_2GHZ) { /* 2GHz band */
+ if (freq == 2484)
+ return 14;
+ if (freq < 2484) {
+ if (ath_hal_isgsmsku(ah))
+ return mapgsm(freq, flags);
+ return ((int)freq - 2407) / 5;
+ } else
+ return 15 + ((freq - 2512) / 20);
+ } else if (flags & CHANNEL_5GHZ) {/* 5Ghz band */
+ if (ath_hal_ispublicsafetysku(ah) &&
+ IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
+ return mappsb(freq, flags);
+ } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
+ return (freq - 4000) / 5;
+ } else {
+ return (freq - 5000) / 5;
+ }
+ } else { /* either, guess */
+ if (freq == 2484)
+ return 14;
+ if (freq < 2484) {
+ if (ath_hal_isgsmsku(ah))
+ return mapgsm(freq, flags);
+ return ((int)freq - 2407) / 5;
+ }
+ if (freq < 5000) {
+ if (ath_hal_ispublicsafetysku(ah) &&
+ IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
+ return mappsb(freq, flags);
+ } else if (freq > 4900) {
+ return (freq - 4000) / 5;
+ } else {
+ return 15 + ((freq - 2512) / 20);
+ }
+ }
+ return (freq - 5000) / 5;
+ }
+}
+
+typedef enum {
+ WIRELESS_MODE_11a = 0,
+ WIRELESS_MODE_TURBO = 1,
+ WIRELESS_MODE_11b = 2,
+ WIRELESS_MODE_11g = 3,
+ WIRELESS_MODE_108g = 4,
+
+ WIRELESS_MODE_MAX
+} WIRELESS_MODE;
+
+static WIRELESS_MODE
+ath_hal_chan2wmode(struct ath_hal *ah, const HAL_CHANNEL *chan)
+{
+ if (IS_CHAN_CCK(chan))
+ return WIRELESS_MODE_11b;
+ if (IS_CHAN_G(chan))
+ return WIRELESS_MODE_11g;
+ if (IS_CHAN_108G(chan))
+ return WIRELESS_MODE_108g;
+ if (IS_CHAN_TURBO(chan))
+ return WIRELESS_MODE_TURBO;
+ return WIRELESS_MODE_11a;
+}
+
+/*
+ * Convert between microseconds and core system clocks.
+ */
+ /* 11a Turbo 11b 11g 108g */
+static const uint8_t CLOCK_RATE[] = { 40, 80, 22, 44, 88 };
+
+u_int
+ath_hal_mac_clks(struct ath_hal *ah, u_int usecs)
+{
+ const HAL_CHANNEL *c = (const HAL_CHANNEL *) AH_PRIVATE(ah)->ah_curchan;
+ u_int clks;
+
+ /* NB: ah_curchan may be null when called attach time */
+ if (c != AH_NULL) {
+ clks = usecs * CLOCK_RATE[ath_hal_chan2wmode(ah, c)];
+ if (IS_CHAN_HT40(c))
+ clks <<= 1;
+ else if (IS_CHAN_HALF_RATE(c))
+ clks >>= 1;
+ else if (IS_CHAN_QUARTER_RATE(c))
+ clks >>= 2;
+ } else
+ clks = usecs * CLOCK_RATE[WIRELESS_MODE_11b];
+ return clks;
+}
+
+u_int
+ath_hal_mac_usec(struct ath_hal *ah, u_int clks)
+{
+ const HAL_CHANNEL *c = (const HAL_CHANNEL *) AH_PRIVATE(ah)->ah_curchan;
+ u_int usec;
+
+ /* NB: ah_curchan may be null when called attach time */
+ if (c != AH_NULL) {
+ usec = clks / CLOCK_RATE[ath_hal_chan2wmode(ah, c)];
+ if (IS_CHAN_HT40(c))
+ usec >>= 1;
+ else if (IS_CHAN_HALF_RATE(c))
+ usec <<= 1;
+ else if (IS_CHAN_QUARTER_RATE(c))
+ usec <<= 2;
+ } else
+ usec = clks / CLOCK_RATE[WIRELESS_MODE_11b];
+ return usec;
+}
+
+/*
+ * Setup a h/w rate table's reverse lookup table and
+ * fill in ack durations. This routine is called for
+ * each rate table returned through the ah_getRateTable
+ * method. The reverse lookup tables are assumed to be
+ * initialized to zero (or at least the first entry).
+ * We use this as a key that indicates whether or not
+ * we've previously setup the reverse lookup table.
+ *
+ * XXX not reentrant, but shouldn't matter
+ */
+void
+ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt)
+{
+#define N(a) (sizeof(a)/sizeof(a[0]))
+ int i;
+
+ if (rt->rateCodeToIndex[0] != 0) /* already setup */
+ return;
+ for (i = 0; i < N(rt->rateCodeToIndex); i++)
+ rt->rateCodeToIndex[i] = (uint8_t) -1;
+ for (i = 0; i < rt->rateCount; i++) {
+ uint8_t code = rt->info[i].rateCode;
+ uint8_t cix = rt->info[i].controlRate;
+
+ HALASSERT(code < N(rt->rateCodeToIndex));
+ rt->rateCodeToIndex[code] = i;
+ HALASSERT((code | rt->info[i].shortPreamble) <
+ N(rt->rateCodeToIndex));
+ rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
+ /*
+ * XXX for 11g the control rate to use for 5.5 and 11 Mb/s
+ * depends on whether they are marked as basic rates;
+ * the static tables are setup with an 11b-compatible
+ * 2Mb/s rate which will work but is suboptimal
+ */
+ rt->info[i].lpAckDuration = ath_hal_computetxtime(ah, rt,
+ WLAN_CTRL_FRAME_SIZE, cix, AH_FALSE);
+ rt->info[i].spAckDuration = ath_hal_computetxtime(ah, rt,
+ WLAN_CTRL_FRAME_SIZE, cix, AH_TRUE);
+ }
+#undef N
+}
+
+HAL_STATUS
+ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
+ uint32_t capability, uint32_t *result)
+{
+ const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
+
+ switch (type) {
+ case HAL_CAP_REG_DMN: /* regulatory domain */
+ *result = AH_PRIVATE(ah)->ah_currentRD;
+ return HAL_OK;
+ case HAL_CAP_CIPHER: /* cipher handled in hardware */
+ case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
+ return HAL_ENOTSUPP;
+ case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
+ return HAL_ENOTSUPP;
+ case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */
+ return pCap->halHwPhyCounterSupport ? HAL_OK : HAL_ENXIO;
+ case HAL_CAP_WME_TKIPMIC: /* hardware can do TKIP MIC when WMM is turned on */
+ return HAL_ENOTSUPP;
+ case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
+ return HAL_ENOTSUPP;
+ case HAL_CAP_KEYCACHE_SIZE: /* hardware key cache size */
+ *result = pCap->halKeyCacheSize;
+ return HAL_OK;
+ case HAL_CAP_NUM_TXQUEUES: /* number of hardware tx queues */
+ *result = pCap->halTotalQueues;
+ return HAL_OK;
+ case HAL_CAP_VEOL: /* hardware supports virtual EOL */
+ return pCap->halVEOLSupport ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_PSPOLL: /* hardware PS-Poll support works */
+ return pCap->halPSPollBroken ? HAL_ENOTSUPP : HAL_OK;
+ case HAL_CAP_COMPRESSION:
+ return pCap->halCompressSupport ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_BURST:
+ return pCap->halBurstSupport ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_FASTFRAME:
+ return pCap->halFastFramesSupport ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_DIAG: /* hardware diagnostic support */
+ *result = AH_PRIVATE(ah)->ah_diagreg;
+ return HAL_OK;
+ case HAL_CAP_TXPOW: /* global tx power limit */
+ switch (capability) {
+ case 0: /* facility is supported */
+ return HAL_OK;
+ case 1: /* current limit */
+ *result = AH_PRIVATE(ah)->ah_powerLimit;
+ return HAL_OK;
+ case 2: /* current max tx power */
+ *result = AH_PRIVATE(ah)->ah_maxPowerLevel;
+ return HAL_OK;
+ case 3: /* scale factor */
+ *result = AH_PRIVATE(ah)->ah_tpScale;
+ return HAL_OK;
+ }
+ return HAL_ENOTSUPP;
+ case HAL_CAP_BSSIDMASK: /* hardware supports bssid mask */
+ return pCap->halBssIdMaskSupport ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
+ return pCap->halMcastKeySrchSupport ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
+ return HAL_ENOTSUPP;
+ case HAL_CAP_RFSILENT: /* rfsilent support */
+ switch (capability) {
+ case 0: /* facility is supported */
+ return pCap->halRfSilentSupport ? HAL_OK : HAL_ENOTSUPP;
+ case 1: /* current setting */
+ return AH_PRIVATE(ah)->ah_rfkillEnabled ?
+ HAL_OK : HAL_ENOTSUPP;
+ case 2: /* rfsilent config */
+ *result = AH_PRIVATE(ah)->ah_rfsilent;
+ return HAL_OK;
+ }
+ return HAL_ENOTSUPP;
+ case HAL_CAP_11D:
+#ifdef AH_SUPPORT_11D
+ return HAL_OK;
+#else
+ return HAL_ENOTSUPP;
+#endif
+ case HAL_CAP_RXORN_FATAL: /* HAL_INT_RXORN treated as fatal */
+ return AH_PRIVATE(ah)->ah_rxornIsFatal ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_HT:
+ return pCap->halHTSupport ? HAL_OK : HAL_ENOTSUPP;
+ case HAL_CAP_TX_CHAINMASK: /* mask of TX chains supported */
+ *result = pCap->halTxChainMask;
+ return HAL_OK;
+ case HAL_CAP_RX_CHAINMASK: /* mask of RX chains supported */
+ *result = pCap->halRxChainMask;
+ return HAL_OK;
+ case HAL_CAP_RXTSTAMP_PREC: /* rx desc tstamp precision (bits) */
+ *result = pCap->halTstampPrecision;
+ return HAL_OK;
+ default:
+ return HAL_EINVAL;
+ }
+}
+
+HAL_BOOL
+ath_hal_setcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
+ uint32_t capability, uint32_t setting, HAL_STATUS *status)
+{
+
+ switch (type) {
+ case HAL_CAP_TXPOW:
+ switch (capability) {
+ case 3:
+ if (setting <= HAL_TP_SCALE_MIN) {
+ AH_PRIVATE(ah)->ah_tpScale = setting;
+ return AH_TRUE;
+ }
+ break;
+ }
+ break;
+ case HAL_CAP_RFSILENT: /* rfsilent support */
+ /*
+ * NB: allow even if halRfSilentSupport is false
+ * in case the EEPROM is misprogrammed.
+ */
+ switch (capability) {
+ case 1: /* current setting */
+ AH_PRIVATE(ah)->ah_rfkillEnabled = (setting != 0);
+ return AH_TRUE;
+ case 2: /* rfsilent config */
+ /* XXX better done per-chip for validation? */
+ AH_PRIVATE(ah)->ah_rfsilent = setting;
+ return AH_TRUE;
+ }
+ break;
+ case HAL_CAP_REG_DMN: /* regulatory domain */
+ AH_PRIVATE(ah)->ah_currentRD = setting;
+ return AH_TRUE;
+ case HAL_CAP_RXORN_FATAL: /* HAL_INT_RXORN treated as fatal */
+ AH_PRIVATE(ah)->ah_rxornIsFatal = setting;
+ return AH_TRUE;
+ default:
+ break;
+ }
+ if (status)
+ *status = HAL_EINVAL;
+ return AH_FALSE;
+}
+
+/*
+ * Common support for getDiagState method.
+ */
+
+static u_int
+ath_hal_getregdump(struct ath_hal *ah, const HAL_REGRANGE *regs,
+ void *dstbuf, int space)
+{
+ uint32_t *dp = dstbuf;
+ int i;
+
+ for (i = 0; space >= 2*sizeof(uint32_t); i++) {
+ u_int r = regs[i].start;
+ u_int e = regs[i].end;
+ *dp++ = (r<<16) | e;
+ space -= sizeof(uint32_t);
+ do {
+ *dp++ = OS_REG_READ(ah, r);
+ r += sizeof(uint32_t);
+ space -= sizeof(uint32_t);
+ } while (r <= e && space >= sizeof(uint32_t));
+ }
+ return (char *) dp - (char *) dstbuf;
+}
+
+HAL_BOOL
+ath_hal_getdiagstate(struct ath_hal *ah, int request,
+ const void *args, uint32_t argsize,
+ void **result, uint32_t *resultsize)
+{
+ switch (request) {
+ case HAL_DIAG_REVS:
+ *result = &AH_PRIVATE(ah)->ah_devid;
+ *resultsize = sizeof(HAL_REVS);
+ return AH_TRUE;
+ case HAL_DIAG_REGS:
+ *resultsize = ath_hal_getregdump(ah, args, *result,*resultsize);
+ return AH_TRUE;
+ case HAL_DIAG_FATALERR:
+ *result = &AH_PRIVATE(ah)->ah_fatalState[0];
+ *resultsize = sizeof(AH_PRIVATE(ah)->ah_fatalState);
+ return AH_TRUE;
+ case HAL_DIAG_EEREAD:
+ if (argsize != sizeof(uint16_t))
+ return AH_FALSE;
+ if (!ath_hal_eepromRead(ah, *(const uint16_t *)args, *result))
+ return AH_FALSE;
+ *resultsize = sizeof(uint16_t);
+ return AH_TRUE;
+#ifdef AH_PRIVATE_DIAG
+ case HAL_DIAG_SETKEY: {
+ const HAL_DIAG_KEYVAL *dk;
+
+ if (argsize != sizeof(HAL_DIAG_KEYVAL))
+ return AH_FALSE;
+ dk = (const HAL_DIAG_KEYVAL *)args;
+ return ah->ah_setKeyCacheEntry(ah, dk->dk_keyix,
+ &dk->dk_keyval, dk->dk_mac, dk->dk_xor);
+ }
+ case HAL_DIAG_RESETKEY:
+ if (argsize != sizeof(uint16_t))
+ return AH_FALSE;
+ return ah->ah_resetKeyCacheEntry(ah, *(const uint16_t *)args);
+#ifdef AH_SUPPORT_WRITE_EEPROM
+ case HAL_DIAG_EEWRITE: {
+ const HAL_DIAG_EEVAL *ee;
+ if (argsize != sizeof(HAL_DIAG_EEVAL))
+ return AH_FALSE;
+ ee = (const HAL_DIAG_EEVAL *)args;
+ return ath_hal_eepromWrite(ah, ee->ee_off, ee->ee_data);
+ }
+#endif /* AH_SUPPORT_WRITE_EEPROM */
+#endif /* AH_PRIVATE_DIAG */
+ case HAL_DIAG_11NCOMPAT:
+ if (argsize == 0) {
+ *resultsize = sizeof(uint32_t);
+ *((uint32_t *)(*result)) =
+ AH_PRIVATE(ah)->ah_11nCompat;
+ } else if (argsize == sizeof(uint32_t)) {
+ AH_PRIVATE(ah)->ah_11nCompat = *(const uint32_t *)args;
+ } else
+ return AH_FALSE;
+ return AH_TRUE;
+ }
+ return AH_FALSE;
+}
+
+/*
+ * Set the properties of the tx queue with the parameters
+ * from qInfo.
+ */
+HAL_BOOL
+ath_hal_setTxQProps(struct ath_hal *ah,
+ HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo)
+{
+ uint32_t cw;
+
+ if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+ HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
+ "%s: inactive queue\n", __func__);
+ return AH_FALSE;
+ }
+ /* XXX validate parameters */
+ qi->tqi_ver = qInfo->tqi_ver;
+ qi->tqi_subtype = qInfo->tqi_subtype;
+ qi->tqi_qflags = qInfo->tqi_qflags;
+ qi->tqi_priority = qInfo->tqi_priority;
+ if (qInfo->tqi_aifs != HAL_TXQ_USEDEFAULT)
+ qi->tqi_aifs = AH_MIN(qInfo->tqi_aifs, 255);
+ else
+ qi->tqi_aifs = INIT_AIFS;
+ if (qInfo->tqi_cwmin != HAL_TXQ_USEDEFAULT) {
+ cw = AH_MIN(qInfo->tqi_cwmin, 1024);
+ /* make sure that the CWmin is of the form (2^n - 1) */
+ qi->tqi_cwmin = 1;
+ while (qi->tqi_cwmin < cw)
+ qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
+ } else
+ qi->tqi_cwmin = qInfo->tqi_cwmin;
+ if (qInfo->tqi_cwmax != HAL_TXQ_USEDEFAULT) {
+ cw = AH_MIN(qInfo->tqi_cwmax, 1024);
+ /* make sure that the CWmax is of the form (2^n - 1) */
+ qi->tqi_cwmax = 1;
+ while (qi->tqi_cwmax < cw)
+ qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
+ } else
+ qi->tqi_cwmax = INIT_CWMAX;
+ /* Set retry limit values */
+ if (qInfo->tqi_shretry != 0)
+ qi->tqi_shretry = AH_MIN(qInfo->tqi_shretry, 15);
+ else
+ qi->tqi_shretry = INIT_SH_RETRY;
+ if (qInfo->tqi_lgretry != 0)
+ qi->tqi_lgretry = AH_MIN(qInfo->tqi_lgretry, 15);
+ else
+ qi->tqi_lgretry = INIT_LG_RETRY;
+ qi->tqi_cbrPeriod = qInfo->tqi_cbrPeriod;
+ qi->tqi_cbrOverflowLimit = qInfo->tqi_cbrOverflowLimit;
+ qi->tqi_burstTime = qInfo->tqi_burstTime;
+ qi->tqi_readyTime = qInfo->tqi_readyTime;
+
+ switch (qInfo->tqi_subtype) {
+ case HAL_WME_UPSD:
+ if (qi->tqi_type == HAL_TX_QUEUE_DATA)
+ qi->tqi_intFlags = HAL_TXQ_USE_LOCKOUT_BKOFF_DIS;
+ break;
+ default:
+ break; /* NB: silence compiler */
+ }
+ return AH_TRUE;
+}
+
+HAL_BOOL
+ath_hal_getTxQProps(struct ath_hal *ah,
+ HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi)
+{
+ if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
+ HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
+ "%s: inactive queue\n", __func__);
+ return AH_FALSE;
+ }
+
+ qInfo->tqi_qflags = qi->tqi_qflags;
+ qInfo->tqi_ver = qi->tqi_ver;
+ qInfo->tqi_subtype = qi->tqi_subtype;
+ qInfo->tqi_qflags = qi->tqi_qflags;
+ qInfo->tqi_priority = qi->tqi_priority;
+ qInfo->tqi_aifs = qi->tqi_aifs;
+ qInfo->tqi_cwmin = qi->tqi_cwmin;
+ qInfo->tqi_cwmax = qi->tqi_cwmax;
+ qInfo->tqi_shretry = qi->tqi_shretry;
+ qInfo->tqi_lgretry = qi->tqi_lgretry;
+ qInfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
+ qInfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
+ qInfo->tqi_burstTime = qi->tqi_burstTime;
+ qInfo->tqi_readyTime = qi->tqi_readyTime;
+ return AH_TRUE;
+}
+
+ /* 11a Turbo 11b 11g 108g */
+static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93 };
+
+/*
+ * Read the current channel noise floor and return.
+ * If nf cal hasn't finished, channel noise floor should be 0
+ * and we return a nominal value based on band and frequency.
+ *
+ * NB: This is a private routine used by per-chip code to
+ * implement the ah_getChanNoise method.
+ */
+int16_t
+ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan)
+{
+ HAL_CHANNEL_INTERNAL *ichan;
+
+ ichan = ath_hal_checkchannel(ah, chan);
+ if (ichan == AH_NULL) {
+ HALDEBUG(ah, HAL_DEBUG_NFCAL,
+ "%s: invalid channel %u/0x%x; no mapping\n",
+ __func__, chan->channel, chan->channelFlags);
+ return 0;
+ }
+ if (ichan->rawNoiseFloor == 0) {
+ WIRELESS_MODE mode = ath_hal_chan2wmode(ah, chan);
+
+ HALASSERT(mode < WIRELESS_MODE_MAX);
+ return NOISE_FLOOR[mode] + ath_hal_getNfAdjust(ah, ichan);
+ } else
+ return ichan->rawNoiseFloor + ichan->noiseFloorAdjust;
+}
+
+/*
+ * Process all valid raw noise floors into the dBm noise floor values.
+ * Though our device has no reference for a dBm noise floor, we perform
+ * a relative minimization of NF's based on the lowest NF found across a
+ * channel scan.
+ */
+void
+ath_hal_process_noisefloor(struct ath_hal *ah)
+{
+ HAL_CHANNEL_INTERNAL *c;
+ int16_t correct2, correct5;
+ int16_t lowest2, lowest5;
+ int i;
+
+ /*
+ * Find the lowest 2GHz and 5GHz noise floor values after adjusting
+ * for statistically recorded NF/channel deviation.
+ */
+ correct2 = lowest2 = 0;
+ correct5 = lowest5 = 0;
+ for (i = 0; i < AH_PRIVATE(ah)->ah_nchan; i++) {
+ WIRELESS_MODE mode;
+ int16_t nf;
+
+ c = &AH_PRIVATE(ah)->ah_channels[i];
+ if (c->rawNoiseFloor >= 0)
+ continue;
+ mode = ath_hal_chan2wmode(ah, (HAL_CHANNEL *) c);
+ HALASSERT(mode < WIRELESS_MODE_MAX);
+ nf = c->rawNoiseFloor + NOISE_FLOOR[mode] +
+ ath_hal_getNfAdjust(ah, c);
+ if (IS_CHAN_5GHZ(c)) {
+ if (nf < lowest5) {
+ lowest5 = nf;
+ correct5 = NOISE_FLOOR[mode] -
+ (c->rawNoiseFloor + ath_hal_getNfAdjust(ah, c));
+ }
+ } else {
+ if (nf < lowest2) {
+ lowest2 = nf;
+ correct2 = NOISE_FLOOR[mode] -
+ (c->rawNoiseFloor + ath_hal_getNfAdjust(ah, c));
+ }
+ }
+ }
+
+ /* Correct the channels to reach the expected NF value */
+ for (i = 0; i < AH_PRIVATE(ah)->ah_nchan; i++) {
+ c = &AH_PRIVATE(ah)->ah_channels[i];
+ if (c->rawNoiseFloor >= 0)
+ continue;
+ /* Apply correction factor */
+ c->noiseFloorAdjust = ath_hal_getNfAdjust(ah, c) +
+ (IS_CHAN_5GHZ(c) ? correct5 : correct2);
+ HALDEBUG(ah, HAL_DEBUG_NFCAL, "%u/0x%x raw nf %d adjust %d\n",
+ c->channel, c->channelFlags, c->rawNoiseFloor,
+ c->noiseFloorAdjust);
+ }
+}
+
+/*
+ * INI support routines.
+ */
+
+int
+ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
+ int col, int regWr)
+{
+ int r;
+
+ for (r = 0; r < ia->rows; r++) {
+ OS_REG_WRITE(ah, HAL_INI_VAL(ia, r, 0),
+ HAL_INI_VAL(ia, r, col));
+ DMA_YIELD(regWr);
+ }
+ return regWr;
+}
+
+void
+ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, int col)
+{
+ int r;
+
+ for (r = 0; r < ia->rows; r++)
+ data[r] = HAL_INI_VAL(ia, r, col);
+}
+
+int
+ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
+ const uint32_t data[], int regWr)
+{
+ int r;
+
+ for (r = 0; r < ia->rows; r++) {
+ OS_REG_WRITE(ah, HAL_INI_VAL(ia, r, 0), data[r]);
+ DMA_YIELD(regWr);
+ }
+ return regWr;
+}
View
899 sys/external/isc/atheros_hal/dist/ah.h
@@ -0,0 +1,899 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah.h,v 1.1.1.1 2008/12/11 04:46:23 alc Exp $
+ */
+
+#ifndef _ATH_AH_H_
+#define _ATH_AH_H_
+/*
+ * Atheros Hardware Access Layer
+ *
+ * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
+ * structure for use with the device. Hardware-related operations that
+ * follow must call back into the HAL through interface, supplying the
+ * reference as the first parameter.
+ */
+
+#include "ah_osdep.h"
+
+/*
+ * __ahdecl is analogous to _cdecl; it defines the calling
+ * convention used within the HAL. For most systems this
+ * can just default to be empty and the compiler will (should)
+ * use _cdecl. For systems where _cdecl is not compatible this
+ * must be defined. See linux/ah_osdep.h for an example.
+ */
+#ifndef __ahdecl
+#define __ahdecl
+#endif
+
+/*
+ * Status codes that may be returned by the HAL. Note that
+ * interfaces that return a status code set it only when an
+ * error occurs--i.e. you cannot check it for success.
+ */
+typedef enum {
+ HAL_OK = 0, /* No error */
+ HAL_ENXIO = 1, /* No hardware present */
+ HAL_ENOMEM = 2, /* Memory allocation failed */
+ HAL_EIO = 3, /* Hardware didn't respond as expected */
+ HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
+ HAL_EEVERSION = 5, /* EEPROM version invalid */
+ HAL_EELOCKED = 6, /* EEPROM unreadable */
+ HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
+ HAL_EEREAD = 8, /* EEPROM read problem */
+ HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
+ HAL_EESIZE = 10, /* EEPROM size not supported */
+ HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
+ HAL_EINVAL = 12, /* Invalid parameter to function */
+ HAL_ENOTSUPP = 13, /* Hardware revision not supported */
+ HAL_ESELFTEST = 14, /* Hardware self-test failed */
+ HAL_EINPROGRESS = 15, /* Operation incomplete */
+} HAL_STATUS;
+
+typedef enum {
+ AH_FALSE = 0, /* NB: lots of code assumes false is zero */
+ AH_TRUE = 1,
+} HAL_BOOL;
+
+typedef enum {
+ HAL_CAP_REG_DMN = 0, /* current regulatory domain */
+ HAL_CAP_CIPHER = 1, /* hardware supports cipher */
+ HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
+ HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
+ HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
+ HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */
+ HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
+ HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
+ HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */
+ HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */
+ HAL_CAP_DIAG = 11, /* hardware diagnostic support */
+ HAL_CAP_COMPRESSION = 12, /* hardware supports compression */
+ HAL_CAP_BURST = 13, /* hardware supports packet bursting */
+ HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
+ HAL_CAP_TXPOW = 15, /* global tx power limit */
+ HAL_CAP_TPC = 16, /* per-packet tx power control */
+ HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */
+ HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */
+ HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */
+ HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */
+ /* 21 was HAL_CAP_XR */
+ HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */
+ /* 23 was HAL_CAP_CHAN_HALFRATE */
+ /* 24 was HAL_CAP_CHAN_QUARTERRATE */
+ HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */
+ HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
+ HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
+ HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
+ HAL_CAP_INTMIT = 29, /* interference mitigation */
+ HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */
+ HAL_CAP_HT = 31, /* hardware can support HT */
+ HAL_CAP_TX_CHAINMASK = 32, /* mask of TX chains supported */
+ HAL_CAP_RX_CHAINMASK = 33, /* mask of RX chains supported */
+ HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */
+ HAL_CAP_BB_HANG = 35, /* can baseband hang */
+ HAL_CAP_MAC_HANG = 36, /* can MAC hang */
+} HAL_CAPABILITY_TYPE;
+
+/*
+ * "States" for setting the LED. These correspond to
+ * the possible 802.11 operational states and there may
+ * be a many-to-one mapping between these states and the
+ * actual hardware state for the LED's (i.e. the hardware
+ * may have fewer states).
+ */
+typedef enum {
+ HAL_LED_INIT = 0,
+ HAL_LED_SCAN = 1,
+ HAL_LED_AUTH = 2,
+ HAL_LED_ASSOC = 3,
+ HAL_LED_RUN = 4
+} HAL_LED_STATE;
+
+/*
+ * Transmit queue types/numbers. These are used to tag
+ * each transmit queue in the hardware and to identify a set
+ * of transmit queues for operations such as start/stop dma.
+ */
+typedef enum {
+ HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
+ HAL_TX_QUEUE_DATA = 1, /* data xmit q's */
+ HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */
+ HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
+ HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */
+} HAL_TX_QUEUE;
+
+#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
+
+/*
+ * Transmit queue subtype. These map directly to
+ * WME Access Categories (except for UPSD). Refer
+ * to Table 5 of the WME spec.
+ */
+typedef enum {
+ HAL_WME_AC_BK = 0, /* background access category */
+ HAL_WME_AC_BE = 1, /* best effort access category*/
+ HAL_WME_AC_VI = 2, /* video access category */
+ HAL_WME_AC_VO = 3, /* voice access category */
+ HAL_WME_UPSD = 4, /* uplink power save */
+} HAL_TX_QUEUE_SUBTYPE;
+
+/*
+ * Transmit queue flags that control various
+ * operational parameters.
+ */
+typedef enum {
+ /*
+ * Per queue interrupt enables. When set the associated
+ * interrupt may be delivered for packets sent through
+ * the queue. Without these enabled no interrupts will
+ * be delivered for transmits through the queue.
+ */
+ HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
+ HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
+ HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
+ HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
+ HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
+ /*
+ * Enable hardware compression for packets sent through
+ * the queue. The compression buffer must be setup and
+ * packets must have a key entry marked in the tx descriptor.
+ */
+ HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
+ /*
+ * Disable queue when veol is hit or ready time expires.
+ * By default the queue is disabled only on reaching the
+ * physical end of queue (i.e. a null link ptr in the
+ * descriptor chain).
+ */
+ HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
+ /*
+ * Schedule frames on delivery of a DBA (DMA Beacon Alert)
+ * event. Frames will be transmitted only when this timer
+ * fires, e.g to transmit a beacon in ap or adhoc modes.
+ */
+ HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */
+ /*
+ * Each transmit queue has a counter that is incremented
+ * each time the queue is enabled and decremented when
+ * the list of frames to transmit is traversed (or when
+ * the ready time for the queue expires). This counter
+ * must be non-zero for frames to be scheduled for
+ * transmission. The following controls disable bumping
+ * this counter under certain conditions. Typically this
+ * is used to gate frames based on the contents of another
+ * queue (e.g. CAB traffic may only follow a beacon frame).
+ * These are meaningful only when frames are scheduled
+ * with a non-ASAP policy (e.g. DBA-gated).
+ */
+ HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
+ HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
+
+ /*
+ * Fragment burst backoff policy. Normally the no backoff
+ * is done after a successful transmission, the next fragment
+ * is sent at SIFS. If this flag is set backoff is done
+ * after each fragment, regardless whether it was ack'd or
+ * not, after the backoff count reaches zero a normal channel
+ * access procedure is done before the next transmit (i.e.
+ * wait AIFS instead of SIFS).
+ */
+ HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
+ /*
+ * Disable post-tx backoff following each frame.
+ */
+ HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
+ /*
+ * DCU arbiter lockout control. This controls how
+ * lower priority tx queues are handled with respect to
+ * to a specific queue when multiple queues have frames
+ * to send. No lockout means lower priority queues arbitrate
+ * concurrently with this queue. Intra-frame lockout
+ * means lower priority queues are locked out until the
+ * current frame transmits (e.g. including backoffs and bursting).
+ * Global lockout means nothing lower can arbitrary so
+ * long as there is traffic activity on this queue (frames,
+ * backoff, etc).
+ */
+ HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
+ HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
+
+ HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
+ HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */
+} HAL_TX_QUEUE_FLAGS;
+
+typedef struct {
+ uint32_t tqi_ver; /* hal TXQ version */
+ HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
+ HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
+ uint32_t tqi_priority; /* (not used) */
+ uint32_t tqi_aifs; /* aifs */
+ uint32_t tqi_cwmin; /* cwMin */
+ uint32_t tqi_cwmax; /* cwMax */
+ uint16_t tqi_shretry; /* rts retry limit */
+ uint16_t tqi_lgretry; /* long retry limit (not used)*/
+ uint32_t tqi_cbrPeriod; /* CBR period (us) */
+ uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */
+ uint32_t tqi_burstTime; /* max burst duration (us) */
+ uint32_t tqi_readyTime; /* frame schedule time (us) */
+ uint32_t tqi_compBuf; /* comp buffer phys addr */
+} HAL_TXQ_INFO;
+
+#define HAL_TQI_NONVAL 0xffff
+
+/* token to use for aifs, cwmin, cwmax */
+#define HAL_TXQ_USEDEFAULT ((uint32_t) -1)
+
+/* compression definitions */
+#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */
+#define HAL_COMP_BUF_ALIGN_SIZE 512
+
+/*
+ * Transmit packet types. This belongs in ah_desc.h, but
+ * is here so we can give a proper type to various parameters
+ * (and not require everyone include the file).
+ *
+ * NB: These values are intentionally assigned for
+ * direct use when setting up h/w descriptors.
+ */
+typedef enum {
+ HAL_PKT_TYPE_NORMAL = 0,
+ HAL_PKT_TYPE_ATIM = 1,
+ HAL_PKT_TYPE_PSPOLL = 2,
+ HAL_PKT_TYPE_BEACON = 3,
+ HAL_PKT_TYPE_PROBE_RESP = 4,
+ HAL_PKT_TYPE_CHIRP = 5,
+ HAL_PKT_TYPE_GRP_POLL = 6,
+ HAL_PKT_TYPE_AMPDU = 7,
+} HAL_PKT_TYPE;
+
+/* Rx Filter Frame Types */
+typedef enum {
+ HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
+ HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
+ HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
+ HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
+ HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
+ HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
+ HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
+ HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
+ HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */
+ HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
+} HAL_RX_FILTER;
+
+typedef enum {
+ HAL_PM_AWAKE = 0,
+ HAL_PM_FULL_SLEEP = 1,
+ HAL_PM_NETWORK_SLEEP = 2,
+ HAL_PM_UNDEFINED = 3
+} HAL_POWER_MODE;
+
+/*
+ * NOTE WELL:
+ * These are mapped to take advantage of the common locations for many of
+ * the bits on all of the currently supported MAC chips. This is to make
+ * the ISR as efficient as possible, while still abstracting HW differences.
+ * When new hardware breaks this commonality this enumerated type, as well
+ * as the HAL functions using it, must be modified. All values are directly
+ * mapped unless commented otherwise.
+ */
+typedef enum {
+ HAL_INT_RX = 0x00000001, /* Non-common mapping */
+ HAL_INT_RXDESC = 0x00000002,
+ HAL_INT_RXNOFRM = 0x00000008,
+ HAL_INT_RXEOL = 0x00000010,
+ HAL_INT_RXORN = 0x00000020,
+ HAL_INT_TX = 0x00000040, /* Non-common mapping */
+ HAL_INT_TXDESC = 0x00000080,
+ HAL_INT_TXURN = 0x00000800,
+ HAL_INT_MIB = 0x00001000,
+ HAL_INT_RXPHY = 0x00004000,
+ HAL_INT_RXKCM = 0x00008000,
+ HAL_INT_SWBA = 0x00010000,
+ HAL_INT_BMISS = 0x00040000,
+ HAL_INT_BNR = 0x00100000, /* Non-common mapping */
+ HAL_INT_TIM = 0x00200000, /* Non-common mapping */
+ HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
+ HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
+ HAL_INT_GPIO = 0x01000000,
+ HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
+ HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
+ HAL_INT_CST = 0x10000000, /* Non-common mapping */
+ HAL_INT_GTT = 0x20000000, /* Non-common mapping */
+ HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
+#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */
+ HAL_INT_BMISC = HAL_INT_TIM
+ | HAL_INT_DTIM
+ | HAL_INT_DTIMSYNC
+ | HAL_INT_CABEND,
+
+ /* Interrupt bits that map directly to ISR/IMR bits */
+ HAL_INT_COMMON = HAL_INT_RXNOFRM
+ | HAL_INT_RXDESC
+ | HAL_INT_RXEOL
+ | HAL_INT_RXORN
+ | HAL_INT_TXURN
+ | HAL_INT_TXDESC
+ | HAL_INT_MIB
+ | HAL_INT_RXPHY
+ | HAL_INT_RXKCM
+ | HAL_INT_SWBA
+ | HAL_INT_BMISS
+ | HAL_INT_GPIO,
+} HAL_INT;
+
+typedef enum {
+ HAL_RFGAIN_INACTIVE = 0,
+ HAL_RFGAIN_READ_REQUESTED = 1,
+ HAL_RFGAIN_NEED_CHANGE = 2
+} HAL_RFGAIN;
+
+/*
+ * Channels are specified by frequency.
+ */
+typedef struct {
+ uint32_t channelFlags; /* see below */
+ uint16_t channel; /* setting in Mhz */
+ uint8_t privFlags;
+ int8_t maxRegTxPower; /* max regulatory tx power in dBm */
+ int8_t maxTxPower; /* max true tx power in 0.5 dBm */
+ int8_t minTxPower; /* min true tx power in 0.5 dBm */
+} HAL_CHANNEL;
+
+/* channelFlags */
+#define CHANNEL_CW_INT 0x00002 /* CW interference detected on channel */
+#define CHANNEL_TURBO 0x00010 /* Turbo Channel */
+#define CHANNEL_CCK 0x00020 /* CCK channel */
+#define CHANNEL_OFDM 0x00040 /* OFDM channel */
+#define CHANNEL_2GHZ 0x00080 /* 2 GHz spectrum channel */
+#define CHANNEL_5GHZ 0x00100 /* 5 GHz spectrum channel */
+#define CHANNEL_PASSIVE 0x00200 /* Only passive scan allowed in the channel */
+#define CHANNEL_DYN 0x00400 /* dynamic CCK-OFDM channel */
+#define CHANNEL_STURBO 0x02000 /* Static turbo, no 11a-only usage */
+#define CHANNEL_HALF 0x04000 /* Half rate channel */
+#define CHANNEL_QUARTER 0x08000 /* Quarter rate channel */
+#define CHANNEL_HT20 0x10000 /* 11n 20MHZ channel */
+#define CHANNEL_HT40PLUS 0x20000 /* 11n 40MHZ channel w/ ext chan above */
+#define CHANNEL_HT40MINUS 0x40000 /* 11n 40MHZ channel w/ ext chan below */
+
+/* privFlags */
+#define CHANNEL_INTERFERENCE 0x01 /* Software use: channel interference
+ used for as AR as well as RADAR
+ interference detection */
+#define CHANNEL_DFS 0x02 /* DFS required on channel */
+#define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */
+#define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked for DFS */
+
+#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
+#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
+#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
+#ifdef notdef
+#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN)
+#else
+#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
+#endif
+#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
+#define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO)
+#define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
+#define CHANNEL_108A CHANNEL_T
+#define CHANNEL_G_HT20 (CHANNEL_G|CHANNEL_HT20)
+#define CHANNEL_A_HT20 (CHANNEL_A|CHANNEL_HT20)
+#define CHANNEL_G_HT40PLUS (CHANNEL_G|CHANNEL_HT40PLUS)
+#define CHANNEL_G_HT40MINUS (CHANNEL_G|CHANNEL_HT40MINUS)
+#define CHANNEL_A_HT40PLUS (CHANNEL_A|CHANNEL_HT40PLUS)
+#define CHANNEL_A_HT40MINUS (CHANNEL_A|CHANNEL_HT40MINUS)
+#define CHANNEL_ALL \
+ (CHANNEL_OFDM | CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | \
+ CHANNEL_TURBO | CHANNEL_HT20 | CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)
+#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
+
+#define HAL_ANTENNA_MIN_MODE 0
+#define HAL_ANTENNA_FIXED_A 1
+#define HAL_ANTENNA_FIXED_B 2
+#define HAL_ANTENNA_MAX_MODE 3
+
+typedef struct {
+ uint32_t ackrcv_bad;
+ uint32_t rts_bad;
+ uint32_t rts_good;
+ uint32_t fcs_bad;
+ uint32_t beacons;
+} HAL_MIB_STATS;
+
+typedef uint16_t HAL_CTRY_CODE; /* country code */
+typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */
+
+enum {
+ CTRY_DEBUG = 0x1ff, /* debug country code */
+ CTRY_DEFAULT = 0 /* default country code */
+};
+
+enum {
+ HAL_MODE_11A = 0x001, /* 11a channels */
+ HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
+ HAL_MODE_11B = 0x004, /* 11b channels */
+ HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
+#ifdef notdef
+ HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
+#else
+ HAL_MODE_11G = 0x008, /* XXX historical */
+#endif
+ HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
+ HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
+ HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */
+ HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */
+ HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */
+ HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */
+ HAL_MODE_11NG_HT20 = 0x008000,
+ HAL_MODE_11NA_HT20 = 0x010000,
+ HAL_MODE_11NG_HT40PLUS = 0x020000,
+ HAL_MODE_11NG_HT40MINUS = 0x040000,
+ HAL_MODE_11NA_HT40PLUS = 0x080000,
+ HAL_MODE_11NA_HT40MINUS = 0x100000,
+ HAL_MODE_ALL = 0xffffff
+};
+
+typedef struct {
+ int rateCount; /* NB: for proper padding */
+ uint8_t rateCodeToIndex[144]; /* back mapping */
+ struct {
+ uint8_t valid; /* valid for rate control use */
+ uint8_t phy; /* CCK/OFDM/XR */
+ uint32_t rateKbps; /* transfer rate in kbs */
+ uint8_t rateCode; /* rate for h/w descriptors */
+ uint8_t shortPreamble; /* mask for enabling short
+ * preamble in CCK rate code */
+ uint8_t dot11Rate; /* value for supported rates
+ * info element of MLME */
+ uint8_t controlRate; /* index of next lower basic
+ * rate; used for dur. calcs */
+ uint16_t lpAckDuration; /* long preamble ACK duration */
+ uint16_t spAckDuration; /* short preamble ACK duration*/
+ } info[32];
+} HAL_RATE_TABLE;
+
+typedef struct {
+ u_int rs_count; /* number of valid entries */
+ uint8_t rs_rates[32]; /* rates */
+} HAL_RATE_SET;
+
+/*
+ * 802.11n specific structures and enums
+ */
+typedef enum {
+ HAL_CHAINTYPE_TX = 1, /* Tx chain type */
+ HAL_CHAINTYPE_RX = 2, /* RX chain type */
+} HAL_CHAIN_TYPE;
+
+typedef struct {
+ u_int Tries;
+ u_int Rate;
+ u_int PktDuration;
+ u_int ChSel;
+ u_int RateFlags;
+#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
+#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
+#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
+} HAL_11N_RATE_SERIES;
+
+typedef enum {
+ HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
+ HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */
+} HAL_HT_MACMODE;
+
+typedef enum {
+ HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
+ HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */
+} HAL_HT_PHYMODE;
+
+typedef enum {
+ HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
+ HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */
+} HAL_HT_EXTPROTSPACING;
+
+
+typedef enum {
+ HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
+ HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
+} HAL_HT_RXCLEAR;
+
+/*
+ * Antenna switch control. By default antenna selection
+ * enables multiple (2) antenna use. To force use of the
+ * A or B antenna only specify a fixed setting. Fixing
+ * the antenna will also disable any diversity support.
+ */
+typedef enum {
+ HAL_ANT_VARIABLE = 0, /* variable by programming */
+ HAL_ANT_FIXED_A = 1, /* fixed antenna A */
+ HAL_ANT_FIXED_B = 2, /* fixed antenna B */
+} HAL_ANT_SETTING;
+
+typedef enum {
+ HAL_M_STA = 1, /* infrastructure station */
+ HAL_M_IBSS = 0, /* IBSS (adhoc) station */
+ HAL_M_HOSTAP = 6, /* Software Access Point */
+ HAL_M_MONITOR = 8 /* Monitor mode */
+} HAL_OPMODE;
+
+typedef struct {
+ uint8_t kv_type; /* one of HAL_CIPHER */
+ uint8_t kv_pad;
+ uint16_t kv_len; /* length in bits */
+ uint8_t kv_val[16]; /* enough for 128-bit keys */
+ uint8_t kv_mic[8]; /* TKIP MIC key */
+ uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
+} HAL_KEYVAL;
+
+typedef enum {
+ HAL_CIPHER_WEP = 0,
+ HAL_CIPHER_AES_OCB = 1,
+ HAL_CIPHER_AES_CCM = 2,
+ HAL_CIPHER_CKIP = 3,
+ HAL_CIPHER_TKIP = 4,
+ HAL_CIPHER_CLR = 5, /* no encryption */
+
+ HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
+} HAL_CIPHER;
+
+enum {
+ HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */
+ HAL_SLOT_TIME_9 = 9,
+ HAL_SLOT_TIME_20 = 20,
+};
+
+/*
+ * Per-station beacon timer state. Note that the specified
+ * beacon interval (given in TU's) can also include flags
+ * to force a TSF reset and to enable the beacon xmit logic.
+ * If bs_cfpmaxduration is non-zero the hardware is setup to
+ * coexist with a PCF-capable AP.
+ */
+typedef struct {
+ uint32_t bs_nexttbtt; /* next beacon in TU */
+ uint32_t bs_nextdtim; /* next DTIM in TU */
+ uint32_t bs_intval; /* beacon interval+flags */
+#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
+#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
+#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
+ uint32_t bs_dtimperiod;
+ uint16_t bs_cfpperiod; /* CFP period in TU */
+ uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
+ uint32_t bs_cfpnext; /* next CFP in TU */
+ uint16_t bs_timoffset; /* byte offset to TIM bitmap */
+ uint16_t bs_bmissthreshold; /* beacon miss threshold */
+ uint32_t bs_sleepduration; /* max sleep duration */
+} HAL_BEACON_STATE;
+
+/*
+ * Like HAL_BEACON_STATE but for non-station mode setup.
+ * NB: see above flag definitions for bt_intval.
+ */
+typedef struct {
+ uint32_t bt_intval; /* beacon interval+flags */
+ uint32_t bt_nexttbtt; /* next beacon in TU */
+ uint32_t bt_nextatim; /* next ATIM in TU */
+ uint32_t bt_nextdba; /* next DBA in 1/8th TU */
+ uint32_t bt_nextswba; /* next SWBA in 1/8th TU */
+ uint32_t bt_flags; /* timer enables */
+#define HAL_BEACON_TBTT_EN 0x00000001
+#define HAL_BEACON_DBA_EN 0x00000002
+#define HAL_BEACON_SWBA_EN 0x00000004
+} HAL_BEACON_TIMERS;
+
+/*
+ * Per-node statistics maintained by the driver for use in
+ * optimizing signal quality and other operational aspects.
+ */
+typedef struct {
+ uint32_t ns_avgbrssi; /* average beacon rssi */
+ uint32_t ns_avgrssi; /* average data rssi */
+ uint32_t ns_avgtxrssi; /* average tx rssi */
+} HAL_NODE_STATS;
+
+#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
+
+struct ath_desc;
+struct ath_tx_status;
+struct ath_rx_status;
+
+/*
+ * Hardware Access Layer (HAL) API.
+ *
+ * Clients of the HAL call ath_hal_attach to obtain a reference to an
+ * ath_hal structure for use with the device. Hardware-related operations
+ * that follow must call back into the HAL through interface, supplying
+ * the reference as the first parameter. Note that before using the
+ * reference returned by ath_hal_attach the caller should verify the
+ * ABI version number.
+ */
+struct ath_hal {
+ uint32_t ah_magic; /* consistency check magic number */
+ uint32_t ah_abi; /* HAL ABI version */
+#define HAL_ABI_VERSION 0x08112800 /* YYMMDDnn */
+ uint16_t ah_devid; /* PCI device ID */
+ uint16_t ah_subvendorid; /* PCI subvendor ID */
+ HAL_SOFTC ah_sc; /* back pointer to driver/os state */
+ HAL_BUS_TAG ah_st; /* params for register r+w */
+ HAL_BUS_HANDLE ah_sh;
+ HAL_CTRY_CODE ah_countryCode;
+
+ uint32_t ah_macVersion; /* MAC version id */
+ uint16_t ah_macRev; /* MAC revision */
+ uint16_t ah_phyRev; /* PHY revision */
+ /* NB: when only one radio is present the rev is in 5Ghz */
+ uint16_t ah_analog5GhzRev;/* 5GHz radio revision */
+ uint16_t ah_analog2GhzRev;/* 2GHz radio revision */
+
+ const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
+ u_int mode);
+ void __ahdecl(*ah_detach)(struct ath_hal*);
+
+ /* Reset functions */
+ HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
+ HAL_CHANNEL *, HAL_BOOL bChannelChange,
+ HAL_STATUS *status);
+ HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
+ HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
+ void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
+ HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *,
+ HAL_BOOL *);
+ HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, HAL_CHANNEL *,
+ u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
+ HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, HAL_CHANNEL *);
+ HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t);
+
+ /* Transmit functions */
+ HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
+ HAL_BOOL incTrigLevel);
+ int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
+ const HAL_TXQ_INFO *qInfo);
+ HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q,
+ const HAL_TXQ_INFO *qInfo);
+ HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q,
+ HAL_TXQ_INFO *qInfo);
+ HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
+ HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
+ uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
+ HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp);
+ uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q);
+ HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
+ HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
+ HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
+ u_int pktLen, u_int hdrLen,
+ HAL_PKT_TYPE type, u_int txPower,
+ u_int txRate0, u_int txTries0,
+ u_int keyIx, u_int antMode, u_int flags,
+ u_int rtsctsRate, u_int rtsctsDuration,
+ u_int compicvLen, u_int compivLen,
+ u_int comp);
+ HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*,
+ u_int txRate1, u_int txTries1,
+ u_int txRate2, u_int txTries2,
+ u_int txRate3, u_int txTries3);
+ HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
+ u_int segLen, HAL_BOOL firstSeg,
+ HAL_BOOL lastSeg, const struct ath_desc *);
+ HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
+ struct ath_desc *, struct ath_tx_status *);
+ void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *);
+ void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
+
+ /* Receive Functions */
+ uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
+ void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp);
+ void __ahdecl(*ah_enableReceive)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
+ void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
+ void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
+ void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
+ uint32_t filter0, uint32_t filter1);
+ HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
+ uint32_t index);
+ HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
+ uint32_t index);
+ uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
+ void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t);
+ HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
+ uint32_t size, u_int flags);
+ HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *,
+ struct ath_desc *, uint32_t phyAddr,
+ struct ath_desc *next, uint64_t tsf,
+ struct ath_rx_status *);
+ void __ahdecl(*ah_rxMonitor)(struct ath_hal *,
+ const HAL_NODE_STATS *, HAL_CHANNEL *);
+ void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
+ const HAL_NODE_STATS *);
+
+ /* Misc Functions */
+ HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
+ HAL_CAPABILITY_TYPE, uint32_t capability,
+ uint32_t *result);
+ HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *,
+ HAL_CAPABILITY_TYPE, uint32_t capability,
+ uint32_t setting, HAL_STATUS *);
+ HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request,
+ const void *args, uint32_t argsize,
+ void **result, uint32_t *resultsize);
+ void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *);
+ HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*);
+ void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *);
+ HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*);
+ HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
+ uint16_t, HAL_STATUS *);
+ void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
+ void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
+ const uint8_t *bssid, uint16_t assocId);
+ HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio);
+ HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio);
+ uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio);
+ HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,
+ uint32_t gpio, uint32_t val);
+ void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t);
+ uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
+ uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
+ void __ahdecl(*ah_resetTsf)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
+ void __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
+ HAL_MIB_STATS*);
+ HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
+ u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
+ void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int);
+ HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*,
+ HAL_ANT_SETTING);
+ HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int);
+ u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
+ u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
+ u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int);
+ u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
+ u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int);
+ void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int);
+
+ /* Key Cache Functions */
+ uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
+ HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,
+ uint16_t);
+ HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
+ uint16_t, const HAL_KEYVAL *,
+ const uint8_t *, int);
+ HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
+ uint16_t, const uint8_t *);
+
+ /* Power Management Functions */
+ HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*,
+ HAL_POWER_MODE mode, int setChip);
+ HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
+ int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *);
+
+ /* Beacon Management Functions */
+ void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
+ const HAL_BEACON_TIMERS *);
+ /* NB: deprecated, use ah_setBeaconTimers instead */
+ void __ahdecl(*ah_beaconInit)(struct ath_hal *,
+ uint32_t nexttbtt, uint32_t intval);
+ void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
+ const HAL_BEACON_STATE *);
+ void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
+
+ /* Interrupt functions */
+ HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
+ HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
+ HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
+};
+
+/*
+ * Check the PCI vendor ID and device ID against Atheros' values
+ * and return a printable description for any Atheros hardware.
+ * AH_NULL is returned if the ID's do not describe Atheros hardware.
+ */
+extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid);
+
+/*
+ * Attach the HAL for use with the specified device. The device is
+ * defined by the PCI device ID. The caller provides an opaque pointer
+ * to an upper-layer data structure (HAL_SOFTC) that is stored in the
+ * HAL state block for later use. Hardware register accesses are done
+ * using the specified bus tag and handle. On successful return a
+ * reference to a state block is returned that must be supplied in all
+ * subsequent HAL calls. Storage associated with this reference is
+ * dynamically allocated and must be freed by calling the ah_detach
+ * method when the client is done. If the attach operation fails a
+ * null (AH_NULL) reference will be returned and a status code will
+ * be returned if the status parameter is non-zero.
+ */
+extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC,
+ HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status);
+
+/*
+ * Return a list of channels available for use with the hardware.
+ * The list is based on what the hardware is capable of, the specified
+ * country code, the modeSelect mask, and whether or not outdoor
+ * channels are to be permitted.
+ *
+ * The channel list is returned in the supplied array. maxchans
+ * defines the maximum size of this array. nchans contains the actual
+ * number of channels returned. If a problem occurred or there were
+ * no channels that met the criteria then AH_FALSE is returned.
+ */
+extern HAL_BOOL __ahdecl ath_hal_init_channels(struct ath_hal *,
+ HAL_CHANNEL *chans, u_int maxchans, u_int *nchans,
+ uint8_t *regclassids, u_int maxregids, u_int *nregids,
+ HAL_CTRY_CODE cc, u_int modeSelect,
+ HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels);
+
+/*
+ * Calibrate noise floor data following a channel scan or similar.
+ * This must be called prior retrieving noise floor data.
+ */
+extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
+
+/*
+ * Return bit mask of wireless modes supported by the hardware.
+ */
+extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE);
+
+/*
+ * Calculate the transmit duration of a frame.
+ */
+extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
+ const HAL_RATE_TABLE *rates, uint32_t frameLen,
+ uint16_t rateix, HAL_BOOL shortPreamble);
+
+/*
+ * Return if device is public safety.
+ */
+extern HAL_BOOL __ahdecl ath_hal_ispublicsafetysku(struct ath_hal *);
+
+/*
+ * Return if device is operating in 900 MHz band.
+ */
+extern HAL_BOOL ath_hal_isgsmsku(struct ath_hal *);
+
+/*
+ * Convert between IEEE channel number and channel frequency
+ * using the specified channel flags; e.g. CHANNEL_2GHZ.
+ */
+extern int __ahdecl ath_hal_mhz2ieee(struct ath_hal *, u_int mhz, u_int flags);
+#endif /* _ATH_AH_H_ */
View
49 sys/external/isc/atheros_hal/dist/ah_debug.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_debug.h,v 1.1.1.1 2008/12/11 04:46:23 alc Exp $
+ */
+#ifndef _ATH_AH_DEBUG_H_
+#define _ATH_AH_DEBUG_H_
+/*
+ * Atheros Device Hardware Access Layer (HAL).
+ *
+ * Debug mask definitions.
+ */
+enum {
+ HAL_DEBUG_REGDOMAIN = 0x00000001, /* regulatory handling */
+ HAL_DEBUG_ATTACH = 0x00000002, /* work done in attach */
+ HAL_DEBUG_RESET = 0x00000004, /* reset work */
+ HAL_DEBUG_NFCAL = 0x00000008, /* noise floor calibration */
+ HAL_DEBUG_PERCAL = 0x00000010, /* periodic calibration */
+ HAL_DEBUG_ANI = 0x00000020, /* ANI operation */
+ HAL_DEBUG_PHYIO = 0x00000040, /* phy i/o operations */
+ HAL_DEBUG_REGIO = 0x00000080, /* register i/o operations */
+ HAL_DEBUG_RFPARAM = 0x00000100,
+ HAL_DEBUG_TXQUEUE = 0x00000200, /* tx queue handling */
+ HAL_DEBUG_TX = 0x00000400,
+ HAL_DEBUG_TXDESC = 0x00000800,
+ HAL_DEBUG_RX = 0x00001000,
+ HAL_DEBUG_RXDESC = 0x00002000,
+ HAL_DEBUG_KEYCACHE = 0x00004000, /* keycache handling */
+ HAL_DEBUG_EEPROM = 0x00008000,
+ HAL_DEBUG_BEACON = 0x00010000, /* beacon setup work */
+ HAL_DEBUG_POWER = 0x00020000, /* power management */
+ HAL_DEBUG_INTERRUPT = 0x00000080, /* interrupt handling */
+
+ HAL_DEBUG_ANY = 0xffffffff
+};
+#endif /* _ATH_AH_DEBUG_H_ */
View
55 sys/external/isc/atheros_hal/dist/ah_decode.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_decode.h,v 1.1.1.1 2008/12/11 04:46:23 alc Exp $
+ */
+#ifndef _ATH_AH_DECODE_H_
+#define _ATH_AH_DECODE_H_
+/*
+ * Register tracing support.
+ *
+ * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
+ * writes to the file /tmp/ath_hal.log. The file format is a simple
+ * fixed-size array of records. When done logging set hw.ath.hal.alq=0
+ * and then decode the file with the arcode program (that is part of the
+ * HAL). If you start+stop tracing the data will be appended to an
+ * existing file.
+ */
+struct athregrec {
+ uint32_t op : 8,
+ reg : 24;
+ uint32_t val;
+};
+
+enum {
+ OP_READ = 0, /* register read */
+ OP_WRITE = 1, /* register write */
+ OP_DEVICE = 2, /* device identification */
+ OP_MARK = 3, /* application marker */
+};
+
+enum {
+ AH_MARK_RESET, /* ar*Reset entry, bChannelChange */
+ AH_MARK_RESET_LINE, /* ar*_reset.c, line %d */
+ AH_MARK_RESET_DONE, /* ar*Reset exit, error code */
+ AH_MARK_CHIPRESET, /* ar*ChipReset, channel num */
+ AH_MARK_PERCAL, /* ar*PerCalibration, channel num */
+ AH_MARK_SETCHANNEL, /* ar*SetChannel, channel num */
+ AH_MARK_ANI_RESET, /* ar*AniReset, opmode */
+ AH_MARK_ANI_POLL, /* ar*AniReset, listen time */
+ AH_MARK_ANI_CONTROL, /* ar*AniReset, cmd */
+};
+#endif /* _ATH_AH_DECODE_H_ */
View
220 sys/external/isc/atheros_hal/dist/ah_desc.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_desc.h,v 1.1.1.1 2008/12/11 04:46:23 alc Exp $
+ */
+
+#ifndef _DEV_ATH_DESC_H
+#define _DEV_ATH_DESC_H
+
+#include "opt_ah.h" /* NB: required for AH_SUPPORT_AR5416 */
+
+/*
+ * Transmit descriptor status. This structure is filled
+ * in only after the tx descriptor process method finds a
+ * ``done'' descriptor; at which point it returns something
+ * other than HAL_EINPROGRESS.
+ *
+ * Note that ts_antenna may not be valid for all h/w. It
+ * should be used only if non-zero.
+ */
+struct ath_tx_status {
+ uint16_t ts_seqnum; /* h/w assigned sequence number */
+ uint16_t ts_tstamp; /* h/w assigned timestamp */
+ uint8_t ts_status; /* frame status, 0 => xmit ok */
+ uint8_t ts_rate; /* h/w transmit rate index */
+#define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */
+ int8_t ts_rssi; /* tx ack RSSI */
+ uint8_t ts_shortretry; /* # short retries */
+ uint8_t ts_longretry; /* # long retries */
+ uint8_t ts_virtcol; /* virtual collision count */
+ uint8_t ts_antenna; /* antenna information */
+ uint8_t ts_finaltsi; /* final transmit series index */
+#ifdef AH_SUPPORT_AR5416
+ /* 802.11n status */
+ uint8_t ts_flags; /* misc flags */
+ int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */
+ int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */
+/* #define ts_rssi ts_rssi_combined */
+ uint32_t ts_ba_low; /* blockack bitmap low */
+ uint32_t ts_ba_high; /* blockack bitmap high */
+ uint32_t ts_evm0; /* evm bytes */
+ uint32_t ts_evm1;
+ uint32_t ts_evm2;
+#endif /* AH_SUPPORT_AR5416 */
+};
+
+/* bits found in ts_status */
+#define HAL_TXERR_XRETRY 0x01 /* excessive retries */
+#define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */
+#define HAL_TXERR_FIFO 0x04 /* fifo underrun */
+#define HAL_TXERR_XTXOP 0x08 /* txop exceeded */
+#define HAL_TXERR_TIMER_EXPIRED 0x10 /* Tx timer expired */
+
+/* bits found in ts_flags */
+#define HAL_TX_BA 0x01 /* Block Ack seen */
+#define HAL_TX_AGGR 0x02 /* Aggregate */
+#define HAL_TX_DESC_CFG_ERR 0x10 /* Error in 20/40 desc config */
+#define HAL_TX_DATA_UNDERRUN 0x20 /* Tx buffer underrun */
+#define HAL_TX_DELIM_UNDERRUN 0x40 /* Tx delimiter underrun */
+
+/*
+ * Receive descriptor status. This structure is filled
+ * in only after the rx descriptor process method finds a
+ * ``done'' descriptor; at which point it returns something
+ * other than HAL_EINPROGRESS.
+ *
+ * If rx_status is zero, then the frame was received ok;
+ * otherwise the error information is indicated and rs_phyerr
+ * contains a phy error code if HAL_RXERR_PHY is set. In general
+ * the frame contents is undefined when an error occurred thought
+ * for some errors (e.g. a decryption error), it may be meaningful.
+ *
+ * Note that the receive timestamp is expanded using the TSF to
+ * at least 15 bits (regardless of what the h/w provides directly).
+ * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to
+ * find out if the hardware is capable.
+ *
+ * rx_rssi is in units of dbm above the noise floor. This value
+ * is measured during the preamble and PLCP; i.e. with the initial
+ * 4us of detection. The noise floor is typically a consistent
+ * -96dBm absolute power in a 20MHz channel.
+ */
+struct ath_rx_status {
+ uint16_t rs_datalen; /* rx frame length */
+ uint8_t rs_status; /* rx status, 0 => recv ok */
+ uint8_t rs_phyerr; /* phy error code */
+ int8_t rs_rssi; /* rx frame RSSI (combined for 11n) */
+ uint8_t rs_keyix; /* key cache index */
+ uint8_t rs_rate; /* h/w receive rate index */
+ uint8_t rs_more; /* more descriptors follow */
+ uint32_t rs_tstamp; /* h/w assigned timestamp */
+ uint32_t rs_antenna; /* antenna information */
+#ifdef AH_SUPPORT_AR5416
+ /* 802.11n status */
+ int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */
+ int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */
+ uint8_t rs_isaggr; /* is part of the aggregate */
+ uint8_t rs_moreaggr; /* more frames in aggr to follow */
+ uint8_t rs_num_delims; /* number of delims in aggr */
+ uint8_t rs_flags; /* misc flags */
+ uint32_t rs_evm0; /* evm bytes */
+ uint32_t rs_evm1;
+ uint32_t rs_evm2;
+#endif /* AH_SUPPORT_AR5416 */
+};
+
+/* bits found in rs_status */
+#define HAL_RXERR_CRC 0x01 /* CRC error on frame */
+#define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */
+#define HAL_RXERR_FIFO 0x04 /* fifo overrun */
+#define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */
+#define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */
+
+/* bits found in rs_flags */
+#define HAL_RX_MORE 0x01 /* more descriptors follow */
+#define HAL_RX_MORE_AGGR 0x02 /* more frames in aggr */
+#define HAL_RX_GI 0x04 /* full gi */
+#define HAL_RX_2040 0x08 /* 40 Mhz */
+#define HAL_RX_DELIM_CRC_PRE 0x10 /* crc error in delimiter pre */
+#define HAL_RX_DELIM_CRC_POST 0x20 /* crc error in delim after */
+#define HAL_RX_DECRYPT_BUSY 0x40 /* decrypt was too slow */
+#define HAL_RX_HI_RX_CHAIN 0x80 /* SM power save: hi Rx chain control */
+
+enum {
+ HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */
+ HAL_PHYERR_TIMING = 1, /* Timing error */
+ HAL_PHYERR_PARITY = 2, /* Illegal parity */
+ HAL_PHYERR_RATE = 3, /* Illegal rate */
+ HAL_PHYERR_LENGTH = 4, /* Illegal length */
+ HAL_PHYERR_RADAR = 5, /* Radar detect */
+ HAL_PHYERR_SERVICE = 6, /* Illegal service */
+ HAL_PHYERR_TOR = 7, /* Transmit override receive */
+ /* NB: these are specific to the 5212 */
+ HAL_PHYERR_OFDM_TIMING = 17, /* */
+ HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */
+ HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */
+ HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */
+ HAL_PHYERR_OFDM_POWER_DROP = 21, /* */
+ HAL_PHYERR_OFDM_SERVICE = 22, /* */
+ HAL_PHYERR_OFDM_RESTART = 23, /* */
+ HAL_PHYERR_CCK_TIMING = 25, /* */
+ HAL_PHYERR_CCK_HEADER_CRC = 26, /* */
+ HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */
+ HAL_PHYERR_CCK_SERVICE = 30, /* */
+ HAL_PHYERR_CCK_RESTART = 31, /* */
+};
+
+/* value found in rs_keyix to mark invalid entries */
+#define HAL_RXKEYIX_INVALID ((uint8_t) -1)
+/* value used to specify no encryption key for xmit */
+#define HAL_TXKEYIX_INVALID ((u_int) -1)
+
+/* XXX rs_antenna definitions */
+
+/*
+ * Definitions for the software frame/packet descriptors used by
+ * the Atheros HAL. This definition obscures hardware-specific
+ * details from the driver. Drivers are expected to fillin the
+ * portions of a descriptor that are not opaque then use HAL calls
+ * to complete the work. Status for completed frames is returned
+ * in a device-independent format.
+ */
+#ifdef AH_SUPPORT_AR5416
+#define HAL_DESC_HW_SIZE 20
+#else
+#define HAL_DESC_HW_SIZE 4
+#endif /* AH_SUPPORT_AR5416 */
+
+struct ath_desc {
+ /*
+ * The following definitions are passed directly
+ * the hardware and managed by the HAL. Drivers
+ * should not touch those elements marked opaque.
+ */
+ uint32_t ds_link; /* phys address of next descriptor */
+ uint32_t ds_data; /* phys address of data buffer */
+ uint32_t ds_ctl0; /* opaque DMA control 0 */
+ uint32_t ds_ctl1; /* opaque DMA control 1 */
+ uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */
+};
+
+struct ath_desc_status {
+ union {
+ struct ath_tx_status tx;/* xmit status */
+ struct ath_rx_status rx;/* recv status */
+ } ds_us;
+};
+
+#define ds_txstat ds_us.tx
+#define ds_rxstat ds_us.rx
+
+/* flags passed to tx descriptor setup methods */
+#define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */
+#define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */
+#define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */
+#define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */
+#define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */
+#define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */
+/* NB: this only affects frame, not any RTS/CTS */
+#define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */
+#define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */
+#define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */
+#define HAL_TXDESC_VMF 0x0200 /* virtual more frag */
+
+/* flags passed to rx descriptor setup methods */
+#define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */
+#endif /* _DEV_ATH_DESC_H */
View
84 sys/external/isc/atheros_hal/dist/ah_devid.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_devid.h,v 1.1.1.1 2008/12/11 04:46:23 alc Exp $
+ */
+
+#ifndef _DEV_ATH_DEVID_H_
+#define _DEV_ATH_DEVID_H_
+
+#define ATHEROS_VENDOR_ID 0x168c /* Atheros PCI vendor ID */
+/*
+ * NB: all Atheros-based devices should have a PCI vendor ID
+ * of 0x168c, but some vendors, in their infinite wisdom
+ * do not follow this so we must handle them specially.
+ */
+#define ATHEROS_3COM_VENDOR_ID 0xa727 /* 3Com 3CRPAG175 vendor ID */
+#define ATHEROS_3COM2_VENDOR_ID 0x10b7 /* 3Com 3CRDAG675 vendor ID */
+
+/* AR5210 (for reference) */
+#define AR5210_DEFAULT 0x1107 /* No eeprom HW default */
+#define AR5210_PROD 0x0007 /* Final device ID */
+#define AR5210_AP 0x0207 /* Early AP11s */
+
+/* AR5211 */
+#define AR5211_DEFAULT 0x1112 /* No eeprom HW default */
+#define AR5311_DEVID 0x0011 /* Final ar5311 devid */
+#define AR5211_DEVID 0x0012 /* Final ar5211 devid */
+#define AR5211_LEGACY 0xff12 /* Original emulation board */
+#define AR5211_FPGA11B 0xf11b /* 11b emulation board */
+
+/* AR5212 */
+#define AR5212_DEFAULT 0x1113 /* No eeprom HW default */
+#define AR5212_DEVID 0x0013 /* Final ar5212 devid */
+#define AR5212_FPGA 0xf013 /* Emulation board */
+#define AR5212_DEVID_IBM 0x1014 /* IBM minipci ID */
+#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
+#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
+#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
+#define AR5212_AR2315_REV6 0x0086 /* AR2315 WMAC (AP51-Light) */
+#define AR5212_AR2315_REV7 0x0087 /* AR2315 WMAC (AP51-Full) */
+#define AR5212_AR2317_REV1 0x0090 /* AR2317 WMAC (AP61-Light) */
+#define AR5212_AR2317_REV2 0x0091 /* AR2317 WMAC (AP61-Full) */
+
+/* AR5212 compatible devid's also attach to 5212 */
+#define AR5212_DEVID_0014 0x0014
+#define AR5212_DEVID_0015 0x0015
+#define AR5212_DEVID_0016 0x0016
+#define AR5212_DEVID_0017 0x0017
+#define AR5212_DEVID_0018 0x0018
+#define AR5212_DEVID_0019 0x0019
+#define AR5212_AR2413 0x001a /* AR2413 aka Griffin-lite */
+#define AR5212_AR5413 0x001b /* Eagle */
+#define AR5212_AR5424 0x001c /* Condor (PCI express) */
+#define AR5212_AR2417 0x001d /* Nala, PCI */
+#define AR5212_DEVID_FF19 0xff19 /* XXX PCI express */
+
+/* AR5213 */
+#define AR5213_SREV_1_0 0x0055
+#define AR5213_SREV_REG 0x4020
+
+/* AR5416 compatible devid's */
+#define AR5416_DEVID_PCI 0x0023 /* AR5416 PCI (MB/CB) Owl */
+#define AR5416_DEVID_PCIE 0x0024 /* AR5416 PCI-E (XB) Owl */
+#define AR9160_DEVID_PCI 0x0027 /* AR9160 PCI Sowl */
+#define AR9280_DEVID_PCI 0x0029 /* AR9280 PCI Merlin */
+#define AR9280_DEVID_PCIE 0x002a /* AR9280 PCI-E Merlin */
+#define AR9285_DEVID_PCIE 0x002b /* AR9285 PCI-E Kite */
+
+#define AR_SUBVENDOR_ID_NOG 0x0e11 /* No 11G subvendor ID */
+#define AR_SUBVENDOR_ID_NEW_A 0x7065 /* Update device to new RD */
+#endif /* _DEV_ATH_DEVID_H */
View
133 sys/external/isc/atheros_hal/dist/ah_eeprom.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_eeprom.h,v 1.1.1.1 2008/12/11 04:46:23 alc Exp $
+ */
+#ifndef _ATH_AH_EEPROM_H_
+#define _ATH_AH_EEPROM_H_
+
+#define AR_EEPROM_VER1 0x1000 /* Version 1.0; 5210 only */
+/*
+ * Version 3 EEPROMs are all 16K.
+ * 3.1 adds turbo limit, antenna gain, 16 CTL's, 11g info,
+ * and 2.4Ghz ob/db for B & G
+ * 3.2 has more accurate pcdac intercepts and analog chip
+ * calibration.
+ * 3.3 adds ctl in-band limit, 32 ctl's, and frequency
+ * expansion
+ * 3.4 adds xr power, gainI, and 2.4 turbo params
+ */
+#define AR_EEPROM_VER3 0x3000 /* Version 3.0; start of 16k EEPROM */
+#define AR_EEPROM_VER3_1 0x3001 /* Version 3.1 */
+#define AR_EEPROM_VER3_2 0x3002 /* Version 3.2 */
+#define AR_EEPROM_VER3_3 0x3003 /* Version 3.3 */
+#define AR_EEPROM_VER3_4 0x3004 /* Version 3.4 */
+#define AR_EEPROM_VER4 0x4000 /* Version 4.x */
+#define AR_EEPROM_VER4_0 0x4000 /* Version 4.0 */
+#define AR_EEPROM_VER4_1 0x4001 /* Version 4.0 */
+#define AR_EEPROM_VER4_2 0x4002 /* Version 4.0 */
+#define AR_EEPROM_VER4_3 0x4003 /* Version 4.0 */
+#define AR_EEPROM_VER4_6 0x4006 /* Version 4.0 */
+#define AR_EEPROM_VER4_7 0x3007 /* Version 4.7 */
+#define AR_EEPROM_VER4_9 0x4009 /* EEPROM EAR futureproofing */
+#define AR_EEPROM_VER5 0x5000 /* Version 5.x */
+#define AR_EEPROM_VER5_0 0x5000 /* Adds new 2413 cal powers and added params */
+#define AR_EEPROM_VER5_1 0x5001 /* Adds capability values */
+#define AR_EEPROM_VER5_3 0x5003 /* Adds spur mitigation table */
+#define AR_EEPROM_VER5_4 0x5004
+/*
+ * Version 14 EEPROMs came in with AR5416.
+ * 14.2 adds txFrameToPaOn, txFrameToDataStart, ht40PowerInc
+ * 14.3 adds bswAtten, bswMargin, swSettle, and base OpFlags for HT20/40
+ */
+#define AR_EEPROM_VER14 0xE000 /* Version 14.x */
+#define AR_EEPROM_VER14_1 0xE001 /* Adds 11n support */
+#define AR_EEPROM_VER14_2 0xE002
+#define AR_EEPROM_VER14_3 0xE003
+#define AR_EEPROM_VER14_7 0xE007
+#define AR_EEPROM_VER14_9 0xE009
+#define AR_EEPROM_VER14_16 0xE010
+#define AR_EEPROM_VER14_17 0xE011
+#define AR_EEPROM_VER14_19 0xE013
+
+enum {
+ AR_EEP_RFKILL, /* use ath_hal_eepromGetFlag */
+ AR_EEP_AMODE, /* use ath_hal_eepromGetFlag */
+ AR_EEP_BMODE, /* use ath_hal_eepromGetFlag */
+ AR_EEP_GMODE, /* use ath_hal_eepromGetFlag */
+ AR_EEP_TURBO5DISABLE, /* use ath_hal_eepromGetFlag */
+ AR_EEP_TURBO2DISABLE, /* use ath_hal_eepromGetFlag */
+ AR_EEP_ISTALON, /* use ath_hal_eepromGetFlag */
+ AR_EEP_32KHZCRYSTAL, /* use ath_hal_eepromGetFlag */
+ AR_EEP_MACADDR, /* uint8_t* */
+ AR_EEP_COMPRESS, /* use ath_hal_eepromGetFlag */
+ AR_EEP_FASTFRAME, /* use ath_hal_eepromGetFlag */
+ AR_EEP_AES, /* use ath_hal_eepromGetFlag */
+ AR_EEP_BURST, /* use ath_hal_eepromGetFlag */
+ AR_EEP_MAXQCU, /* uint16_t* */
+ AR_EEP_KCENTRIES, /* uint16_t* */
+ AR_EEP_NFTHRESH_5, /* int16_t* */
+ AR_EEP_NFTHRESH_2, /* int16_t* */
+ AR_EEP_REGDMN_0, /* uint16_t* */
+ AR_EEP_REGDMN_1, /* uint16_t* */
+ AR_EEP_OPCAP, /* uint16_t* */
+ AR_EEP_OPMODE, /* uint16_t* */
+ AR_EEP_RFSILENT, /* uint16_t* */
+ AR_EEP_OB_5, /* uint8_t* */
+ AR_EEP_DB_5, /* uint8_t* */
+ AR_EEP_OB_2, /* uint8_t* */
+ AR_EEP_DB_2, /* uint8_t* */
+ AR_EEP_TXMASK, /* uint8_t* */
+ AR_EEP_RXMASK, /* uint8_t* */
+ AR_EEP_RXGAIN_TYPE, /* uint8_t* */
+ AR_EEP_TXGAIN_TYPE, /* uint8_t* */
+ AR_EEP_OL_PWRCTRL, /* use ath_hal_eepromGetFlag */
+ AR_EEP_FSTCLK_5G, /* use ath_hal_eepromGetFlag */
+ AR_EEP_ANTGAINMAX_5, /* int8_t* */
+ AR_EEP_ANTGAINMAX_2, /* int8_t* */
+ AR_EEP_WRITEPROTECT, /* use ath_hal_eepromGetFlag */
+};
+
+typedef struct {
+ uint16_t rdEdge;
+ uint16_t twice_rdEdgePower;
+ HAL_BOOL flag;
+} RD_EDGES_POWER;
+
+/* XXX should probably be version-dependent */
+#define SD_NO_CTL 0xf0
+#define NO_CTL 0xff
+#define CTL_MODE_M 0x0f
+#define CTL_11A 0
+#define CTL_11B 1
+#define CTL_11G 2
+#define CTL_TURBO 3
+#define CTL_108G 4
+#define CTL_2GHT20 5
+#define CTL_5GHT20 6
+#define CTL_2GHT40 7
+#define CTL_5GHT40 8
+
+#define AR_NO_SPUR 0x8000
+
+/* XXX exposed to chip code */
+#define MAX_RATE_POWER 63
+
+HAL_STATUS ath_hal_v1EepromAttach(struct ath_hal *ah);
+HAL_STATUS ath_hal_legacyEepromAttach(struct ath_hal *ah);
+HAL_STATUS ath_hal_v14EepromAttach(struct ath_hal *ah);
+HAL_STATUS ath_hal_v4kEepromAttach(struct ath_hal *ah);
+#endif /* _ATH_AH_EEPROM_H_ */
View
253 sys/external/isc/atheros_hal/dist/ah_eeprom_v1.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2008 Sam Leffler, Errno Consulting
+ * Copyright (c) 2008 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * $Id: ah_eeprom_v1.c,v 1.1.1.1 2008/12/11 04:46:23 alc Exp $
+ */
+#include "opt_ah.h"
+
+#include "ah.h"
+#include "ah_internal.h"
+#include "ah_eeprom_v1.h"
+
+static HAL_STATUS
+v1EepromGet(struct ath_hal *ah, int param, void *val)
+{
+ HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
+ uint32_t sum;
+ uint16_t eeval;
+ uint8_t *macaddr;
+ int i;
+
+ switch (param) {
+ case AR_EEP_MACADDR: /* Get MAC Address */
+ sum = 0;
+ macaddr = val;
+ for (i = 0; i < 3; i++) {
+ if (!ath_hal_eepromRead(ah, AR_EEPROM_MAC(i), &eeval)) {
+ HALDEBUG(ah, HAL_DEBUG_ANY,
+ "%s: cannot read EEPROM location %u\n",
+ __func__, i);
+ return HAL_EEREAD;
+ }
+ sum += eeval;
+ macaddr[2*i + 0] = eeval >> 8;
+ macaddr[2*i + 1] = eeval & 0xff;
+ }
+ if (sum == 0 || sum == 0xffff*3) {
+ HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n",
+ __func__, ath_hal_ether_sprintf(macaddr));
+ return HAL_EEBADMAC;
+ }
+ return HAL_OK;
+ case AR_EEP_REGDMN_0:
+ *(uint16_t *) val = ee->ee_regDomain[0];
+ return HAL_OK;
+ case AR_EEP_RFKILL:
+ HALASSERT(val == AH_NULL);
+ return ee->ee_rfKill ? HAL_OK : HAL_EIO;
+ case AR_EEP_WRITEPROTECT:
+ HALASSERT(val == AH_NULL);
+ return (ee->ee_protect & AR_EEPROM_PROTOTECT_WP_128_191) ?
+ HAL_OK : HAL_EIO;
+ default:
+ HALASSERT(0);
+ return HAL_EINVAL;
+ }
+}
+
+static HAL_BOOL
+v1EepromSet(struct ath_hal *ah, int param, int v)
+{
+ return HAL_EINVAL;
+}
+
+static HAL_BOOL
+v1EepromDiag(struct ath_hal *ah, int request,
+ const void *args, uint32_t argsize, void **result, uint32_t *resultsize)