Skip to content
Browse files

Import madwifi's HAL of 19-jul-2004

  • Loading branch information...
1 parent 6764bd9 commit 4f01909fe0a4f27366659ac37fa6431ef9f52b8d dyoung committed Jul 19, 2004
View
58 contrib/sys/arch/i386/dev/athhal-elf-o.inc
@@ -0,0 +1,58 @@
+#
+# Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer,
+# without modification.
+# 2. Redistributions in binary form must reproduce at minimum a disclaimer
+# similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+# redistribution must be conditioned upon including a substantially
+# similar Disclaimer requirement for further binary redistribution.
+# 3. Neither the names of the above-listed copyright holders nor the names
+# of any contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# Alternatively, this software may be distributed under the terms of the
+# GNU General Public License ("GPL") version 2 as published by the Free
+# Software Foundation.
+#
+# NO WARRANTY
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+# AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+# THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+# IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+# THE POSSIBILITY OF SUCH DAMAGES.
+#
+# $Id: athhal-elf-o.inc,v 1.1.1.1 2004/07/19 23:51:18 dyoung Exp $
+#
+
+#
+# Compilation configuration for building i386-elf.
+# This assumes the build platform is also i386-elf.
+#
+
+#
+ifndef TOOLPREFIX
+TOOLPREFIX=
+endif
+#
+CC= ${TOOLPREFIX}gcc
+LD= ${TOOLPREFIX}ld
+STRIP= ${TOOLPREFIX}strip
+OBJCOPY=${TOOLPREFIX}objcopy
+NM= ${TOOLPREFIX}nm
+
+COPTS+= -DAH_BYTE_ORDER=AH_LITTLE_ENDIAN
+ifndef CONFIG_FRAME_POINTER
+COPTS+= -fomit-frame-pointer
+endif
View
6,360 contrib/sys/arch/i386/dev/athhal-elf-o.uue
2,893 additions, 3,467 deletions not shown because the diff is too large. Please use a local Git client to view these changes.
View
7 contrib/sys/arch/i386/dev/athhal_opt.h
@@ -1,3 +1,4 @@
-#define AH_SUPPORT_AR5210 1
-#define AH_SUPPORT_AR5211 1
-#define AH_SUPPORT_AR5212 1
+#define AH_SUPPORT_AR5210 1
+#define AH_SUPPORT_AR5211 1
+#define AH_SUPPORT_AR5212 1
+#define AH_ENABLE_TX_TPC 1
View
4 contrib/sys/dev/ic/athhal-COPYRIGHT
@@ -4,7 +4,7 @@ copyright does _NOT_ contain a "or GPL" clause and does _NOT_ permit
redistribution with changes.
/*-
- * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
+ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros
* Communications, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms are permitted
@@ -38,5 +38,5 @@ redistribution with changes.
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGES.
*
- * $Id: COPYRIGHT,v 1.2 2003/06/25 04:50:21 sam Exp $
+ * $Id: COPYRIGHT,v 1.2 2004/05/15 22:26:24 samleffler Exp $
*/
View
6 contrib/sys/dev/ic/athhal-README
@@ -1,4 +1,4 @@
-$Id: README,v 1.2 2003/07/02 01:55:27 sam Exp $
+$Id: README,v 1.2 2004/05/15 22:26:25 samleffler Exp $
WARNING: THIS IS A BETA DISTRIBUTION. THIS SOFTWARE HAS KNOWN PROBLEMS AND
@@ -9,8 +9,8 @@ WARNING: USE AT YOUR OWN RISK!
Atheros Hardware Access Layer (HAL)
===================================
-* Copyright (c) 2002, 2003 Sam Leffler.
-* Copyright (c) 2002, 2003 Atheros Communications, Inc.
+* Copyright (c) 2002-2004 Sam Leffler.
+* Copyright (c) 2002-2004 Atheros Communications, Inc.
* All rights reserved.
Read the file COPYRIGHT for the complete copyright.
View
288 contrib/sys/dev/ic/athhal.h
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
+ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros
* Communications, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms are permitted
@@ -33,7 +33,7 @@
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGES.
*
- * $Id: ah.h,v 1.45 2003/12/06 22:58:09 sam Exp $
+ * $Id: ah.h,v 1.3 2004/06/09 16:33:48 samleffler Exp $
*/
#ifndef _ATH_AH_H_
@@ -49,6 +49,17 @@
#include "ah_osdep.h"
/*
+ * __ahdecl is analogous to _cdecl; it defines the calling
+ * convention used within the HAL. For most systems this
+ * can just default to be empty and the compiler will (should)
+ * use _cdecl. For systems where _cdecl is not compatible this
+ * must be defined. See linux/ah_osdep.h for an example.
+ */
+#ifndef __ahdecl
+#define __ahdecl
+#endif
+
+/*
* Status codes that may be returned by the HAL. Note that
* interfaces that return a status code set it only when an
* error occurs--i.e. you cannot check it for success.
@@ -77,6 +88,13 @@ typedef enum {
AH_TRUE = 1,
} HAL_BOOL;
+typedef enum {
+ HAL_CAP_REG_DMN = 0, /* current regulatory domain */
+ HAL_CAP_CIPHER = 1, /* hardware supports cipher */
+ HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
+ HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
+} HAL_CAPABILITY_TYPE;
+
/*
* "States" for setting the LED. These correspond to
* the possible 802.11 operational states and there may
@@ -108,6 +126,48 @@ typedef enum {
#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
/*
+ * Transmit queue subtype. These map directly to
+ * WME Access Categories (except for UPSD). Refer
+ * to Table 5 of the WME spec.
+ */
+typedef enum {
+ HAL_WME_AC_BK = 0, /* background access category */
+ HAL_WME_AC_BE = 1, /* best effort access category*/
+ HAL_WME_AC_VI = 2, /* video access category */
+ HAL_WME_AC_VO = 3, /* voice access category */
+ HAL_WME_UPSD = 4, /* uplink power save */
+} HAL_TX_QUEUE_SUBTYPE;
+
+/*
+ * Transmit queue flags that control various
+ * operational parameters.
+ */
+typedef enum {
+ TXQ_FLAG_TXINT_ENABLE = 0x0001, /* TXOK,TXERR Interrupts */
+ TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, /* TXDESC Interrupts */
+ TXQ_FLAG_BACKOFF_DISABLE = 0x0004, /* disable Post Backoff */
+ TXQ_FLAG_COMPRESSION_ENABLE = 0x0008, /* compression enabled */
+ TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0010, /* enable ready time
+ expiry policy */
+ TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0020, /* enable backoff while
+ sending fragment burst*/
+} HAL_TX_QUEUE_FLAGS;
+
+typedef struct {
+ u_int32_t tqi_ver; /* hal TXQ version */
+ HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
+ HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
+ u_int32_t tqi_priority;
+ u_int32_t tqi_aifs; /* AIFS shift */
+ int32_t tqi_cwmin; /* cwMin shift */
+ int32_t tqi_cwmax; /* cwMax shift */
+ u_int32_t tqi_cbrPeriod;
+ u_int32_t tqi_cbrOverflowLimit;
+ u_int32_t tqi_burstTime;
+ u_int32_t tqi_readyTime;
+} HAL_TXQ_INFO;
+
+/*
* Transmit packet types. This belongs in ah_desc.h, but
* is here so we can give a proper type to various parameters
* (and not require everyone include the file).
@@ -212,6 +272,7 @@ typedef struct {
#define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */
#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */
#define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */
+#define CHANNEL_XR 0x0800 /* XR channel */
#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
@@ -222,6 +283,8 @@ typedef struct {
#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
#endif
#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
+#define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
+#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
#define CHANNEL_ALL \
(CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_5GHZ|CHANNEL_2GHZ|CHANNEL_TURBO)
#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
@@ -252,6 +315,7 @@ enum {
#else
HAL_MODE_11G = 0x008,
#endif
+ HAL_MODE_108G = 0x020,
HAL_MODE_ALL = 0xfff
};
@@ -291,14 +355,22 @@ typedef enum {
} HAL_OPMODE;
typedef struct {
- int wk_len;
- u_int8_t wk_key[16]; /* XXX big enough for WEP */
+ u_int8_t kv_type; /* one of HAL_CIPHER */
+ u_int8_t kv_pad;
+ u_int16_t kv_len; /* length in bits */
+ u_int8_t kv_val[16]; /* enough for 128-bit keys */
+ u_int8_t kv_mic[8]; /* TKIP MIC key */
} HAL_KEYVAL;
typedef enum {
HAL_CIPHER_WEP = 0,
- HAL_CIPHER_AES_CCM = 1,
- HAL_CIPHER_CKIP = 2
+ HAL_CIPHER_AES_OCB = 1,
+ HAL_CIPHER_AES_CCM = 2,
+ HAL_CIPHER_CKIP = 3,
+ HAL_CIPHER_TKIP = 4,
+ HAL_CIPHER_CLR = 5, /* no encryption */
+
+ HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
} HAL_CIPHER;
enum {
@@ -307,12 +379,17 @@ enum {
};
/*
- * Per-station beacon timer state.
+ * Per-station beacon timer state. Note that the specified
+ * beacon interval (given in TU's) can also include flags
+ * to force a TSF reset and to enable the beacon xmit logic.
*/
typedef struct {
u_int32_t bs_nexttbtt; /* next beacon in TU */
u_int32_t bs_nextdtim; /* next DTIM in TU */
- u_int16_t bs_intval; /* beacon interval/period */
+ u_int32_t bs_intval; /* beacon interval+flags */
+#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
+#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
+#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
u_int8_t bs_dtimperiod;
u_int8_t bs_cfpperiod; /* # of DTIMs between CFPs */
u_int16_t bs_cfpmaxduration; /* max CFP duration in TU */
@@ -337,7 +414,7 @@ struct ath_desc;
struct ath_hal {
u_int32_t ah_magic; /* consistency check magic number */
u_int32_t ah_abi; /* HAL ABI version */
-#define HAL_ABI_VERSION 0x03112500 /* YYMMDDnn */
+#define HAL_ABI_VERSION 0x04050400 /* YYMMDDnn */
u_int16_t ah_devid; /* PCI device ID */
u_int16_t ah_subvendorid; /* PCI subvendor ID */
HAL_SOFTC ah_sc; /* back pointer to driver/os state */
@@ -351,138 +428,160 @@ struct ath_hal {
u_int16_t ah_analog5GhzRev;/* 2GHz radio revision */
u_int16_t ah_analog2GhzRev;/* 5GHz radio revision */
- const HAL_RATE_TABLE *(*ah_getRateTable)(struct ath_hal *, u_int mode);
- void (*ah_detach)(struct ath_hal*);
+ const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
+ u_int mode);
+ void __ahdecl(*ah_detach)(struct ath_hal*);
/* Reset functions */
- HAL_BOOL (*ah_reset)(struct ath_hal *, HAL_OPMODE,
+ HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
HAL_CHANNEL *, HAL_BOOL bChannelChange,
HAL_STATUS *status);
- HAL_BOOL (*ah_setPCUConfig)(struct ath_hal *, HAL_OPMODE);
- HAL_BOOL (*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *);
+ HAL_BOOL __ahdecl (*ah_phyDisable)(struct ath_hal *);
+ void __ahdecl (*ah_setPCUConfig)(struct ath_hal *);
+ HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *);
/* Transmit functions */
- HAL_BOOL (*ah_updateTxTrigLevel)(struct ath_hal*,
+ HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
HAL_BOOL incTrigLevel);
- int (*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE type,
- HAL_BOOL irq);
- HAL_BOOL (*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
- HAL_BOOL (*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
- u_int32_t (*ah_getTxDP)(struct ath_hal*, u_int);
- HAL_BOOL (*ah_setTxDP)(struct ath_hal*, u_int, u_int32_t txdp);
- HAL_BOOL (*ah_startTxDma)(struct ath_hal*, u_int);
- HAL_BOOL (*ah_stopTxDma)(struct ath_hal*, u_int);
- HAL_BOOL (*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
+ int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
+ const HAL_TXQ_INFO *qInfo);
+ HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q,
+ const HAL_TXQ_INFO *qInfo);
+ HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
+ HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
+ u_int32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
+ HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, u_int32_t txdp);
+ HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
+ HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
+ HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
u_int pktLen, u_int hdrLen,
HAL_PKT_TYPE type, u_int txPower,
u_int txRate0, u_int txTries0,
u_int keyIx, u_int antMode, u_int flags,
u_int rtsctsRate, u_int rtsctsDuration);
- HAL_BOOL (*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc *,
- HAL_BOOL shortPreamble,
+ HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc *,
u_int txRate1, u_int txTries1,
u_int txRate2, u_int txTries2,
u_int txRate3, u_int txTries3);
- HAL_BOOL (*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
+ HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
u_int segLen, HAL_BOOL firstSeg,
HAL_BOOL lastSeg);
- HAL_STATUS (*ah_procTxDesc)(struct ath_hal *, struct ath_desc *);
- HAL_BOOL (*ah_hasVEOL)(struct ath_hal *);
+ HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_desc *);
+ HAL_BOOL __ahdecl(*ah_hasVEOL)(struct ath_hal *);
+ /* NB: experimental, may go away */
+ HAL_BOOL __ahdecl(*ah_updateTxDesc)(struct ath_hal *, struct ath_desc *,
+ u_int txRate0, u_int txTries0,
+ u_int txRate1, u_int txTries1,
+ u_int txRate2, u_int txTries2,
+ u_int txRate3, u_int txTries3);
/* Receive Functions */
- u_int32_t (*ah_getRxDP)(struct ath_hal*);
- void (*ah_setRxDP)(struct ath_hal*, u_int32_t rxdp);
- void (*ah_enableReceive)(struct ath_hal*);
- HAL_BOOL (*ah_stopDmaReceive)(struct ath_hal*);
- void (*ah_startPcuReceive)(struct ath_hal*);
- void (*ah_stopPcuReceive)(struct ath_hal*);
- void (*ah_setMulticastFilter)(struct ath_hal*,
+ u_int32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
+ void __ahdecl(*ah_setRxDP)(struct ath_hal*, u_int32_t rxdp);
+ void __ahdecl(*ah_enableReceive)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
+ void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
+ void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
+ void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
u_int32_t filter0, u_int32_t filter1);
- HAL_BOOL (*ah_setMulticastFilterIndex)(struct ath_hal*,
+ HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
u_int32_t index);
- HAL_BOOL (*ah_clrMulticastFilterIndex)(struct ath_hal*,
+ HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
u_int32_t index);
- u_int32_t (*ah_getRxFilter)(struct ath_hal*);
- void (*ah_setRxFilter)(struct ath_hal*, u_int32_t);
- HAL_BOOL (*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
+ u_int32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
+ void __ahdecl(*ah_setRxFilter)(struct ath_hal*, u_int32_t);
+ HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
u_int32_t size, u_int flags);
- HAL_STATUS (*ah_procRxDesc)(struct ath_hal *, struct ath_desc *,
+ HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *,
u_int32_t phyAddr, struct ath_desc *next);
- void (*ah_rxMonitor)(struct ath_hal *);
+ void __ahdecl(*ah_rxMonitor)(struct ath_hal *);
/* Misc Functions */
- void (*ah_dumpState)(struct ath_hal *);
- HAL_BOOL (*ah_getDiagState)(struct ath_hal *,
- int, void **, u_int *);
- void (*ah_getMacAddress)(struct ath_hal *, u_int8_t *);
- HAL_BOOL (*ah_setMacAddress)(struct ath_hal *, const u_int8_t *);
- HAL_BOOL (*ah_setRegulatoryDomain)(struct ath_hal*,
+ HAL_STATUS __ahdecl (*ah_getCapability)(struct ath_hal *,
+ HAL_CAPABILITY_TYPE, u_int32_t capability,
+ u_int32_t *result);
+ HAL_BOOL __ahdecl (*ah_setCapability)(struct ath_hal *,
+ HAL_CAPABILITY_TYPE, u_int32_t capability,
+ u_int32_t setting, HAL_STATUS *);
+ HAL_BOOL __ahdecl (*ah_getDiagState)(struct ath_hal *, int request,
+ const void *args, u_int32_t argsize,
+ void **result, u_int32_t *resultsize);
+ void __ahdecl(*ah_getMacAddress)(struct ath_hal *, u_int8_t *);
+ HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const u_int8_t*);
+ HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
u_int16_t, HAL_STATUS *);
- void (*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
- void (*ah_writeAssocid)(struct ath_hal*,
+ void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
+ void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
const u_int8_t *bssid, u_int16_t assocId,
u_int16_t timOffset);
- u_int32_t (*ah_gpioGet)(struct ath_hal*, u_int32_t gpio);
- void (*ah_gpioSetIntr)(struct ath_hal*, u_int, u_int32_t);
- u_int32_t (*ah_getTsf32)(struct ath_hal*);
- u_int64_t (*ah_getTsf64)(struct ath_hal*);
- void (*ah_resetTsf)(struct ath_hal*);
- u_int16_t (*ah_getRegDomain)(struct ath_hal*);
- HAL_BOOL (*ah_detectCardPresent)(struct ath_hal*);
- void (*ah_updateMibCounters)(struct ath_hal*, HAL_MIB_STATS*);
- HAL_BOOL (*ah_isHwCipherSupported)(struct ath_hal*, HAL_CIPHER);
- HAL_RFGAIN (*ah_getRfGain)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, u_int32_t gpio);
+ HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, u_int32_t gpio);
+ u_int32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, u_int32_t gpio);
+ HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,
+ u_int32_t gpio, u_int32_t val);
+ void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, u_int32_t);
+ u_int32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
+ u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
+ void __ahdecl(*ah_resetTsf)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
+ void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, HAL_MIB_STATS*);
+ HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
#if 0
- u_int32_t (*ah_getCurRssi)(struct ath_hal*);
- u_int32_t (*ah_getDefAntenna)(struct ath_hal*);
- void (*ah_setDefAntenna)(struct ath_hal*, u_int32_t antenna);
+ u_int32_t __ahdecl(*ah_getCurRssi)(struct ath_hal*);
+ u_int32_t __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
+ void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int32_t ant);
#endif
- HAL_BOOL (*ah_setSlotTime)(struct ath_hal*, u_int);
+ HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
+ u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
+ u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
+ u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
/* Key Cache Functions */
- u_int32_t (*ah_getKeyCacheSize)(struct ath_hal*);
- HAL_BOOL (*ah_resetKeyCacheEntry)(struct ath_hal*, u_int16_t);
- HAL_BOOL (*ah_isKeyCacheEntryValid)(struct ath_hal *, u_int16_t);
- HAL_BOOL (*ah_setKeyCacheEntry)(struct ath_hal*,
+ u_int32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, u_int16_t);
+ HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,u_int16_t);
+ HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
u_int16_t, const HAL_KEYVAL *,
const u_int8_t *, int);
- HAL_BOOL (*ah_setKeyCacheEntryMac)(struct ath_hal*,
+ HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
u_int16_t, const u_int8_t *);
/* Power Management Functions */
- HAL_BOOL (*ah_setPowerMode)(struct ath_hal*,
+ HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*,
HAL_POWER_MODE mode, int setChip,
u_int16_t sleepDuration);
- HAL_POWER_MODE (*ah_getPowerMode)(struct ath_hal*);
- HAL_BOOL (*ah_queryPSPollSupport)(struct ath_hal*);
- HAL_BOOL (*ah_initPSPoll)(struct ath_hal*);
- HAL_BOOL (*ah_enablePSPoll)(struct ath_hal *,
+ HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_queryPSPollSupport)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_initPSPoll)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_enablePSPoll)(struct ath_hal *,
u_int8_t *, u_int16_t);
- HAL_BOOL (*ah_disablePSPoll)(struct ath_hal *);
+ HAL_BOOL __ahdecl(*ah_disablePSPoll)(struct ath_hal *);
/* Beacon Management Functions */
- void (*ah_beaconInit)(struct ath_hal *, HAL_OPMODE,
- u_int32_t, u_int32_t);
- void (*ah_setStationBeaconTimers)(struct ath_hal*,
+ void __ahdecl(*ah_beaconInit)(struct ath_hal *,
+ u_int32_t nexttbtt, u_int32_t intval);
+ void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
const HAL_BEACON_STATE *, u_int32_t tsf,
u_int32_t dtimCount, u_int32_t cfpCcount);
- void (*ah_resetStationBeaconTimers)(struct ath_hal*);
- HAL_BOOL (*ah_waitForBeaconDone)(struct ath_hal *,
+ void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_waitForBeaconDone)(struct ath_hal *,
HAL_BUS_ADDR);
/* Interrupt functions */
- HAL_BOOL (*ah_isInterruptPending)(struct ath_hal*);
- HAL_BOOL (*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT *);
- HAL_INT (*ah_getInterrupts)(struct ath_hal*);
- HAL_INT (*ah_setInterrupts)(struct ath_hal*, HAL_INT);
+ HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
+ HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT *);
+ HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
+ HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
};
/*
* Check the PCI vendor ID and device ID against Atheros' values
* and return a printable description for any Atheros hardware.
* AH_NULL is returned if the ID's do not describe Atheros hardware.
*/
-extern const char *ath_hal_probe(u_int16_t vendorid, u_int16_t devid);
+extern const char *__ahdecl ath_hal_probe(u_int16_t vendorid, u_int16_t devid);
/*
* Attach the HAL for use with the specified device. The device is
@@ -497,7 +596,7 @@ extern const char *ath_hal_probe(u_int16_t vendorid, u_int16_t devid);
* null (AH_NULL) reference will be returned and a status code will
* be returned if the status parameter is non-zero.
*/
-extern struct ath_hal *ath_hal_attach(u_int16_t devid, HAL_SOFTC,
+extern struct ath_hal * __ahdecl ath_hal_attach(u_int16_t devid, HAL_SOFTC,
HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status);
/*
@@ -511,34 +610,35 @@ extern struct ath_hal *ath_hal_attach(u_int16_t devid, HAL_SOFTC,
* number of channels returned. If a problem occurred or there were
* no channels that met the criteria then AH_FALSE is returned.
*/
-extern HAL_BOOL ath_hal_init_channels(struct ath_hal *,
+extern HAL_BOOL __ahdecl ath_hal_init_channels(struct ath_hal *,
HAL_CHANNEL *chans, u_int maxchans, u_int *nchans,
- HAL_CTRY_CODE cc, u_int16_t modeSelect, int enableOutdoor);
+ HAL_CTRY_CODE cc, u_int16_t modeSelect,
+ HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels);
/*
* Return bit mask of wireless modes supported by the hardware.
*/
-extern u_int ath_hal_getwirelessmodes(struct ath_hal *ah, HAL_CTRY_CODE cc);
+extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE);
/*
* Return rate table for specified mode (11a, 11b, 11g, etc).
*/
-extern const HAL_RATE_TABLE *ath_hal_getratetable(struct ath_hal *,
+extern const HAL_RATE_TABLE * __ahdecl ath_hal_getratetable(struct ath_hal *,
u_int mode);
/*
* Calculate the transmit duration of a frame.
*/
-extern u_int16_t ath_hal_computetxtime(struct ath_hal *,
+extern u_int16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
const HAL_RATE_TABLE *rates, u_int32_t frameLen,
u_int16_t rateix, HAL_BOOL shortPreamble);
/*
* Convert between IEEE channel number and channel frequency
* using the specified channel flags; e.g. CHANNEL_2GHZ.
*/
-extern u_int ath_hal_mhz2ieee(u_int mhz, u_int flags);
-extern u_int ath_hal_ieee2mhz(u_int ieee, u_int flags);
+extern u_int __ahdecl ath_hal_mhz2ieee(u_int mhz, u_int flags);
+extern u_int __ahdecl ath_hal_ieee2mhz(u_int ieee, u_int flags);
/*
* Return a version string for the HAL release.
View
14 contrib/sys/dev/ic/athhal_desc.h
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
+ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros
* Communications, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms are permitted
@@ -33,7 +33,7 @@
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGES.
*
- * $Id: ah_desc.h,v 1.11 2003/06/25 04:50:22 sam Exp $
+ * $Id: ah_desc.h,v 1.2 2004/05/15 22:26:25 samleffler Exp $
*/
#ifndef _DEV_ATH_DESC_H
@@ -53,6 +53,7 @@ struct ath_tx_status {
u_int16_t ts_tstamp; /* h/w assigned timestamp */
u_int8_t ts_status; /* frame status, 0 => xmit ok */
u_int8_t ts_rate; /* h/w transmit rate index */
+#define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */
int8_t ts_rssi; /* tx ack RSSI */
u_int8_t ts_shortretry; /* # short retries */
u_int8_t ts_longretry; /* # long retries */
@@ -72,10 +73,17 @@ struct ath_tx_status {
*
* If rx_status is zero, then the frame was received ok;
* otherwise the error information is indicated and rs_phyerr
- * contains a phy error code if HAL_RXERR_PHY is set.
+ * contains a phy error code if HAL_RXERR_PHY is set. In general
+ * the frame contents is undefined when an error occurred thought
+ * for some errors (e.g. a decryption error), it may be meaningful.
*
* Note that the receive timestamp is expanded using the TSF to
* a full 16 bits (regardless of what the h/w provides directly).
+ *
+ * rx_rssi is in units of dbm above the noise floor. This value
+ * is measured during the preamble and PLCP; i.e. with the initial
+ * 4us of detection. The noise floor is typically a consistent
+ * -96dBm absolute power in a 20MHz channel.
*/
struct ath_rx_status {
u_int16_t rs_datalen; /* rx frame length */
View
10 contrib/sys/dev/ic/athhal_devid.h
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
+ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros
* Communications, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms are permitted
@@ -33,7 +33,7 @@
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGES.
*
- * $Id: ah_devid.h,v 1.7 2003/10/22 21:17:40 sam Exp $
+ * $Id: ah_devid.h,v 1.4 2004/06/09 16:33:48 samleffler Exp $
*/
#ifndef _DEV_ATH_DEVID_H_
@@ -45,7 +45,8 @@
* of 0x168c, but some vendors, in their infinite wisdom
* do not follow this so we must handle them specially.
*/
-#define ATHEROS_3COM_VENDOR_ID 0xa727 /* 3Com PCI vendor ID */
+#define ATHEROS_3COM_VENDOR_ID 0xa727 /* 3Com 3CRPAG175 vendor ID */
+#define ATHEROS_3COM2_VENDOR_ID 0x10b7 /* 3Com 3CRDAG675 vendor ID */
/* AR5210 (for reference) */
#define AR5210_DEFAULT 0x1107 /* No eeprom HW default */
@@ -64,6 +65,9 @@
#define AR5212_DEVID 0x0013 /* Final ar5212 devid */
#define AR5212_FPGA 0xf013 /* Emulation board */
#define AR5212_DEVID_IBM 0x1014 /* IBM minipci ID */
+#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
+#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
+#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
#define AR_SUBVENDOR_ID_NOG 0x0e11 /* No 11G subvendor ID */
#endif /* _DEV_ATH_DEVID_H */
View
504 contrib/sys/dev/ic/athhal_osdep.c
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
+ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros
* Communications, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms are permitted
@@ -33,85 +33,80 @@
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGES.
*
- * $Id: ah_osdep.c,v 1.28 2003/11/01 01:43:21 sam Exp $
+ * $Id: ah_osdep.c,v 1.3 2004/06/09 16:33:48 samleffler Exp $
*/
#include "opt_ah.h"
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/sysctl.h>
-#include <sys/bus.h>
-#include <sys/malloc.h>
-#include <sys/proc.h>
+#ifndef EXPORT_SYMTAB
+#define EXPORT_SYMTAB
+#endif
-#include <machine/stdarg.h>
+#include <linux/config.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/init.h>
-#include <net/ethernet.h> /* XXX for ether_sprintf */
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
-#include <contrib/dev/ath/ah.h>
+#include <linux/sysctl.h>
+#include <linux/proc_fs.h>
-extern void ath_hal_printf(struct ath_hal *, const char*, ...)
- __printflike(2,3);
-extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
- __printflike(2, 0);
-extern const char* ath_hal_ether_sprintf(const u_int8_t *mac);
-extern void *ath_hal_malloc(size_t);
-extern void ath_hal_free(void *);
-#ifdef AH_ASSERT
-extern void ath_hal_assert_failed(const char* filename,
- int lineno, const char* msg);
-#endif
-#ifdef AH_DEBUG
-extern void HALDEBUG(struct ath_hal *ah, const char* fmt, ...);
-extern void HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...);
-#endif /* AH_DEBUG */
+#include <asm/io.h>
-/* NB: put this here instead of the driver to avoid circular references */
-SYSCTL_NODE(_hw, OID_AUTO, ath, CTLFLAG_RD, 0, "Atheros driver parameters");
-SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, "Atheros HAL parameters");
+#include "ah.h"
-#ifdef AH_DEBUG
-static int ath_hal_debug = 0; /* XXX */
-SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug,
- 0, "Atheros HAL debugging printfs");
-#endif /* AH_DEBUG */
+#ifndef __MOD_INC_USE_COUNT
+#define __MOD_INC_USE_COUNT(_m) \
+ if (!try_module_get(_m)) { \
+ printk(KERN_WARNING "try_module_get failed\n"); \
+ return NULL; \
+ }
+#define __MOD_DEC_USE_COUNT(_m) module_put(_m)
+#endif
-SYSCTL_STRING(_hw_ath_hal, OID_AUTO, version, CTLFLAG_RD, ath_hal_version, 0,
- "Atheros HAL version");
+#ifdef AH_DEBUG
+static int ath_hal_debug = 0;
+#endif
int ath_hal_dma_beacon_response_time = 2; /* in TU's */
-SYSCTL_INT(_hw_ath_hal, OID_AUTO, dma_brt, CTLFLAG_RW,
- &ath_hal_dma_beacon_response_time, 0,
- "Atheros HAL DMA beacon response time");
int ath_hal_sw_beacon_response_time = 10; /* in TU's */
-SYSCTL_INT(_hw_ath_hal, OID_AUTO, sw_brt, CTLFLAG_RW,
- &ath_hal_sw_beacon_response_time, 0,
- "Atheros HAL software beacon response time");
int ath_hal_additional_swba_backoff = 0; /* in TU's */
-SYSCTL_INT(_hw_ath_hal, OID_AUTO, swba_backoff, CTLFLAG_RW,
- &ath_hal_additional_swba_backoff, 0,
- "Atheros HAL additional SWBA backoff time");
-void*
-ath_hal_malloc(size_t size)
+struct ath_hal *
+_ath_hal_attach(u_int16_t devid, HAL_SOFTC sc,
+ HAL_BUS_TAG t, HAL_BUS_HANDLE h, void* s)
{
- return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
+ HAL_STATUS status;
+ struct ath_hal *ah = ath_hal_attach(devid, sc, t, h, &status);
+
+ *(HAL_STATUS *)s = status;
+ if (ah)
+ __MOD_INC_USE_COUNT(THIS_MODULE);
+ return ah;
}
void
-ath_hal_free(void* p)
+ath_hal_detach(struct ath_hal *ah)
{
- return free(p, M_DEVBUF);
+ (*ah->ah_detach)(ah);
+ __MOD_DEC_USE_COUNT(THIS_MODULE);
}
-void
+/*
+ * Print/log message support.
+ */
+
+void __ahdecl
ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)
{
- vprintf(fmt, ap);
+ char buf[1024]; /* XXX */
+ vsnprintf(buf, sizeof(buf), fmt, ap);
+ printk("%s", buf);
}
-void
+void __ahdecl
ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)
{
va_list ap;
@@ -120,14 +115,70 @@ ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)
va_end(ap);
}
-const char*
+/*
+ * Format an Ethernet MAC for printing.
+ */
+const char* __ahdecl
ath_hal_ether_sprintf(const u_int8_t *mac)
{
- return ether_sprintf(mac);
+ static char etherbuf[18];
+ snprintf(etherbuf, sizeof(etherbuf), "%02x:%02x:%02x:%02x:%02x:%02x",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ return etherbuf;
+}
+
+#ifdef AH_ASSERT
+void __ahdecl
+ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
+{
+ printk("Atheros HAL assertion failure: %s: line %u: %s\n",
+ filename, lineno, msg);
+ panic("ath_hal_assert");
}
+#endif /* AH_ASSERT */
+/*
+ * Memory-mapped device register read/write. These are here
+ * as routines when debugging support is enabled and/or when
+ * explicitly configured to use function calls. The latter is
+ * for architectures that might need to do something before
+ * referencing memory (e.g. remap an i/o window).
+ *
+ * NB: see the comments in ah_osdep.h about byte-swapping register
+ * reads and writes to understand what's going on below.
+ */
+#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
+void __ahdecl
+ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val)
+{
#ifdef AH_DEBUG
-void
+ if (ath_hal_debug > 1)
+ ath_hal_printf(ah, "WRITE 0x%x <= 0x%x\n", reg, val);
+#endif
+ if (reg >= 0x4000 && reg < 0x5000)
+ *((volatile u_int32_t *)(ah->ah_sh + reg)) = __bswap32(val);
+ else
+ *((volatile u_int32_t *)(ah->ah_sh + reg)) = val;
+}
+
+u_int32_t __ahdecl
+ath_hal_reg_read(struct ath_hal *ah, u_int reg)
+{
+ u_int32_t val;
+
+ val = *((volatile u_int32_t *)(ah->ah_sh + reg));
+ if (reg >= 0x4000 && reg < 0x5000)
+ val = __bswap32(val);
+#ifdef AH_DEBUG
+ if (ath_hal_debug > 1)
+ ath_hal_printf(ah, "READ 0x%x => 0x%x\n", reg, val);
+#endif
+ return val;
+}
+#endif /* AH_DEBUG || AH_REGOPS_FUNC */
+
+#ifdef AH_DEBUG
+void __ahdecl
HALDEBUG(struct ath_hal *ah, const char* fmt, ...)
{
if (ath_hal_debug) {
@@ -138,7 +189,8 @@ HALDEBUG(struct ath_hal *ah, const char* fmt, ...)
}
}
-void
+
+void __ahdecl
HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...)
{
if (ath_hal_debug >= level) {
@@ -150,245 +202,169 @@ HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...)
}
#endif /* AH_DEBUG */
-#ifdef AH_DEBUG_ALQ
/*
- * ALQ register tracing support.
- *
- * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
- * writes to the file /tmp/ath_hal.log. The file format is a simple
- * fixed-size array of records. When done logging set hw.ath.hal.alq=0
- * and then decode the file with the arcode program (that is part of the
- * HAL). If you start+stop tracing the data will be appended to an
- * existing file.
- *
- * NB: doesn't handle multiple devices properly; only one DEVICE record
- * is emitted and the different devices are not identified.
+ * Delay n microseconds.
*/
-#include <sys/alq.h>
-#include <sys/pcpu.h>
-#include <contrib/dev/ath/ah_decode.h>
-
-static struct alq *ath_hal_alq;
-static int ath_hal_alq_emitdev; /* need to emit DEVICE record */
-static u_int ath_hal_alq_lost; /* count of lost records */
-static const char *ath_hal_logfile = "/tmp/ath_hal.log";
-static u_int ath_hal_alq_qsize = 64*1024;
-
-static int
-ath_hal_setlogging(int enable)
+void __ahdecl
+ath_hal_delay(int n)
{
- int error;
-
- if (enable) {
- error = suser(curthread);
- if (error == 0) {
- error = alq_open(&ath_hal_alq, ath_hal_logfile,
- curthread->td_ucred,
- sizeof (struct athregrec), ath_hal_alq_qsize);
- ath_hal_alq_lost = 0;
- ath_hal_alq_emitdev = 1;
- printf("ath_hal: logging to %s enabled\n",
- ath_hal_logfile);
- }
- } else {
- if (ath_hal_alq)
- alq_close(ath_hal_alq);
- ath_hal_alq = NULL;
- printf("ath_hal: logging disabled\n");
- error = 0;
- }
- return (error);
+ udelay(n);
}
-static int
-sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS)
+u_int32_t __ahdecl
+ath_hal_getuptime(struct ath_hal *ah)
{
- int error, enable;
-
- enable = (ath_hal_alq != NULL);
- error = sysctl_handle_int(oidp, &enable, 0, req);
- if (error || !req->newptr)
- return (error);
- else
- return (ath_hal_setlogging(enable));
-}
-SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW,
- 0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging");
-SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW,
- &ath_hal_alq_qsize, 0, "In-memory log size (#records)");
-SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW,
- &ath_hal_alq_lost, 0, "Register operations not logged");
-
-static struct ale *
-ath_hal_alq_get(struct ath_hal *ah)
-{
- struct ale *ale;
-
- if (ath_hal_alq_emitdev) {
- ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
- if (ale) {
- struct athregrec *r =
- (struct athregrec *) ale->ae_data;
- r->op = OP_DEVICE;
- r->reg = 0;
- r->val = ah->ah_devid;
- alq_post(ath_hal_alq, ale);
- ath_hal_alq_emitdev = 0;
- } else
- ath_hal_alq_lost++;
- }
- ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
- if (!ale)
- ath_hal_alq_lost++;
- return ale;
+ return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
}
-void
-ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
-{
- if (ath_hal_alq) {
- struct ale *ale = ath_hal_alq_get(ah);
- if (ale) {
- struct athregrec *r = (struct athregrec *) ale->ae_data;
- r->op = OP_WRITE;
- r->reg = reg;
- r->val = val;
- alq_post(ath_hal_alq, ale);
- }
- }
-#if _BYTE_ORDER == _BIG_ENDIAN
- if (reg >= 0x4000 && reg < 0x5000)
- bus_space_write_4(ah->ah_st, ah->ah_sh, reg, htole32(val));
- else
-#endif
- bus_space_write_4(ah->ah_st, ah->ah_sh, reg, val);
-}
+/*
+ * Allocate/free memory.
+ */
-u_int32_t
-ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
+void * __ahdecl
+ath_hal_malloc(size_t size)
{
- u_int32_t val;
-
- val = bus_space_read_4(ah->ah_st, ah->ah_sh, reg);
-#if _BYTE_ORDER == _BIG_ENDIAN
- if (reg >= 0x4000 && reg < 0x5000)
- val = le32toh(val);
-#endif
- if (ath_hal_alq) {
- struct ale *ale = ath_hal_alq_get(ah);
- if (ale) {
- struct athregrec *r = (struct athregrec *) ale->ae_data;
- r->op = OP_READ;
- r->reg = reg;
- r->val = val;
- alq_post(ath_hal_alq, ale);
- }
- }
- return val;
+ void *p;
+ p = kmalloc(size, GFP_KERNEL);
+ if (p)
+ OS_MEMZERO(p, size);
+ return p;
+
}
-void
-OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
+void __ahdecl
+ath_hal_free(void* p)
{
- if (ath_hal_alq) {
- struct ale *ale = ath_hal_alq_get(ah);
- if (ale) {
- struct athregrec *r = (struct athregrec *) ale->ae_data;
- r->op = OP_MARK;
- r->reg = id;
- r->val = v;
- alq_post(ath_hal_alq, ale);
- }
- }
+ kfree(p);
}
-#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
-/*
- * Memory-mapped device register read/write. These are here
- * as routines when debugging support is enabled and/or when
- * explicitly configured to use function calls. The latter is
- * for architectures that might need to do something before
- * referencing memory (e.g. remap an i/o window).
- *
- * NB: see the comments in ah_osdep.h about byte-swapping register
- * reads and writes to understand what's going on below.
- */
-void
-ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
+void * __ahdecl
+ath_hal_memcpy(void *dst, const void *src, size_t n)
{
-#if _BYTE_ORDER == _BIG_ENDIAN
- if (reg >= 0x4000 && reg < 0x5000)
- bus_space_write_4(ah->ah_st, ah->ah_sh, reg, htole32(val));
- else
-#endif
- bus_space_write_4(ah->ah_st, ah->ah_sh, reg, val);
+ return memcpy(dst, src, n);
}
-u_int32_t
-ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
-{
- u_int32_t val;
+#ifdef CONFIG_SYSCTL
+enum {
+ DEV_ATH = 9, /* XXX must match driver */
+};
+
+#define CTL_AUTO -2 /* cannot be CTL_ANY or CTL_NONE */
- val = bus_space_read_4(ah->ah_st, ah->ah_sh, reg);
-#if _BYTE_ORDER == _BIG_ENDIAN
- if (reg >= 0x4000 && reg < 0x5000)
- val = le32toh(val);
+static ctl_table ath_hal_sysctls[] = {
+#ifdef AH_DEBUG
+ { .ctl_name = CTL_AUTO,
+ .procname = "debug",
+ .mode = 0644,
+ .data = &ath_hal_debug,
+ .maxlen = sizeof(ath_hal_debug),
+ .proc_handler = proc_dointvec
+ },
#endif
- return val;
-}
-#endif /* AH_DEBUG || AH_REGOPS_FUNC */
+ { .ctl_name = CTL_AUTO,
+ .procname = "dma_beacon_response_time",
+ .data = &ath_hal_dma_beacon_response_time,
+ .maxlen = sizeof(ath_hal_dma_beacon_response_time),
+ .mode = 0644,
+ .proc_handler = proc_dointvec
+ },
+ { .ctl_name = CTL_AUTO,
+ .procname = "sw_beacon_response_time",
+ .mode = 0644,
+ .data = &ath_hal_sw_beacon_response_time,
+ .maxlen = sizeof(ath_hal_sw_beacon_response_time),
+ .proc_handler = proc_dointvec
+ },
+ { .ctl_name = CTL_AUTO,
+ .procname = "swba_backoff",
+ .mode = 0644,
+ .data = &ath_hal_additional_swba_backoff,
+ .maxlen = sizeof(ath_hal_additional_swba_backoff),
+ .proc_handler = proc_dointvec
+ },
+ { 0 }
+};
+static ctl_table ath_hal_table[] = {
+ { .ctl_name = CTL_AUTO,
+ .procname = "hal",
+ .mode = 0555,
+ .child = ath_hal_sysctls
+ }, { 0 }
+};
+static ctl_table ath_ath_table[] = {
+ { .ctl_name = DEV_ATH,
+ .procname = "ath",
+ .mode = 0555,
+ .child = ath_hal_table
+ }, { 0 }
+};
+static ctl_table ath_root_table[] = {
+ { .ctl_name = CTL_DEV,
+ .procname = "dev",
+ .mode = 0555,
+ .child = ath_ath_table
+ }, { 0 }
+};
+static struct ctl_table_header *ath_hal_sysctl_header;
-#ifdef AH_ASSERT
void
-ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
+ath_hal_sysctl_register(void)
{
- printf("Atheros HAL assertion failure: %s: line %u: %s\n",
- filename, lineno, msg);
- panic("ath_hal_assert");
-}
-#endif /* AH_ASSERT */
+ static int initialized = 0;
-/*
- * Delay n microseconds.
- */
-void
-ath_hal_delay(int n)
-{
- DELAY(n);
+ if (!initialized) {
+ ath_hal_sysctl_header =
+ register_sysctl_table(ath_root_table, 1);
+ initialized = 1;
+ }
}
-u_int32_t
-ath_hal_getuptime(struct ath_hal *ah)
+void
+ath_hal_sysctl_unregister(void)
{
- struct bintime bt;
- getbinuptime(&bt);
- return (bt.sec * 1000) +
- (((uint64_t)1000 * (uint32_t)(bt.frac >> 32)) >> 32);
+ if (ath_hal_sysctl_header)
+ unregister_sysctl_table(ath_hal_sysctl_header);
}
+#endif /* CONFIG_SYSCTL */
/*
* Module glue.
*/
+static char *dev_info = "ath_hal";
-static int
-ath_hal_modevent(module_t mod, int type, void *unused)
+MODULE_AUTHOR("Errno Consulting, Sam Leffler");
+MODULE_DESCRIPTION("Atheros Hardware Access Layer (HAL)");
+MODULE_SUPPORTED_DEVICE("Atheros WLAN devices");
+#ifdef MODULE_LICENSE
+MODULE_LICENSE("Proprietary");
+#endif
+
+EXPORT_SYMBOL(ath_hal_probe);
+EXPORT_SYMBOL(_ath_hal_attach);
+EXPORT_SYMBOL(ath_hal_detach);
+EXPORT_SYMBOL(ath_hal_init_channels);
+EXPORT_SYMBOL(ath_hal_getwirelessmodes);
+EXPORT_SYMBOL(ath_hal_computetxtime);
+EXPORT_SYMBOL(ath_hal_mhz2ieee);
+EXPORT_SYMBOL(ath_hal_ieee2mhz);
+
+static int __init
+init_ath_hal(void)
{
- switch (type) {
- case MOD_LOAD:
- if (bootverbose)
- printf("ath_hal: <Atheros Hardware Access Layer>"
- "version %s\n", ath_hal_version);
- return 0;
- case MOD_UNLOAD:
- return 0;
- }
- return EINVAL;
+ printk(KERN_INFO "%s: %s\n", dev_info, ath_hal_version);
+#ifdef CONFIG_SYSCTL
+ ath_hal_sysctl_register();
+#endif
+ return (0);
}
+module_init(init_ath_hal);
-static moduledata_t ath_hal_mod = {
- "ath_hal",
- ath_hal_modevent,
- 0
-};
-DECLARE_MODULE(ath_hal, ath_hal_mod, SI_SUB_DRIVERS, SI_ORDER_ANY);
-MODULE_VERSION(ath_hal, 1);
+static void __exit
+exit_ath_hal(void)
+{
+#ifdef CONFIG_SYSCTL
+ ath_hal_sysctl_unregister();
+#endif
+ printk(KERN_INFO "%s: driver unloaded\n", dev_info);
+}
+module_exit(exit_ath_hal);
View
175 contrib/sys/dev/ic/athhal_osdep.h
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting, Atheros
+ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros
* Communications, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms are permitted
@@ -33,56 +33,111 @@
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGES.
*
- * $Id: ah_osdep.h,v 1.10 2003/11/01 01:21:31 sam Exp $
+ * $Id: ah_osdep.h,v 1.1.1.7 2004/06/09 16:25:50 samleffler Exp $
*/
#ifndef _ATH_AH_OSDEP_H_
#define _ATH_AH_OSDEP_H_
/*
* Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
*/
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/endian.h>
-#include <machine/bus.h>
+/*
+ * Starting with 2.6.4 the kernel supports a configuration option
+ * to pass parameters in registers. If this is enabled we must
+ * mark all function interfaces in+out of the HAL to pass parameters
+ * on the stack as this is the convention used internally (for
+ * maximum portability).
+ */
+#ifdef CONFIG_REGPARM
+#define __ahdecl __attribute__((regparm(0)))
+#else
+#define __ahdecl
+#endif
+
+/*
+ * When building the HAL proper we use no GPL-contaminated include
+ * files and must define these types ourself. Beware of these being
+ * mismatched against the contents of <linux/types.h>
+ */
+#ifndef _LINUX_TYPES_H
+/* NB: arm defaults to unsigned so be explicit */
+typedef signed char int8_t;
+typedef short int16_t;
+typedef int int32_t;
+typedef long long int64_t;
+
+typedef unsigned char u_int8_t;
+typedef unsigned short u_int16_t;
+typedef unsigned int u_int32_t;
+typedef unsigned long long u_int64_t;
+
+typedef unsigned int size_t;
+typedef unsigned int u_int;
+typedef void *va_list;
+#endif
+
+/*
+ * Linux/BSD gcc compatibility shims.
+ */
+#define __printflike(_a,_b) \
+ __attribute__ ((__format__ (__printf__, _a, _b)))
+#define __va_list va_list
+#define OS_INLINE __inline
typedef void* HAL_SOFTC;
-typedef bus_space_tag_t HAL_BUS_TAG;
-typedef bus_space_handle_t HAL_BUS_HANDLE;
-typedef bus_addr_t HAL_BUS_ADDR;
+typedef int HAL_BUS_TAG;
+typedef void* HAL_BUS_HANDLE;
+typedef u_int32_t HAL_BUS_ADDR; /* XXX architecture dependent */
/*
* Delay n microseconds.
*/
-extern void ath_hal_delay(int);
+extern void __ahdecl ath_hal_delay(int);
#define OS_DELAY(_n) ath_hal_delay(_n)
-#define OS_INLINE __inline
-#define OS_MEMZERO(_a, _size) bzero((_a), (_size))
-#define OS_MEMCPY(_dst, _src, _size) bcopy((_src), (_dst), (_size))
-#define OS_MACEQU(_a, _b) \
- (bcmp((_a), (_b), IEEE80211_ADDR_LEN) == 0)
+#define OS_MEMZERO(_a, _n) __builtin_memset((_a), 0, (_n))
+#define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n)
+extern void * __ahdecl ath_hal_memcpy(void *, const void *, size_t);
+
+#define abs(_a) __builtin_abs(_a)
struct ath_hal;
-extern u_int32_t ath_hal_getuptime(struct ath_hal *);
+extern u_int32_t __ahdecl ath_hal_getuptime(struct ath_hal *);
#define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah)
/*
+ * Byte order/swapping support.
+ */
+#define AH_LITTLE_ENDIAN 1234
+#define AH_BIG_ENDIAN 4321
+
+#if AH_BYTE_ORDER == AH_BIG_ENDIAN
+/*
+ * This could be optimized but since we only use it for
+ * a few registers there's little reason to do so.
+ */
+static inline u_int32_t
+__bswap32(u_int32_t _x)
+{
+ return ((u_int32_t)(
+ (((const u_int8_t *)(&_x))[0] ) |
+ (((const u_int8_t *)(&_x))[1]<< 8) |
+ (((const u_int8_t *)(&_x))[2]<<16) |
+ (((const u_int8_t *)(&_x))[3]<<24))
+ );
+}
+#else
+#define __bswap32(_x) (_x)
+#endif
+
+/*
* Register read/write; we assume the registers will always
* be memory-mapped. Note that register accesses are done
* using target-specific functions when debugging is enabled
* (AH_DEBUG) or we are explicitly configured this way. The
* latter is used on some platforms where the full i/o space
* cannot be directly mapped.
- */
-#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
-#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
-#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
-
-extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
-extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
-#else
-/*
+ *
* The hardware registers are native little-endian byte order.
* Big-endian hosts are handled by enabling hardware byte-swap
* of register reads and writes at reset. But the PCI clock
@@ -91,35 +146,51 @@ extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
* Most of this code is collapsed at compile time because the
* register values are constants.
*/
-#define AH_LITTLE_ENDIAN 1234
-#define AH_BIG_ENDIAN 4321
+#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
+/* use functions to do register operations */
+#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
+#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
-#if _BYTE_ORDER == _BIG_ENDIAN
-#define OS_REG_WRITE(_ah, _reg, _val) do { \
- if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
- bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
- (_reg), htole32(_val)); \
- else \
- bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
- (_reg), (_val)); \
-} while (0)
-#define OS_REG_READ(_ah, _reg) \
- (((_reg) >= 0x4000 && (_reg) < 0x5000) ? \
- le32toh(bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, \
- (_reg))) : \
- bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
-#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
-#define OS_REG_WRITE(_ah, _reg, _val) \
- bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, (_reg), (_val))
-#define OS_REG_READ(_ah, _reg) \
- ((u_int32_t) bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
-#endif /* _BYTE_ORDER */
-#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
-
-#ifdef AH_DEBUG_ALQ
-extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
+extern void __ahdecl ath_hal_reg_write(struct ath_hal *ah,
+ u_int reg, u_int32_t val);
+extern u_int32_t __ahdecl ath_hal_reg_read(struct ath_hal *ah, u_int reg);
#else
+/* inline register operations */
+#if AH_BYTE_ORDER == AH_BIG_ENDIAN
+#define OS_REG_WRITE(_ah, _reg, _val) do { \
+ if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
+ *((volatile u_int32_t *)((_ah)->ah_sh + (_reg))) = \
+ __bswap32((_val)); \
+ else \
+ *((volatile u_int32_t *)((_ah)->ah_sh + (_reg))) = (_val); \
+} while (0)
+#define OS_REG_READ(_ah, _reg) \
+ (((_reg) >= 0x4000 && (_reg) < 0x5000) ? \
+ __bswap32(*((volatile u_int32_t *)((_ah)->ah_sh + (_reg)))) : \
+ *((volatile u_int32_t *)((_ah)->ah_sh + (_reg))))
+#else /* AH_LITTLE_ENDIAN */
+#define OS_REG_WRITE(_ah, _reg, _val) do { \
+ *((volatile u_int32_t *)((_ah)->ah_sh + (_reg))) = (_val); \
+} while (0)
+#define OS_REG_READ(_ah, _reg) \
+ *((volatile u_int32_t *)((_ah)->ah_sh + (_reg)))
+#endif /* AH_BYTE_ORDER */
+#endif /* AH_DEBUG || AH_REGFUNC */
#define OS_MARK(_ah, _id, _v)
-#endif
+
+/*
+ * Linux-specific attach/detach methods needed for module reference counting.
+ *
+ * XXX We can't use HAL_STATUS because the type isn't defined at this
+ * point (circular dependency); we wack the type and patch things
+ * up in the function.
+ *
+ * NB: These are intentionally not marked __ahdecl since they are
+ * compiled with the default calling convetion and are not called
+ * from within the HAL.
+ */
+extern struct ath_hal *_ath_hal_attach(u_int16_t devid, HAL_SOFTC,
+ HAL_BUS_TAG, HAL_BUS_HANDLE, void* status);
+extern void ath_hal_detach(struct ath_hal *);
#endif /* _ATH_AH_OSDEP_H_ */
View
6 contrib/sys/dev/ic/athhal_version.h
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
+ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -33,6 +33,6 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
- * $Id: version.h,v 1.27 2003/12/07 02:20:39 sam Exp $
+ * $Id: version.h,v 1.1.1.10 2004/07/13 19:13:39 samleffler Exp $
*/
-#define ATH_HAL_VERSION "0.9.6.3"
+#define ATH_HAL_VERSION "0.9.9.13"

0 comments on commit 4f01909

Please sign in to comment.
Something went wrong with that request. Please try again.