diff --git a/CircularZone/CircularZone.py b/CircularZone/CircularZone.py index 3741fa4..b7b9583 100644 --- a/CircularZone/CircularZone.py +++ b/CircularZone/CircularZone.py @@ -2,14 +2,17 @@ import pcbnew from .CircularZoneDlg import CircularZoneDlg import wx +import os class CircularZone(pcbnew.ActionPlugin): def defaults(self): - self.name = "Create a circular zone" - self.category = "Undefined" - self.description = "" + self.name = "Circular Zone\nKeepout Zone Generator" + self.category = "Modify PCB" + self.description = "Create a Circular Zone\nor a Circular Keepout Zone" + self.icon_file_name = os.path.join(os.path.dirname(__file__), "./round_keepout_area.png") + self.show_toolbar_button = True def build(self, center_x, center_y, radius, keepout, edge_count): sp = pcbnew.SHAPE_POLY_SET() diff --git a/CircularZone/round_keepout_area.png b/CircularZone/round_keepout_area.png new file mode 100644 index 0000000..03abbcf Binary files /dev/null and b/CircularZone/round_keepout_area.png differ diff --git a/CircularZone/round_keepout_area.svg b/CircularZone/round_keepout_area.svg new file mode 100644 index 0000000..30b4901 --- /dev/null +++ b/CircularZone/round_keepout_area.svg @@ -0,0 +1,216 @@ + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ViaStitching/FillArea.py b/ViaStitching/FillArea.py index d80f6b4..1c716b2 100644 --- a/ViaStitching/FillArea.py +++ b/ViaStitching/FillArea.py @@ -349,11 +349,12 @@ def Run(self): # timestmap again available #target_tracks = filter(lambda x: (x.GetNetname().upper() == self.netname), self.pcb.GetTracks()) target_tracks = filter(lambda x: (x.GetNetname() == self.netname), self.pcb.GetTracks()) - for via in target_tracks: - # pprint.pprint(via.GetTimeStamp()) - if via.Type() == PCB_VIA_T: - if via.GetTimeStamp() == 33: - self.pcb.RemoveNative(via) + target_tracks_cp = list(target_tracks) + l = len (target_tracks_cp) + for i in range(l): + if target_tracks_cp[i].Type() == PCB_VIA_T: + if target_tracks_cp[i].GetTimeStamp() == 33: + self.pcb.RemoveNative(target_tracks_cp[i]) self.RefillBoardAreas() return # no need to run the rest of logic diff --git a/ViaStitching/FillAreaAction.py b/ViaStitching/FillAreaAction.py index 1183b0d..c97b851 100644 --- a/ViaStitching/FillAreaAction.py +++ b/ViaStitching/FillAreaAction.py @@ -71,7 +71,7 @@ def Run(self): PopulateNets("GND", a) modal_result = a.ShowModal() if modal_result == wx.ID_OK: - wx.LogMessage('Via Stitching: Version 1.4') + wx.LogMessage('Via Stitching: Version 1.5') if 1: # try: fill = FillArea.FillArea() fill.SetStepMM(float(a.m_StepMM.GetValue().replace(',', '.')))