NORA ISAFIX: Ban SEP/REP in Emulation mode

Author: Jaroslav

fpga-nora/src/cpu_observer.v

@@ -14,6 +14,7 @@ module cpu_observer
     input           is_isync_i,     // opcode fetch?
     input [7:0]     cpu_dbo_i,      // DB output to the CPU
     input           cef_i,          // Emulation flag?
+    input           stopped_cpu_i,  // is the CPU stopped by ICD?
     // Bus signals
     input           release_wr_i,   // wr-phase
     input           release_cs_i,   // cs-phase
@@ -22,7 +23,8 @@ module cpu_observer
     // Control outputs
     output reg      map_pblrom_o,   // command to map the PBL ROM
     output reg      unmap_pblrom_o, // command to unmap the PBL ROM
-    output          bad_opc6502_abortn      // command to ABORT the current instruction
+    output          bad_opc6502_abortn,     // command to ABORT the current instruction
+    output reg      brk00_opc_o     // BRK opcode detected
 );
     // IMPLEMENTATION
 
@@ -31,8 +33,10 @@ module cpu_observer
     // wire     isafix816_enabled;
 
     // detect bad opcodes of 6502 used in 65816 CPU:
-    wire    is_bad_opcode6502 = (cpu_dbo_i[2:0] == 3'b111) && !cputype02_i && is_isync_i /*&& !internal_cpu_res*/;
+    wire    is_opc_sep_rep = (cpu_dbo_i[7:0] == 8'hC2) || (cpu_dbo_i[7:0] == 8'hE2);
+    wire    is_bad_opcode6502 = ((cpu_dbo_i[2:0] == 3'b111) || is_opc_sep_rep) && !cputype02_i && is_isync_i /*&& !internal_cpu_res*/;
     wire    is_rti_opcode = (cpu_dbo_i == 8'h40) && is_isync_i /*&& !internal_cpu_res*/;
+    wire    is_brk_opcode = (cpu_dbo_i == 8'h00) && is_isync_i;
 
     // ABORTn generated by a bad opcode; signal active low
     reg     bad_opc6502_abort1n, bad_opc6502_abort2n;
@@ -50,6 +54,7 @@ module cpu_observer
             // icd_cpu_stop <= 0;
             map_pblrom_o <= 0;
             unmap_pblrom_o <= 0;
+            brk00_opc_o <= 0;
         end else begin
             // icd_cpu_stop <= 0;
             map_pblrom_o <= 0;
@@ -87,6 +92,8 @@ module cpu_observer
                     // -> yes, then clear the ROMBLOCK bits 7 and 6 to remove the PBL ROM from the map.
                     unmap_pblrom_o <= 1;
                 end
+
+                brk00_opc_o <= is_brk_opcode;
             end
 
             // first u-cycle after PHI2 falling?
@@ -95,6 +102,12 @@ module cpu_observer
                 bad_opc6502_abort2n <= bad_opc6502_abort1n;     // shift 
                 bad_opc6502_abort1n <= 1;           // 1=inactivate!
             end
+
+            // if the CPU is stopped, then clear the BRK opcode flag
+            if (stopped_cpu_i)
+            begin
+                brk00_opc_o <= 0;
+            end
         end
     end
 

fpga-nora/src/nora.v

@@ -281,7 +281,8 @@ module top (
             crwn_r              // bit[0]: CPU R/W signal
         };
 
-    wire     icd_cpu_stop;
+    wire     scrb_cpu_stop, brk00_opc;
+    wire     icd_cpu_stop = scrb_cpu_stop /*| brk00_opc */;
     wire     map_pblrom, unmap_pblrom;
     wire     bad_opc6502_abortn;
     // wire [7:0]  romblock_nr;
@@ -298,6 +299,7 @@ module top (
         .is_isync_i     (csync_vpa_r && cvda_r),
         .cpu_dbo_i      (cpu_db_o),
         .cef_i          (cef_r),
+        .stopped_cpu_i  (stopped_cpu),
         // Bus signals
         .release_wr_i   (release_wr),
         .release_cs_i   (release_cs),
@@ -306,7 +308,8 @@ module top (
         // Control outputs
         .map_pblrom_o   (map_pblrom),
         .unmap_pblrom_o (unmap_pblrom),
-        .bad_opc6502_abortn (bad_opc6502_abortn)
+        .bad_opc6502_abortn (bad_opc6502_abortn),
+        .brk00_opc_o    (brk00_opc)
     );
 
     /* ICD SPI Slave - MISO driver */
@@ -923,7 +926,7 @@ module top (
         .map_bootrom_i      (map_pblrom),            // Map PBL ROM to $E000-$FFFF (for ISAFIX handler)
         .unmap_bootrom_i    (unmap_pblrom),            // Unmap PBL ROM from $E000-$FFFF (for ISAFIX handler)
         // SYSCTRL
-        .cpu_stop_req_o  (icd_cpu_stop),
+        .cpu_stop_req_o  (scrb_cpu_stop),
         .cpu_reset_req_o  (icd_cpu_reset),
         .abrt02_en_o  (isafix816_enabled),
         // SPI Master interface for accessing the flash memory

sw-spiflash/common/isafix.s

@@ -76,6 +76,13 @@ TMP_BITNR = $F9
     ; and store it to our scratchpad.
     STA TMP_IBYTE
 
+    ; Is the faulting instruction REP (0xC2) ?
+    CMP     #$C2
+    beq     handle_rep          ; yes -> jump
+    ; Is the faulting instruction SEP (0xE2) ?
+    CMP     #$E2
+    beq     handle_sep          ; yes -> jump
+
     ; Load the ZP byte, which is in fact an address into zero page, and store to scratchpad
     LDA a:1, X            ; 8-bit load
     STA TMP_ZPBYTE          ; zp byte from the code
@@ -203,6 +210,15 @@ handle_rmb:         ; Reset memory bit
     STA (TMP_ZPBYTE)        ; write back
     ; BRA done_rmb_smb      fall through
 
+    ; -------------------------------------
+    ; Handling the SEP/REP instructions, which are valid but for X16 ROM reasons 
+    ; we want to emulate them as NOP.
+    ; These instructions are 2 bytes.
+handle_rep:
+handle_sep:
+    ; Just skip the REP/SEP by incrementing return address by 2...
+
+
 done_rmb_smb:
     ; SMB/RMB is done.
     ; Fix the return address on the stack - increment by two.

sw-spiflash/sbl-for-cx16/config-sbl.inc

@@ -7,7 +7,7 @@
 config_payload_block = 192
 
 ; how many 8k blocks of the payload (not counting this 8k SBL); 32 == 256k
-config_payload_bcount = 32
+config_payload_bcount = 34
 
 ; Configure NORA_RMBCTRL_REG config. to enable the following features necessary for CX16:
 ;   MIRROR_ZP = mirror RAMBLOCK and ROMBLOCK registers in the zero page ($00=RAMBLOCK and $01=RAMBLOCK)