From 40d96b851d350a45fb023d20df9c285f0f2e8f9b Mon Sep 17 00:00:00 2001 From: Talonj123 Date: Sun, 16 Jul 2017 22:16:12 -0500 Subject: [PATCH] Updated the Adder_tb file and test script to match other changes --- NCL Gates/NCL Gates.mpf | 60 +++++++++++++++-------------- NCL Gates/ncl/ncl.vhd | 6 +-- NCL Gates/ncl/tests/Adder_tb.vhd | 10 ++--- NCL Gates/scripts/tests/Counter.tcl | 37 ++++++++++-------- 4 files changed, 61 insertions(+), 52 deletions(-) diff --git a/NCL Gates/NCL Gates.mpf b/NCL Gates/NCL Gates.mpf index b333a8d..abefa2d 100644 --- a/NCL Gates/NCL Gates.mpf +++ b/NCL Gates/NCL Gates.mpf @@ -2034,49 +2034,51 @@ suppress = 8780 ;an explanation can be had by running: verror 8780 Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused -Project_Files_Count = 21 +Project_Files_Count = 22 Project_File_0 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/scripts/tests/FullAdder.tcl -Project_File_P_0 = compile_order -1 last_compile 0 folder test_scripts dont_compile 1 group_id 0 file_type tcl ood 1 +Project_File_P_0 = folder test_scripts last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1 Project_File_1 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/components/Register.vhd -Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499465356 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499465356 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_2 = ncl/ncl.vhd -Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl last_compile 1499636920 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl last_compile 1500260409 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_3 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/components/Decoder.vhd -Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499465368 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499465368 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_4 = ncl/tests/Decoder2_tb.vhd -Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1499382911 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1499382911 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_5 = scripts/tests/t11_tb.tcl -Project_File_P_5 = folder test_scripts last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1 +Project_File_P_5 = compile_order -1 last_compile 0 folder test_scripts dont_compile 1 group_id 0 file_type tcl ood 1 Project_File_6 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/components/MUX.vhd -Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499465477 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499465477 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_7 = scripts/tests/t21_tb.tcl -Project_File_P_7 = folder test_scripts last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1 +Project_File_P_7 = compile_order -1 last_compile 0 folder test_scripts dont_compile 1 group_id 0 file_type tcl ood 1 Project_File_8 = ncl/impl.vhd -Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl last_compile 1499637396 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl last_compile 1499637396 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_9 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/tests/T22_tb.vhd -Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1499465428 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1499465428 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_10 = scripts/tests/test_threshold_gate.tcl -Project_File_P_10 = folder test_scripts last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1 +Project_File_P_10 = compile_order -1 last_compile 0 folder test_scripts dont_compile 1 group_id 0 file_type tcl ood 1 Project_File_11 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/components/FullAdder.vhd -Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499821360 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499821691 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_12 = ncl/tests/MUX2_tb.vhd -Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1499382436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1499382436 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_13 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/scripts/tests/HalfAdder.tcl -Project_File_P_13 = vhdl_novitalcheck 0 file_type tcl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder test_scripts last_compile 0 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002 -Project_File_14 = ncl/tests/Adder_tb.vhd -Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1499099824 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_15 = scripts/tests/setup.tcl -Project_File_P_15 = folder test_scripts last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1 -Project_File_16 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/tests/T11_tb.vhd -Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1499465436 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_17 = scripts/tests/run_tb.tcl -Project_File_P_17 = folder test_scripts last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1 -Project_File_18 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/tests/T21_tb.vhd -Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1499465444 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_19 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/components/HalfAdder.vhd -Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499645329 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_20 = scripts/tests/t22_tb.tcl -Project_File_P_20 = folder test_scripts last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1 +Project_File_P_13 = vhdl_novitalcheck 0 file_type tcl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder test_scripts last_compile 0 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order -1 cover_nosub 0 dont_compile 1 vhdl_use93 2002 +Project_File_14 = scripts/tests/Counter.tcl +Project_File_P_14 = compile_order -1 last_compile 0 folder test_scripts dont_compile 1 group_id 0 file_type tcl ood 1 +Project_File_15 = ncl/tests/Adder_tb.vhd +Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1500260361 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_16 = scripts/tests/setup.tcl +Project_File_P_16 = compile_order -1 last_compile 0 folder test_scripts dont_compile 1 group_id 0 file_type tcl ood 1 +Project_File_17 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/tests/T11_tb.vhd +Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1499465436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_18 = scripts/tests/run_tb.tcl +Project_File_P_18 = compile_order -1 last_compile 0 folder test_scripts dont_compile 1 group_id 0 file_type tcl ood 1 +Project_File_19 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/tests/T21_tb.vhd +Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_tests last_compile 1499465444 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_20 = C:/Users/Talonj123/git/Asynchronous-Logic/NCL Gates/ncl/components/HalfAdder.vhd +Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder ncl_components last_compile 1499645329 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_21 = scripts/tests/t22_tb.tcl +Project_File_P_21 = compile_order -1 last_compile 0 folder test_scripts dont_compile 1 group_id 0 file_type tcl ood 1 Project_Sim_Count = 0 Project_Folder_Count = 5 Project_Folder_0 = scripts diff --git a/NCL Gates/ncl/ncl.vhd b/NCL Gates/ncl/ncl.vhd index 98b99b9..ba5e14e 100644 --- a/NCL Gates/ncl/ncl.vhd +++ b/NCL Gates/ncl/ncl.vhd @@ -37,11 +37,11 @@ package ncl is end component; component FullAdder is - port(cin : in ncl_pair; + port(iC : in ncl_pair; a : in ncl_pair; b : in ncl_pair; - sum : out ncl_pair; - cout : out ncl_pair); + oS : out ncl_pair; + oC : out ncl_pair); end component; component MUX is diff --git a/NCL Gates/ncl/tests/Adder_tb.vhd b/NCL Gates/ncl/tests/Adder_tb.vhd index c331d7d..785b128 100644 --- a/NCL Gates/ncl/tests/Adder_tb.vhd +++ b/NCL Gates/ncl/tests/Adder_tb.vhd @@ -2,7 +2,7 @@ library ieee; use ieee.std_logic_1164.all; use work.ncl.all; -entity Counter_TB is +entity Adder_TB is port(iA : in ncl_pair; iB : in ncl_pair; iC : in ncl_pair; @@ -10,9 +10,9 @@ entity Counter_TB is -- from_next : in std_logic; oS : out ncl_pair; oC : out ncl_pair); -end entity Counter_TB; +end entity Adder_TB; -architecture structural of Counter_TB is +architecture structural of Adder_TB is signal A : ncl_pair; signal B : ncl_pair; signal Cin : ncl_pair; @@ -33,8 +33,8 @@ begin from_next => internal_control, to_prev => to_prev); Adder: FullAdder - port map(a => A, b => B, cin => Cin, - sum => S, cout => Cout); + port map(a => A, b => B, iC => Cin, + oS => S, oC => Cout); RegAfter: RegisterN generic map(N => 2) diff --git a/NCL Gates/scripts/tests/Counter.tcl b/NCL Gates/scripts/tests/Counter.tcl index 1abc4e2..2fe6c0f 100644 --- a/NCL Gates/scripts/tests/Counter.tcl +++ b/NCL Gates/scripts/tests/Counter.tcl @@ -86,17 +86,17 @@ proc set_inputs {A B C} { } proc null_inputs {} { - force -drive /adder_tb/iA.DATA1 0 [expr round(rand()*5)] - force -drive /adder_tb/iA.DATA0 0 [expr round(rand()*5)] + force -drive /adder_tb/iA.DATA1 0 [expr round(rand()*5)] + force -drive /adder_tb/iA.DATA0 0 [expr round(rand()*5)] - force -drive /adder_tb/iB.DATA1 0 [expr round(rand()*5)] - force -drive /adder_tb/iB.DATA0 0 [expr round(rand()*5)] + force -drive /adder_tb/iB.DATA1 0 [expr round(rand()*5)] + force -drive /adder_tb/iB.DATA0 0 [expr round(rand()*5)] - force -drive /adder_tb/iC.DATA1 0 [expr round(rand()*5)] - force -drive /adder_tb/iC.DATA0 0 [expr round(rand()*5)] + force -drive /adder_tb/iC.DATA1 0 [expr round(rand()*5)] + force -drive /adder_tb/iC.DATA0 0 [expr round(rand()*5)] } -vcom -O1 -lint -quiet -check_synthesis -work work ncl/ncl.vhd ncl/impl.vhd ncl/components/FullAdder.vhd ncl/components/Register.vhd ncl/tests/CounterTest.vhd +vcom -O1 -lint -quiet -check_synthesis -work work ncl/ncl.vhd ncl/impl.vhd ncl/components/FullAdder.vhd ncl/components/Register.vhd ncl/tests/Adder_tb.vhd view wave delete wave * vsim -quiet work.adder_tb @@ -109,9 +109,9 @@ quietly virtual signal -install /adder_tb { (context /adder_tb )(oC.data0 & oC.d quietly virtual signal -install /adder_tb/Adder { (context /adder_tb/Adder )(a.data0 & a.data1 )} {a_virt} quietly virtual signal -install /adder_tb/Adder { (context /adder_tb/Adder )(b.data0 & b.data1 )} {b_virt} -quietly virtual signal -install /adder_tb/Adder { (context /adder_tb/Adder )(cin.data0 & cin.data1 )} {cin_virt} -quietly virtual signal -install /adder_tb/Adder { (context /adder_tb/Adder )(sum.data0 & sum.data1 )} {sum_virt} -quietly virtual signal -install /adder_tb/Adder { (context /adder_tb/Adder )(cout.data0 & cout.data1 )} {cout_virt} +quietly virtual signal -install /adder_tb/Adder { (context /adder_tb/Adder )(iC.data0 & iC.data1 )} {iC_virt} +quietly virtual signal -install /adder_tb/Adder { (context /adder_tb/Adder )(oS.data0 & oS.data1 )} {oS_virt} +quietly virtual signal -install /adder_tb/Adder { (context /adder_tb/Adder )(oC.data0 & oC.data1 )} {oC_virt} #quietly virtual signal -install /adder_tb/RegBefore { (context /adder_tb/RegBefore )(inputs(0).data0 & inputs(0).data1 )} {i0_virt} #quietly virtual signal -install /adder_tb/RegBefore { (context /adder_tb/RegBefore )(inputs(1).data0 & inputs(1).data1 )} {i1_virt} @@ -140,24 +140,31 @@ add wave -radix ncl_pair_out -label "Output C" -color $input_color sim:/adder_tb #add wave -label "out(2)" -radix ncl_pair_out -color $input_color /adder_tb/RegBefore/o2_virt # #add wave -divider "Adder" -#add wave -label "Cin" -radix ncl_pair_in -color $input_color /adder_tb/Adder/cin_virt +#add wave -label "iC" -radix ncl_pair_in -color $input_color /adder_tb/Adder/iC_virt #add wave -label "A" -radix ncl_pair_in -color $input_color /adder_tb/Adder/a_virt #add wave -label "B" -radix ncl_pair_in -color $input_color /adder_tb/Adder/b_virt -#add wave -label "Sum" -radix ncl_pair_out -color $output_color /adder_tb/Adder/sum_virt -#add wave -label "Cout" -radix ncl_pair_out -color $output_color /adder_tb/Adder/cout_virt +#add wave -label "oS" -radix ncl_pair_out -color $output_color /adder_tb/Adder/oS_virt +#add wave -label "oC" -radix ncl_pair_out -color $output_color /adder_tb/Adder/oC_virt null_inputs_now +set expectedS 0 +set expectedC 0 run 50 for {set A 0} {$A <= 1} {incr A} { for {set B 0} {$B <= 1} {incr B} { - for {set S 0} {$S <= 1} {incr S} { + for {set C 0} {$C <= 1} {incr C} { null_inputs while {[examine /adder_tb/to_prev] != 1} { run 1 } - puts $expected run 10 + #check + puts "Time: $now. S: $expectedS C: $expectedC" + set expectedS [expr (($A + $B + $C) >> 0) & 1] + set expectedC [expr (($A + $B + $C) >> 1) & 1] + set_inputs $A $B $C while {[examine /adder_tb/to_prev] != 0} { run 1 } run 10 } } } +puts "Time: $now. S: $expectedS C: $expectedC" run 100 \ No newline at end of file