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8 CONTRIBUTORS
@@ -0,0 +1,8 @@
+This is the list of people who can contribute (or have contributed) to this
+project. This includes code, documentation, testing, content creation and
+bugfixes.
+
+Names should be added to this file like so: Name [email address].
+Please keep the list sorted.
+
+Jim Teeuwen [jimteeuwen at gmail dot com]
18 LICENSE
@@ -0,0 +1,18 @@
+Copyright (c) 2010-2012, Jim Teeuwen
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
13 README.md
@@ -0,0 +1,13 @@
+## DCPU
+
+This repository contains DCPU assembly code.
+Mostly commonly used library bits and bobs, along with a preprocessor
+which should make the writing of larger programs a little less painful.
+
+### License
+
+DCPU, 0x10c and related materials are Copyright 2012 Mojang.
+
+Unless otherwise stated, all of the work in this project is subject to a
+1-clause BSD license. Its contents can be found in the enclosed LICENSE file.
+
24 dcpu-pp/README.md
@@ -0,0 +1,24 @@
+## DCPU Preprocessor
+
+This app is a DCPU Assembly preprocessor. It parses the given input file(s).
+
+Any references to undefined labels are assumed to be defined
+in external files names `<labelname>.dasm`. The 'assembler' looks in a
+predefined path to resolve these files. It then simply includes the file
+contents into the main source file. This allows us to keep source files
+small and manageable.
+
+Everything is minified and stripped of unnecessary bloat and then
+spit out as a single chunk of DCPU assembly code. This can be pasted into
+any of the numerous emulators and run.
+
+### Usage
+
+ go get github.com/jteeuwen/dcpu/dcpu-pp
+
+### License
+
+DCPU, 0x10c and related materials are Copyright 2012 Mojang.
+
+Unless otherwise stated, all of the work in this project is subject to a
+1-clause BSD license. Its contents can be found in the enclosed LICENSE file.
0  dcpu-pp/config.go
No changes.
19 dcpu-pp/main.go
@@ -0,0 +1,19 @@
+// This file is subject to a 1-clause BSD license.
+// Its contents can be found in the enclosed LICENSE file.
+
+package main
+
+import (
+
+)
+
+func main() {
+
+}
+
+// process commandline arguments.
+func parseArgs() *Config {
+ c := NewConfig()
+
+ return c
+}
199 doc/dcpu.lang
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--
+Copyright (c) 2010-2012, Jim Teeuwen
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-->
+<language id="dasm" _name="DASM" version="2.0" _section="Sources">
+ <metadata>
+ <property name="mimetypes">text/x-dasm</property>
+ <property name="globs">*.dasm;*.dasm16</property>
+ <property name="line-comment-start">;</property>
+ </metadata>
+
+ <styles>
+ <style id="comment" _name="Comment" map-to="def:comment"/>
+ <style id="error" _name="Error" map-to="def:error"/>
+ <style id="string" _name="String" map-to="def:string"/>
+ <style id="common-defines" _name="Common Defines" map-to="def:special-constant"/>
+ <style id="included-file" _name="Included File" map-to="def:string"/>
+ <style id="char" _name="Character" map-to="def:character"/>
+ <style id="keyword" _name="Keyword" map-to="def:keyword"/>
+ <style id="escaped-character" _name="Escaped Character" map-to="def:special-char"/>
+ <style id="floating-point" _name="Floating point number" map-to="def:floating-point"/>
+ <style id="decimal" _name="Decimal number" map-to="def:decimal"/>
+ <style id="octal" _name="Octal number" map-to="def:base-n-integer"/>
+ <style id="hexadecimal" _name="Hexadecimal number" map-to="def:base-n-integer"/>
+ <style id="binary" _name="Binary number" map-to="def:base-n-integer"/>
+ <style id="type" _name="Data Type" map-to="def:type"/>
+ </styles>
+
+ <default-regex-options case-sensitive="false" />
+
+ <definitions>
+ <define-regex id="escaped-character" extended="true">
+ \\(
+ [\\\"\'nrbtfav\?]|
+ [0-7]{1,3}|
+ [xX][0-9A-Fa-f]+|
+ u[0-9A-Fa-f]{4}|
+ U[0-9A-Fa-f]{8}
+ )
+ </define-regex>
+
+ <context id="dasm-proper">
+ <include>
+ <context id="comment" style-ref="comment" end-at-line-end="true">
+ <start>;</start>
+ <include>
+ <context ref="def:in-line-comment"/>
+ </include>
+ </context>
+
+ <context id="string" style-ref="string" end-at-line-end="true">
+ <start>"</start>
+ <end>"</end>
+ <include>
+ <context id="escaped-character" style-ref="escaped-character">
+ <match>\%{escaped-character}</match>
+ </context>
+ <context ref="def:line-continue"/>
+ </include>
+ </context>
+
+ <context id="string1" style-ref="string" end-at-line-end="false">
+ <start>`</start>
+ <end>`</end>
+ <include>
+ <context ref="escaped-character"/>
+ <context ref="def:line-continue"/>
+ </include>
+ </context>
+
+ <context id="char" style-ref="char">
+ <match>'(\%{escaped-character}|.)'</match>
+ </context>
+
+ <context id="float" style-ref="floating-point">
+ <match extended="true">
+ (?&lt;![\w\.])
+ ((\.[0-9]+ | [0-9]+\.[0-9]*) ([Ee][+-]?[0-9]*)? |
+ ([0-9]+[Ee][+-]?[0-9]*))
+ [fFlL]?
+ (?![\w\.])
+ </match>
+ </context>
+
+ <context id="hexadecimal" style-ref="hexadecimal">
+ <match extended="true">
+ (?&lt;![\w\.])
+ 0[xX][a-fA-F0-9]+
+ (?![\w\.])
+ </match>
+ </context>
+
+ <context id="binary" style-ref="binary">
+ <match extended="true">
+ (?&lt;![\w\.])
+ 0[bB][01]+
+ (?![\w\.])
+ </match>
+ </context>
+
+ <context id="octal" style-ref="octal">
+ <match extended="true">
+ (?&lt;![\w\.])
+ 0[0-7]+
+ (?![\w\.])
+ </match>
+ </context>
+
+ <context id="decimal" style-ref="decimal">
+ <match extended="true">
+ (?&lt;![\w\.])
+ [0-9]+
+ (?![\w\.])
+ </match>
+ </context>
+
+ <context id="keywords" style-ref="keyword">
+ <keyword>set</keyword>
+ <keyword>add</keyword>
+ <keyword>sub</keyword>
+ <keyword>mul</keyword>
+ <keyword>mli</keyword>
+ <keyword>div</keyword>
+ <keyword>dvi</keyword>
+ <keyword>mod</keyword>
+ <keyword>mdi</keyword>
+ <keyword>and</keyword>
+ <keyword>bor</keyword>
+ <keyword>xor</keyword>
+ <keyword>shr</keyword>
+ <keyword>asr</keyword>
+ <keyword>shl</keyword>
+ <keyword>ifb</keyword>
+ <keyword>ifc</keyword>
+ <keyword>ife</keyword>
+ <keyword>ifn</keyword>
+ <keyword>ifg</keyword>
+ <keyword>ifa</keyword>
+ <keyword>ifl</keyword>
+ <keyword>ifu</keyword>
+ <keyword>adx</keyword>
+ <keyword>sbx</keyword>
+ <keyword>sti</keyword>
+ <keyword>std</keyword>
+ <keyword>jsr</keyword>
+ <keyword>int</keyword>
+ <keyword>iag</keyword>
+ <keyword>ias</keyword>
+ <keyword>rfi</keyword>
+ <keyword>iaq</keyword>
+ <keyword>hwn</keyword>
+ <keyword>hwq</keyword>
+ <keyword>hwi</keyword>
+ <keyword>dat</keyword>
+ <keyword>brk</keyword>
+ </context>
+
+ <context id="types" style-ref="type">
+ <keyword>A</keyword>
+ <keyword>B</keyword>
+ <keyword>C</keyword>
+ <keyword>X</keyword>
+ <keyword>Y</keyword>
+ <keyword>Z</keyword>
+ <keyword>I</keyword>
+ <keyword>J</keyword>
+ <keyword>PC</keyword>
+ <keyword>SP</keyword>
+ <keyword>EX</keyword>
+ <keyword>IA</keyword>
+ <keyword>PUSH</keyword>
+ <keyword>POP</keyword>
+ <keyword>PEEK</keyword>
+ </context>
+ </include>
+ </context>
+
+ <context id="dasm">
+ <include><context ref="dasm-proper"/></include>
+ </context>
+ </definitions>
+</language>
212 doc/dcpu.txt
@@ -0,0 +1,212 @@
+DCPU-16 Specification
+Copyright 1985 Mojang
+Version 1.7
+
+
+
+=== SUMMARY ====================================================================
+
+* 16 bit words
+* 0x10000 words of ram
+* 8 registers (A, B, C, X, Y, Z, I, J)
+* program counter (PC)
+* stack pointer (SP)
+* extra/excess (EX)
+* interrupt address (IA)
+
+In this document, anything within [brackets] is shorthand for "the value of the
+RAM at the location of the value inside the brackets". For example, SP means
+stack pointer, but [SP] means the value of the RAM at the location the stack
+pointer is pointing at.
+
+Whenever the CPU needs to read a word, it reads [PC], then increases PC by one.
+Shorthand for this is [PC++]. In some cases, the CPU will modify a value before
+reading it, in this case the shorthand is [++PC].
+
+For stability and to reduce bugs, it's strongly suggested all multi-word
+operations use little endian in all DCPU-16 programs, wherever possible.
+
+
+
+=== INSTRUCTIONS ===============================================================
+
+Instructions are 1-3 words long and are fully defined by the first word.
+In a basic instruction, the lower five bits of the first word of the instruction
+are the opcode, and the remaining eleven bits are split into a five bit value b
+and a six bit value a.
+b is always handled by the processor after a, and is the lower five bits.
+In bits (in LSB-0 format), a basic instruction has the format: aaaaaabbbbbooooo
+
+In the tables below, C is the time required in cycles to look up the value, or
+perform the opcode, VALUE is the numerical value, NAME is the mnemonic, and
+DESCRIPTION is a short text that describes the opcode or value.
+
+
+
+--- Values: (5/6 bits) ---------------------------------------------------------
+ C | VALUE | DESCRIPTION
+---+-----------+----------------------------------------------------------------
+ 0 | 0x00-0x07 | register (A, B, C, X, Y, Z, I or J, in that order)
+ 0 | 0x08-0x0f | [register]
+ 1 | 0x10-0x17 | [register + next word]
+ 0 | 0x18 | (PUSH / [--SP]) if in b, or (POP / [SP++]) if in a
+ 0 | 0x19 | [SP] / PEEK
+ 1 | 0x1a | [SP + next word] / PICK n
+ 0 | 0x1b | SP
+ 0 | 0x1c | PC
+ 0 | 0x1d | EX
+ 1 | 0x1e | [next word]
+ 1 | 0x1f | next word (literal)
+ 0 | 0x20-0x3f | literal value 0xffff-0x1e (-1..30) (literal) (only for a)
+ --+-----------+----------------------------------------------------------------
+
+* "next word" means "[PC++]". Increases the word length of the instruction by 1.
+* By using 0x18, 0x19, 0x1a as PEEK, POP/PUSH, and PICK there's a reverse stack
+ starting at memory location 0xffff. Example: "SET PUSH, 10", "SET X, POP"
+* Attempting to write to a literal value fails silently
+
+
+
+--- Basic opcodes (5 bits) ----------------------------------------------------
+ C | VAL | NAME | DESCRIPTION
+---+------+----------+---------------------------------------------------------
+ - | 0x00 | n/a | special instruction - see below
+ 1 | 0x01 | SET b, a | sets b to a
+ 2 | 0x02 | ADD b, a | sets b to b+a, sets EX to 0x0001 if there's an overflow,
+ | | | 0x0 otherwise
+ 2 | 0x03 | SUB b, a | sets b to b-a, sets EX to 0xffff if there's an underflow,
+ | | | 0x0 otherwise
+ 2 | 0x04 | MUL b, a | sets b to b*a, sets EX to ((b*a)>>16)&0xffff (treats b,
+ | | | a as unsigned)
+ 2 | 0x05 | MLI b, a | like MUL, but treat b, a as signed
+ 3 | 0x06 | DIV b, a | sets b to b/a, sets EX to ((b<<16)/a)&0xffff. if a==0,
+ | | | sets b and EX to 0 instead. (treats b, a as unsigned)
+ 3 | 0x07 | DVI b, a | like DIV, but treat b, a as signed. Rounds towards 0
+ 3 | 0x08 | MOD b, a | sets b to b%a. if a==0, sets b to 0 instead.
+ 3 | 0x09 | MDI b, a | like MOD, but treat b, a as signed. (MDI -7, 16 == -7)
+ 1 | 0x0a | AND b, a | sets b to b&a
+ 1 | 0x0b | BOR b, a | sets b to b|a
+ 1 | 0x0c | XOR b, a | sets b to b^a
+ 1 | 0x0d | SHR b, a | sets b to b>>>a, sets EX to ((b<<16)>>a)&0xffff
+ | | | (logical shift)
+ 1 | 0x0e | ASR b, a | sets b to b>>a, sets EX to ((b<<16)>>>a)&0xffff
+ | | | (arithmetic shift) (treats b as signed)
+ 1 | 0x0f | SHL b, a | sets b to b<<a, sets EX to ((b<<a)>>16)&0xffff
+
+ 2+| 0x10 | IFB b, a | performs next instruction only if (b&a)!=0
+ 2+| 0x11 | IFC b, a | performs next instruction only if (b&a)==0
+ 2+| 0x12 | IFE b, a | performs next instruction only if b==a
+ 2+| 0x13 | IFN b, a | performs next instruction only if b!=a
+ 2+| 0x14 | IFG b, a | performs next instruction only if b>a
+ 2+| 0x15 | IFA b, a | performs next instruction only if b>a (signed)
+ 2+| 0x16 | IFL b, a | performs next instruction only if b<a
+ 2+| 0x17 | IFU b, a | performs next instruction only if b<a (signed)
+ - | 0x18 | - |
+ - | 0x19 | - |
+ 3 | 0x1a | ADX b, a | sets b to b+a+EX, sets EX to 0x0001 if there is an over-
+ | | | flow, 0x0 otherwise
+ 3 | 0x1b | SBX b, a | sets b to b-a+EX, sets EX to 0xFFFF if there is an under-
+ | | | flow, 0x0 otherwise
+ - | 0x1c | - |
+ - | 0x1d | - |
+ 2 | 0x1e | STI b, a | sets b to a, then increases I and J by 1
+ 2 | 0x1f | STD b, a | sets b to a, then decreases I and J by 1
+---+------+----------+----------------------------------------------------------
+
+* The branching opcodes take one cycle longer to perform if the test fails
+ When they skip an if instruction, they will skip an additional instruction
+ at the cost of one extra cycle. This lets you easily chain conditionals.
+* Signed numbers are represented using two's complement.
+
+
+Special opcodes always have their lower five bits unset, have one value and a
+five bit opcode. In binary, they have the format: aaaaaaooooo00000
+The value (a) is in the same six bit format as defined earlier.
+
+--- Special opcodes: (5 bits) --------------------------------------------------
+ C | VAL | NAME | DESCRIPTION
+---+------+-------+-------------------------------------------------------------
+ - | 0x00 | n/a | reserved for future expansion
+ 3 | 0x01 | JSR a | pushes the address of the next instruction to the stack,
+ | | | then sets PC to a
+ - | 0x02 | - |
+ - | 0x03 | - |
+ - | 0x04 | - |
+ - | 0x05 | - |
+ - | 0x06 | - |
+ - | 0x07 | - |
+ 4 | 0x08 | INT a | triggers a software interrupt with message a
+ 1 | 0x09 | IAG a | sets a to IA
+ 1 | 0x0a | IAS a | sets IA to a
+ 3 | 0x0b | RFI a | disables interrupt queueing, pops A from the stack, then
+ | | | pops PC from the stack
+ 2 | 0x0c | IAQ a | if a is nonzero, interrupts will be added to the queue
+ | | | instead of triggered. if a is zero, interrupts will be
+ | | | triggered as normal again
+ - | 0x0d | - |
+ - | 0x0e | - |
+ - | 0x0f | - |
+ 2 | 0x10 | HWN a | sets a to number of connected hardware devices
+ 4 | 0x11 | HWQ a | sets A, B, C, X, Y registers to information about hardware a
+ | | | A+(B<<16) is a 32 bit word identifying the hardware id
+ | | | C is the hardware version
+ | | | X+(Y<<16) is a 32 bit word identifying the manufacturer
+ 4+| 0x12 | HWI a | sends an interrupt to hardware a
+ - | 0x13 | - |
+ - | 0x14 | - |
+ - | 0x15 | - |
+ - | 0x16 | - |
+ - | 0x17 | - |
+ - | 0x18 | - |
+ - | 0x19 | - |
+ - | 0x1a | - |
+ - | 0x1b | - |
+ - | 0x1c | - |
+ - | 0x1d | - |
+ - | 0x1e | - |
+ - | 0x1f | - |
+---+------+-------+-------------------------------------------------------------
+
+
+
+=== INTERRUPTS =================================================================
+
+The DCPU-16 will perform at most one interrupt between each instruction. If
+multiple interrupts are triggered at the same time, they are added to a queue.
+If the queue grows longer than 256 interrupts, the DCPU-16 will catch fire.
+
+When IA is set to something other than 0, interrupts triggered on the DCPU-16
+will turn on interrupt queueing, push PC to the stack, followed by pushing A to
+the stack, then set the PC to IA, and A to the interrupt message.
+
+If IA is set to 0, a triggered interrupt does nothing. Software interrupts still
+take up four clock cycles, but immediately return, incoming hardware interrupts
+are ignored. Note that a queued interrupt is considered triggered when it leaves
+the queue, not when it enters it.
+
+Interrupt handlers should end with RFI, which will disable interrupt queueing
+and pop A and PC from the stack as a single atomic instruction.
+IAQ is normally not needed within an interrupt handler, but is useful for time
+critical code.
+
+
+
+
+=== HARDWARE ===================================================================
+
+The DCPU-16 supports up to 65535 connected hardware devices. These devices can
+be anything from additional storage, sensors, monitors or speakers.
+How to control the hardware is specified per hardware device, but the DCPU-16
+supports a standard enumeration method for detecting connected hardware via
+the HWN, HWQ and HWI instructions.
+
+Interrupts sent to hardware can't contain messages, can take additional cycles,
+and can read or modify any registers or memory adresses on the DCPU-16. This
+behavior changes per hardware device and is described in the hardware's
+documentation.
+
+Hardware must NOT start modifying registers or ram on the DCPU-16 before at
+least one HWI call has been made to the hardware.
+
+The DPCU-16 does not support hot swapping hardware. The behavior of connecting
+or disconnecting hardware while the DCPU-16 is running is undefined.
10 testdata/disp_clear.dasm
@@ -0,0 +1,10 @@
+; disp_clear(a:start, b:size, c:clr)
+; Fills the screen with a given background colour.
+:disp_clear
+ set i, a
+ set j, b
+:disp_clear_loop
+ sti [i], c
+ ifl i, b
+ set pc, disp_clear_loop
+ set pc, pop
25 testdata/hw_detect.dasm
@@ -0,0 +1,25 @@
+; hw_detect finds a specific hardware device index
+; based on the device ID you specify in registers
+; A and B. It returns the device index in A.
+; A will be -1 if the device was not found.
+:hw_detect
+ set i, a
+ set j, b
+ hwn z
+ sub z, 1
+
+:hw_detect_loop
+ hwq z
+
+ ife a, i
+ ife b, j
+ set pc, hw_detect_ret
+
+ sub z, 1
+ ifg z, 0
+ set pc, hw_detect_loop
+
+:hw_detect_ret
+ set a, z
+ set pc, pop
+
31 testdata/printHex.dasm
@@ -0,0 +1,31 @@
+; printHex(a:dst, b:num, c:clr)
+; Prints the string representation of
+; the given number.
+:printHex
+ set push, 0xff
+
+:printHex_loop1
+ set push, b
+ mod peek, 16
+ shr b, 5
+
+ ifn b, 0
+ set pc, printHex_loop1
+
+:printHex_loop2
+ set [a], pop
+ add [a], 0x30
+
+ ifg [a], 0x39
+ add [a], 7
+
+ bor [a], c
+ add a, 1
+
+ ifn peek, 0xff
+ set pc, printHex_loop2
+
+ set [a], 0x68
+ bor [a], c
+ add sp, 1
+ set pc, pop
11 testdata/printLn.dasm
@@ -0,0 +1,11 @@
+; printLn(a:dst, b:src, c:style)
+; Prints the given string.
+:printLn
+ set i, a
+ set j, b
+:printLn_loop
+ ife [j], 0
+ set pc, pop
+ bor [j], c
+ sti [i], [j]
+ set pc, printLn_loop
96 testdata/test.dasm
@@ -0,0 +1,96 @@
+; Find display
+ set a, 0xf615
+ set b, 0x7349
+ jsr hw_detect
+ set [display], a
+
+; Find keyboard
+ set a, 0x7406
+ set b, 0x30cf
+ jsr hw_detect
+ set [keyboard], a
+
+; Find clock
+ set a, 0xb402
+ set b, 0x12d0
+ jsr hw_detect
+ set [clock], a
+
+; map vidmem
+ set a, 0
+ set b, [vidmem]
+ hwi [display]
+
+; set border colour
+ set a, 3
+ set b, 9 ; lightblue
+ hwi [display]
+
+ set a, [vidmem]
+ set b, a
+ add b, [screenSize]
+ set c, 0x9120
+ jsr disp_clear
+
+; println(disp_label)
+ set a, 0x21
+ add a, [vidmem]
+ set b, strDisplay
+ set c, 0x9100
+ jsr printLn
+
+
+; printHex(disp_address)
+ set a, 0x2c
+ add a, [vidmem]
+ set b, [display]
+ jsr printHex
+
+
+; println(keyboard_label)
+ set a, 0x41
+ add a, [vidmem]
+ set b, strKeyboard
+ jsr printLn
+
+
+; printHex(keyboard_address)
+ set a, 0x4c
+ add a, [vidmem]
+ set b, [keyboard]
+ jsr printHex
+
+
+; println(clock_label)
+ set a, 0x61
+ add a, [vidmem]
+ set b, strClock
+ jsr printLn
+
+
+; printHex(clock_address)
+ set a, 0x6c
+ add a, [vidmem]
+ set b, [clock]
+ jsr printHex
+
+ sub pc, 1
+
+; Program data for various purposes.
+:strDisplay
+ dat "* Display: ", 0
+:strKeyboard
+ dat "* Keyboard: ", 0
+:strClock
+ dat "* Clock: ", 0
+:vidmem
+ dat 0x8000
+:display
+ dat 0
+:keyboard
+ dat 0
+:clock
+ dat 0
+:screenSize
+ dat 0x182
+
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