diff --git a/Lab5/instruction_rom.mif b/Lab5/instruction_rom.mif
@@ -18,9 +18,16 @@ WIDTH=8;
 DEPTH=256;
 
 ADDRESS_RADIX=UNS;
-DATA_RADIX=UNS;
+DATA_RADIX=BIN;
 
 CONTENT BEGIN
-	0    :   1;
-	[1..255]  :   0;
+	0    :   01100000;
+	1    :   01001010;
+	2    :   01111100;
+	3    :   01000011;
+	4    :   11000100;
+	5    :   00111000;
+	6    :   11001000;
+	7    :   10011001;
+	[8..255]  :   00000000;
 END;
diff --git a/Lab5/lab5.jdi b/Lab5/lab5.jdi
@@ -1,6 +1,6 @@
 <sld_project_info>
   <project>
-    <hash md5_digest_80b="cc11d44b993eeeb0f8ff"/>
+    <hash md5_digest_80b="fdf43721094b4f44ac2b"/>
   </project>
   <file_info>
     <file device="EP2C35F672C6" path="lab5.sof" usercode="0xFFFFFFFF"/>

diff --git a/Lab5/lab5.pin b/Lab5/lab5.pin
diff --git a/Lab5/lab5.qsf b/Lab5/lab5.qsf
@@ -81,10 +81,11 @@ set_global_assignment -name VECTOR_WAVEFORM_FILE delay_counter_sim.vwf
 set_global_assignment -name VECTOR_WAVEFORM_FILE temp_register_sim.vwf
 set_global_assignment -name VECTOR_WAVEFORM_FILE immediate_extractor_sim.vwf
 set_global_assignment -name VECTOR_WAVEFORM_FILE decoder_sim.vwf
-set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/CameronSwinoga/OneDrive/Documents/School/McMaster/Third Year/MECHTRON 3TB4/3TB4_Labs/Lab5/decoder_sim.vwf"
 set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name VECTOR_WAVEFORM_FILE full_sim.vwf
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/Users/CameronSwinoga/OneDrive/Documents/School/McMaster/Third Year/MECHTRON 3TB4/3TB4_Labs/Lab5/full_sim.vwf"
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/Lab5/lab5.v b/Lab5/lab5.v
@@ -2,7 +2,9 @@
 module lab5 (
 	input clk, reset_n,
 	output [3:0] stepper_signals,
-	output [3:0] LEDG
+	output [3:0] LEDG,
+	output [7:0] _PC,
+	output [4:0] _STATE
 	);
 
 	wire br, brz, addi, subi, sr0, srh0, clr, mov, mova, movr, movrhs, pause;
@@ -59,7 +61,8 @@ module lab5 (
 		.increment_temp_register (increment_temp_register),
 		.decrement_temp_register (decrement_temp_register),
 		.select_immediate (select_immediate),
-		.select_write_address (select_write_address)	
+		.select_write_address (select_write_address),
+		._STATE(_STATE)
 	);
 
 	datapath the_datapath (
@@ -101,8 +104,9 @@ module lab5 (
 		.temp_is_zero (temp_is_zero),
 		.register0_is_zero (register0_is_zero),
 		// Motor control outputs
-		.stepper_signals (stepper_signals)
+		.stepper_signals (stepper_signals),
 		// Temporary outputs for debugging purposes
+		._PC(_PC)
 	);
 
 

diff --git a/Lab5/stepper_rom.mif b/Lab5/stepper_rom.mif
@@ -18,9 +18,15 @@ WIDTH=4;
 DEPTH=8;
 
 ADDRESS_RADIX=UNS;
-DATA_RADIX=UNS;
+DATA_RADIX=BIN;
 
 CONTENT BEGIN
-	0  :   15;
-	[1..7]  :   0;
+	0  :   1000;
+	1  :   1100;
+	2  :   0100;
+	3  :   0110;
+	4  :   0010;
+	5  :   0011;
+	6  :   0001;
+	7  :   1001;
 END;