Repository is intended for use with Xilinx EDK tools. It is divided (as required) to boards and pcores directories. First one contains board definitions and the following one libraries and hardware units that can be used to build a design (typically using Xilinx XPS tool).
Currently there is only one board description available because it was the target of the rgbproc repository development.
Xilinx ML506 with video
The board is derived from original Xilinx board description for ML506 board. It is extended by connections to AD9980 and CH7301C codecs. For both of them an IO_TYPE is defined as VGA_IN and DVI_OUT (but CH7301C is capable of output VGA as well).
Processing cores (pcores)
The repository consists of many units that can be used to build a design for image/video processing. The backbone is the data bus called simply RGB that is used to pass data (typically) from VGA input to VGA/DVI output.
The most common units are described in the following text.
Unit is intended to transform incoming VGA (coming from AD9980 codec
in digital form) signal to the internal data bus called RGB. It
assumes (hardcoded) resolution 640x480 and the system is preset to
process data at 25 MHz. After several modifications (updating
constraints, changing internal constants of
rgb_in) it should be
able to process even greater resolutions at faster clock.
The major computation done in
rgb_in is determining of valid pixel
data. Thus it generates DE signal of RGB bus. All other signals
are simply passed through the unit.
Unit is intended to transform incoming RGB bus data to protocol used by CH7301C codec. The most important signal is DE flag that is passed to the codec unchanged.
The unit transforms the channels (R, G, B) to IDF0 encoding defined in CH7301C specification. The resulting data are then send to the codec in double data rate (DDR).
Unit can be used to introduce a delay in the pipeline or as an example unit. Eg. after few modifications it could be used as a simple buffer.
Unit splits the RGB bus to two independed RGB buses which can be processed in parallel.
Multiplexor on RGB bus. Selects one from two source lines that is passed to the output. The multiplexor control can be done over IPIF interface which can be connected to some PLBv46 endpoint provided by Xilinx.
When a request to changed to source line is made the multiplexor does not perform it immediately. Instead it waits for vertical synchronization to do it. So it should never damage any frame.
Buffer of one line of an RGB frame. It provides direct access to any number of its elements. It is intended to support filtering.
Constructs a sliding window that can be used by filters (currently supports
only 3x3 window size). It is connected to a number of
rgb_line_buff units to
get few pixels of every line. Output from the unit is k-dimensional RGB bus
where k is the size of window (3x3 = 9).
Unit that provides meta information to software over IPIF interface which can be connected to PLB bus and thus to MicroBlaze. Serves design id, design version, design name (four characters) and negation register to test the communication.