Skip to content
A hardware beatracker and tempo estimator
Verilog VHDL Python Shell Other
Branch: master
Clone or download
Fetching latest commit…
Cannot retrieve the latest commit at this time.
Permalink
Type Name Latest commit message Commit time
Failed to load latest commit information.
bsv
doc
fpga
pcb
ref
sim
sw
.gitignore
README.md

README.md

bt

bt is a hardware beatracker and tempo estimator that probabilistically tries to match a live input stream to one of many phase-locking metronomes.

For details on the project, check out my blog post and project proposal.

screenshot

You can’t perform that action at this time.