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[L1] Update to newest ref manual (more irqs, more registers)

Initial L1 support was done against ref manual rev4.  rev6 adds more
registers and memory map sections.  This commit fills in the RCC definitions,
and adds the new interrupts for medium+ and high density devices.
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1 parent 523943a commit 9d64cd115b4d9c14ec85474069a36b1cd68fcca6 @karlp committed Nov 18, 2012
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19 include/libopencm3/stm32/l1/irq.yaml
@@ -4,8 +4,8 @@ partname_doxygen: STM32L1
irqs:
- wwdg
- pvd
- - tamper
- - rtc
+ - tamper_stamp
+ - rtc_wkup
- flash
- rcc
- exti0
@@ -44,6 +44,19 @@ irqs:
- usart3
- exti15_10
- rtc_alarm
- - usb_wakeup
+ - usb_fs_wakeup
- tim6
- tim7
+ # below here is medium+/high density
+ - sdio
+ - tim5
+ - spi3
+ - uart4
+ - uart5
+ - dma2_ch1
+ - dma2_ch2
+ - dma2_ch3
+ - dma2_ch4
+ - dma2_ch5
+ - aes
+ - comp_acq
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7 include/libopencm3/stm32/l1/memorymap.h
@@ -47,7 +47,6 @@
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
-// datasheet has an error? here
#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
@@ -61,6 +60,7 @@
/* gap */
#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
+#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7c5c)
#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00)
#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04)
@@ -85,13 +85,16 @@
#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00)
#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000)
#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400)
+#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB + 0x01800)
+#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB + 0x01c00)
/* gap */
#define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
/* gap */
#define RCC_BASE (PERIPH_BASE_AHB + 0x03800)
#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00)
/* gap */
-#define DMA_BASE (PERIPH_BASE_AHB + 0x06000)
+#define DMA1_BASE (PERIPH_BASE_AHB + 0x06000)
+#define DMA2_BASE (PERIPH_BASE_AHB + 0x04000)
/* PPIB */
#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
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33 include/libopencm3/stm32/l1/rcc.h
@@ -82,11 +82,31 @@ LGPL License Terms @ref lgpl_license
#define RCC_CR_RTCPRE_DIV2 0
#define RCC_CR_RTCPRE_DIV4 1
#define RCC_CR_RTCPRE_DIV8 2
-#define RCC_CR_RTCPRE_DIV18 3
+#define RCC_CR_RTCPRE_DIV16 3
+#define RCC_CR_RTCPRE_SHIFT 29
+#define RCC_CR_RTCPRE_MASK 0x3
/* --- RCC_ICSCR values ---------------------------------------------------- */
-// TODO
+#define RCC_ICSCR_MSITRIM_SHIFT 24
+#define RCC_ICSCR_MSITRIM_MASK 0xff
+#define RCC_ICSCR_MSICAL_SHIFT 16
+#define RCC_ICSCR_MSICAL_MASK 0xff
+
+#define RCC_ICSCR_MSIRANGE_SHIFT 13
+#define RCC_ICSCR_MSIRANGE_MASK 0x7
+#define RCC_ICSCR_MSIRANGE_65KHZ 0x0
+#define RCC_ICSCR_MSIRANGE_131KHZ 0x1
+#define RCC_ICSCR_MSIRANGE_262KHZ 0x2
+#define RCC_ICSCR_MSIRANGE_524KHZ 0x3
+#define RCC_ICSCR_MSIRANGE_1MHZ 0x4
+#define RCC_ICSCR_MSIRANGE_2MHZ 0x5
+#define RCC_ICSCR_MSIRANGE_4MHZ 0x6
+
+#define RCC_ICSCR_HSITRIM_SHIFT 8
+#define RCC_ICSCR_HSITRIM_MASK 0x1f
+#define RCC_ICSCR_HSICAL_SHIFT 0
+#define RCC_ICSCR_HSICAL_MASK 0xff
/* --- RCC_CFGR values ----------------------------------------------------- */
@@ -347,7 +367,14 @@ LGPL License Terms @ref lgpl_license
#define RCC_CSR_RMVF (1 << 24)
#define RCC_CSR_RTCRST (1 << 23)
#define RCC_CSR_RTCEN (1 << 22)
-/* RTCSEL[1:0] */
+#define RTC_CSR_RTCSEL_SHIFT (1 << 16)
+#define RTC_CSR_RTCSEL_MASK (0x3)
+#define RTC_CSR_RTCSEL_NONE (0x0)
+#define RTC_CSR_RTCSEL_LSE (0x1)
+#define RTC_CSR_RTCSEL_LSI (0x2)
+#define RTC_CSR_RTCSEL_HSI (0x3)
+#define RCC_CSR_LSECSSD (1 << 12)
+#define RCC_CSR_LSECSSON (1 << 11)
#define RCC_CSR_LSEBYP (1 << 10)
#define RCC_CSR_LSERDY (1 << 9)
#define RCC_CSR_LSEON (1 << 8)

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