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[L1] Update to newest ref manual (more irqs, more registers)

Initial L1 support was done against ref manual rev4.  rev6 adds more
registers and memory map sections.  This commit fills in the RCC definitions,
and adds the new interrupts for medium+ and high density devices.
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commit 9d64cd115b4d9c14ec85474069a36b1cd68fcca6 1 parent 523943a
Karl Palsson authored
19 include/libopencm3/stm32/l1/irq.yaml
@@ -4,8 +4,8 @@ partname_doxygen: STM32L1
4 4 irqs:
5 5 - wwdg
6 6 - pvd
7   - - tamper
8   - - rtc
  7 + - tamper_stamp
  8 + - rtc_wkup
9 9 - flash
10 10 - rcc
11 11 - exti0
@@ -44,6 +44,19 @@ irqs:
44 44 - usart3
45 45 - exti15_10
46 46 - rtc_alarm
47   - - usb_wakeup
  47 + - usb_fs_wakeup
48 48 - tim6
49 49 - tim7
  50 + # below here is medium+/high density
  51 + - sdio
  52 + - tim5
  53 + - spi3
  54 + - uart4
  55 + - uart5
  56 + - dma2_ch1
  57 + - dma2_ch2
  58 + - dma2_ch3
  59 + - dma2_ch4
  60 + - dma2_ch5
  61 + - aes
  62 + - comp_acq
7 include/libopencm3/stm32/l1/memorymap.h
@@ -47,7 +47,6 @@
47 47 #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
48 48 /* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
49 49 #define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
50   -// datasheet has an error? here
51 50 #define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
52 51 /* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
53 52 #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
@@ -61,6 +60,7 @@
61 60 /* gap */
62 61 #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
63 62 #define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
  63 +#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7c5c)
64 64 #define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00)
65 65 #define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04)
66 66
@@ -85,13 +85,16 @@
85 85 #define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00)
86 86 #define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000)
87 87 #define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400)
  88 +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB + 0x01800)
  89 +#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB + 0x01c00)
88 90 /* gap */
89 91 #define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
90 92 /* gap */
91 93 #define RCC_BASE (PERIPH_BASE_AHB + 0x03800)
92 94 #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00)
93 95 /* gap */
94   -#define DMA_BASE (PERIPH_BASE_AHB + 0x06000)
  96 +#define DMA1_BASE (PERIPH_BASE_AHB + 0x06000)
  97 +#define DMA2_BASE (PERIPH_BASE_AHB + 0x04000)
95 98
96 99 /* PPIB */
97 100 #define DBGMCU_BASE (PPBI_BASE + 0x00042000)
33 include/libopencm3/stm32/l1/rcc.h
@@ -82,11 +82,31 @@ LGPL License Terms @ref lgpl_license
82 82 #define RCC_CR_RTCPRE_DIV2 0
83 83 #define RCC_CR_RTCPRE_DIV4 1
84 84 #define RCC_CR_RTCPRE_DIV8 2
85   -#define RCC_CR_RTCPRE_DIV18 3
  85 +#define RCC_CR_RTCPRE_DIV16 3
  86 +#define RCC_CR_RTCPRE_SHIFT 29
  87 +#define RCC_CR_RTCPRE_MASK 0x3
86 88
87 89 /* --- RCC_ICSCR values ---------------------------------------------------- */
88 90
89   -// TODO
  91 +#define RCC_ICSCR_MSITRIM_SHIFT 24
  92 +#define RCC_ICSCR_MSITRIM_MASK 0xff
  93 +#define RCC_ICSCR_MSICAL_SHIFT 16
  94 +#define RCC_ICSCR_MSICAL_MASK 0xff
  95 +
  96 +#define RCC_ICSCR_MSIRANGE_SHIFT 13
  97 +#define RCC_ICSCR_MSIRANGE_MASK 0x7
  98 +#define RCC_ICSCR_MSIRANGE_65KHZ 0x0
  99 +#define RCC_ICSCR_MSIRANGE_131KHZ 0x1
  100 +#define RCC_ICSCR_MSIRANGE_262KHZ 0x2
  101 +#define RCC_ICSCR_MSIRANGE_524KHZ 0x3
  102 +#define RCC_ICSCR_MSIRANGE_1MHZ 0x4
  103 +#define RCC_ICSCR_MSIRANGE_2MHZ 0x5
  104 +#define RCC_ICSCR_MSIRANGE_4MHZ 0x6
  105 +
  106 +#define RCC_ICSCR_HSITRIM_SHIFT 8
  107 +#define RCC_ICSCR_HSITRIM_MASK 0x1f
  108 +#define RCC_ICSCR_HSICAL_SHIFT 0
  109 +#define RCC_ICSCR_HSICAL_MASK 0xff
90 110
91 111 /* --- RCC_CFGR values ----------------------------------------------------- */
92 112
@@ -347,7 +367,14 @@ LGPL License Terms @ref lgpl_license
347 367 #define RCC_CSR_RMVF (1 << 24)
348 368 #define RCC_CSR_RTCRST (1 << 23)
349 369 #define RCC_CSR_RTCEN (1 << 22)
350   -/* RTCSEL[1:0] */
  370 +#define RTC_CSR_RTCSEL_SHIFT (1 << 16)
  371 +#define RTC_CSR_RTCSEL_MASK (0x3)
  372 +#define RTC_CSR_RTCSEL_NONE (0x0)
  373 +#define RTC_CSR_RTCSEL_LSE (0x1)
  374 +#define RTC_CSR_RTCSEL_LSI (0x2)
  375 +#define RTC_CSR_RTCSEL_HSI (0x3)
  376 +#define RCC_CSR_LSECSSD (1 << 12)
  377 +#define RCC_CSR_LSECSSON (1 << 11)
351 378 #define RCC_CSR_LSEBYP (1 << 10)
352 379 #define RCC_CSR_LSERDY (1 << 9)
353 380 #define RCC_CSR_LSEON (1 << 8)

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