Skip to content
View kausshhk's full-sized avatar

Block or report kausshhk

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. COD-Lab COD-Lab Public

    Forked from alfadelta10010/COD-Lab

    Instructions & Assignments for COD Lab - UE22EC352A

    SystemVerilog

  2. risced risced Public

    Single - Cycle RV32 core.

    SystemVerilog

  3. RCA RCA Public

    Ripple Carry Adder using system verilog.

    HTML

  4. Gray_code_verification Gray_code_verification Public

    Designed a layered testbench as a part of the course - Verification Of Digital Systems (UE22EC343AB1)

    SystemVerilog

  5. LFSR LFSR Public

    Linear Feedback Shift Register - Buil in Self Test

    Verilog

  6. ARM-LPC ARM-LPC Public

    ARM_LPC1768 microcontroller programs using embedded - C

    C