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b21afc4 Nov 26, 2014
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/*
** ###################################################################
** Processors: MK20DX64VLH7
** MK20DX128VLH7
** MK20DX256VLH7
** MK20DX64VLK7
** MK20DX128VLK7
** MK20DX256VLK7
** MK20DX128VLL7
** MK20DX256VLL7
** MK20DX64VMB7
** MK20DX128VMB7
** MK20DX256VMB7
** MK20DX128VML7
** MK20DX256VML7
**
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: K20P144M72SF1RM Rev. 0, Nov 2011
** Version: rev. 1.4, 2013-06-24
**
** Abstract:
** This header file implements peripheral memory map for MK20D7
** processor.
**
** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2012-01-15)
** Initial public version.
** - rev. 1.1 (2012-02-13)
** SysTick peripheral added.
** - rev. 1.2 (2012-04-13)
** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR.
** Added new #define symbols <peripheralType>_BASE_PTRS.
** - rev. 1.3 (2013-04-05)
** Changed start of doxygen comment.
** - rev. 1.4 (2013-06-24)
** NV_FOPT register - NMI_DIS bit added.
**
** ###################################################################
*/
/*!
* @file MK20D7.h
* @version 1.4
* @date 2013-06-24
* @brief Peripheral memory map for MK20D7
*
* This header file implements peripheral memory map for MK20D7 processor.
*/
/* ----------------------------------------------------------------------------
-- MCU activation
---------------------------------------------------------------------------- */
/* Prevention from multiple including the same memory map */
#if !defined(MCU_MK20D7) /* Check if memory map has not been already included */
#define MCU_MK20D7
/* Check if another memory map has not been also included */
#if (defined(MCU_ACTIVE))
#error MK20D7 memory map: There is already included another memory map. Only one memory map can be included.
#endif /* (defined(MCU_ACTIVE)) */
#define MCU_ACTIVE
#include <stdint.h>
/** Memory map major version (memory maps with equal major version number are
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0100u
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0004u
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
typedef enum {
INT_Initial_Stack_Pointer = 0, /**< Initial stack pointer */
INT_Initial_Program_Counter = 1, /**< Initial program counter */
INT_NMI = 2, /**< Non-maskable interrupt */
INT_Hard_Fault = 3, /**< Hard fault exception */
INT_Mem_Manage_Fault = 4, /**< Memory Manage Fault */
INT_Bus_Fault = 5, /**< Bus fault exception */
INT_Usage_Fault = 6, /**< Usage fault exception */
INT_Reserved7 = 7, /**< Reserved interrupt 7 */
INT_Reserved8 = 8, /**< Reserved interrupt 8 */
INT_Reserved9 = 9, /**< Reserved interrupt 9 */
INT_Reserved10 = 10, /**< Reserved interrupt 10 */
INT_SVCall = 11, /**< A supervisor call exception */
INT_DebugMonitor = 12, /**< Debug Monitor */
INT_Reserved13 = 13, /**< Reserved interrupt 13 */
INT_PendableSrvReq = 14, /**< PendSV exception - request for system level service */
INT_SysTick = 15, /**< SysTick Interrupt */
INT_DMA0 = 16, /**< DMA Channel 0 Transfer Complete */
INT_DMA1 = 17, /**< DMA Channel 1 Transfer Complete */
INT_DMA2 = 18, /**< DMA Channel 2 Transfer Complete */
INT_DMA3 = 19, /**< DMA Channel 3 Transfer Complete */
INT_DMA4 = 20, /**< DMA Channel 4 Transfer Complete */
INT_DMA5 = 21, /**< DMA Channel 5 Transfer Complete */
INT_DMA6 = 22, /**< DMA Channel 6 Transfer Complete */
INT_DMA7 = 23, /**< DMA Channel 7 Transfer Complete */
INT_DMA8 = 24, /**< DMA Channel 8 Transfer Complete */
INT_DMA9 = 25, /**< DMA Channel 9 Transfer Complete */
INT_DMA10 = 26, /**< DMA Channel 10 Transfer Complete */
INT_DMA11 = 27, /**< DMA Channel 11 Transfer Complete */
INT_DMA12 = 28, /**< DMA Channel 12 Transfer Complete */
INT_DMA13 = 29, /**< DMA Channel 13 Transfer Complete */
INT_DMA14 = 30, /**< DMA Channel 14 Transfer Complete */
INT_DMA15 = 31, /**< DMA Channel 15 Transfer Complete */
INT_DMA_Error = 32, /**< DMA Error Interrupt */
INT_MCM = 33, /**< Normal interrupt */
INT_FTFL = 34, /**< FTFL Interrupt */
INT_Read_Collision = 35, /**< Read Collision Interrupt */
INT_LVD_LVW = 36, /**< Low Voltage Detect, Low Voltage Warning */
INT_LLW = 37, /**< Low Leakage Wakeup */
INT_Watchdog = 38, /**< WDOG Interrupt */
INT_Reserved39 = 39, /**< Reserved Interrupt 39 */
INT_I2C0 = 40, /**< I2C0 interrupt */
INT_I2C1 = 41, /**< I2C1 interrupt */
INT_SPI0 = 42, /**< SPI0 Interrupt */
INT_SPI1 = 43, /**< SPI1 Interrupt */
INT_Reserved44 = 44, /**< Reserved interrupt 44 */
INT_CAN0_ORed_Message_buffer = 45, /**< CAN0 OR'd Message Buffers Interrupt */
INT_CAN0_Bus_Off = 46, /**< CAN0 Bus Off Interrupt */
INT_CAN0_Error = 47, /**< CAN0 Error Interrupt */
INT_CAN0_Tx_Warning = 48, /**< CAN0 Tx Warning Interrupt */
INT_CAN0_Rx_Warning = 49, /**< CAN0 Rx Warning Interrupt */
INT_CAN0_Wake_Up = 50, /**< CAN0 Wake Up Interrupt */
INT_I2S0_Tx = 51, /**< I2S0 transmit interrupt */
INT_I2S0_Rx = 52, /**< I2S0 receive interrupt */
INT_Reserved53 = 53, /**< Reserved interrupt 53 */
INT_Reserved54 = 54, /**< Reserved interrupt 54 */
INT_Reserved55 = 55, /**< Reserved interrupt 55 */
INT_Reserved56 = 56, /**< Reserved interrupt 56 */
INT_Reserved57 = 57, /**< Reserved interrupt 57 */
INT_Reserved58 = 58, /**< Reserved interrupt 58 */
INT_Reserved59 = 59, /**< Reserved interrupt 59 */
INT_UART0_LON = 60, /**< UART0 LON interrupt */
INT_UART0_RX_TX = 61, /**< UART0 Receive/Transmit interrupt */
INT_UART0_ERR = 62, /**< UART0 Error interrupt */
INT_UART1_RX_TX = 63, /**< UART1 Receive/Transmit interrupt */
INT_UART1_ERR = 64, /**< UART1 Error interrupt */
INT_UART2_RX_TX = 65, /**< UART2 Receive/Transmit interrupt */
INT_UART2_ERR = 66, /**< UART2 Error interrupt */
INT_UART3_RX_TX = 67, /**< UART3 Receive/Transmit interrupt */
INT_UART3_ERR = 68, /**< UART3 Error interrupt */
INT_UART4_RX_TX = 69, /**< UART4 Receive/Transmit interrupt */
INT_UART4_ERR = 70, /**< UART4 Error interrupt */
INT_Reserved71 = 71, /**< Reserved interrupt 71 */
INT_Reserved72 = 72, /**< Reserved interrupt 72 */
INT_ADC0 = 73, /**< ADC0 interrupt */
INT_ADC1 = 74, /**< ADC1 interrupt */
INT_CMP0 = 75, /**< CMP0 interrupt */
INT_CMP1 = 76, /**< CMP1 interrupt */
INT_CMP2 = 77, /**< CMP2 interrupt */
INT_FTM0 = 78, /**< FTM0 fault, overflow and channels interrupt */
INT_FTM1 = 79, /**< FTM1 fault, overflow and channels interrupt */
INT_FTM2 = 80, /**< FTM2 fault, overflow and channels interrupt */
INT_CMT = 81, /**< CMT interrupt */
INT_RTC = 82, /**< RTC interrupt */
INT_RTC_Seconds = 83, /**< RTC seconds interrupt */
INT_PIT0 = 84, /**< PIT timer channel 0 interrupt */
INT_PIT1 = 85, /**< PIT timer channel 1 interrupt */
INT_PIT2 = 86, /**< PIT timer channel 2 interrupt */
INT_PIT3 = 87, /**< PIT timer channel 3 interrupt */
INT_PDB0 = 88, /**< PDB0 Interrupt */
INT_USB0 = 89, /**< USB0 interrupt */
INT_USBDCD = 90, /**< USBDCD Interrupt */
INT_Reserved91 = 91, /**< Reserved interrupt 91 */
INT_Reserved92 = 92, /**< Reserved interrupt 92 */
INT_Reserved93 = 93, /**< Reserved interrupt 93 */
INT_Reserved94 = 94, /**< Reserved interrupt 94 */
INT_Reserved95 = 95, /**< Reserved interrupt 95 */
INT_Reserved96 = 96, /**< Reserved interrupt 96 */
INT_DAC0 = 97, /**< DAC0 interrupt */
INT_Reserved98 = 98, /**< Reserved interrupt 98 */
INT_TSI0 = 99, /**< TSI0 Interrupt */
INT_MCG = 100, /**< MCG Interrupt */
INT_LPTimer = 101, /**< LPTimer interrupt */
INT_Reserved102 = 102, /**< Reserved interrupt 102 */
INT_PORTA = 103, /**< Port A interrupt */
INT_PORTB = 104, /**< Port B interrupt */
INT_PORTC = 105, /**< Port C interrupt */
INT_PORTD = 106, /**< Port D interrupt */
INT_PORTE = 107, /**< Port E interrupt */
INT_Reserved108 = 108, /**< Reserved interrupt 108 */
INT_Reserved109 = 109, /**< Reserved interrupt 109 */
INT_SWI = 110 /**< Software interrupt */
} IRQInterruptIndex;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Peripheral type defines
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_defines Peripheral type defines
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Peripheral ADC
* @{
*/
/** ADC - Peripheral register structure */
typedef struct ADC_MemMap {
uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
uint32_t CV1; /**< Compare value registers, offset: 0x18 */
uint32_t CV2; /**< Compare value registers, offset: 0x1C */
uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
uint32_t PGA; /**< ADC PGA register, offset: 0x50 */
uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
} volatile *ADC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register accessors */
#define ADC_SC1_REG(base,index) ((base)->SC1[index])
#define ADC_CFG1_REG(base) ((base)->CFG1)
#define ADC_CFG2_REG(base) ((base)->CFG2)
#define ADC_R_REG(base,index) ((base)->R[index])
#define ADC_CV1_REG(base) ((base)->CV1)
#define ADC_CV2_REG(base) ((base)->CV2)
#define ADC_SC2_REG(base) ((base)->SC2)
#define ADC_SC3_REG(base) ((base)->SC3)
#define ADC_OFS_REG(base) ((base)->OFS)
#define ADC_PG_REG(base) ((base)->PG)
#define ADC_MG_REG(base) ((base)->MG)
#define ADC_CLPD_REG(base) ((base)->CLPD)
#define ADC_CLPS_REG(base) ((base)->CLPS)
#define ADC_CLP4_REG(base) ((base)->CLP4)
#define ADC_CLP3_REG(base) ((base)->CLP3)
#define ADC_CLP2_REG(base) ((base)->CLP2)
#define ADC_CLP1_REG(base) ((base)->CLP1)
#define ADC_CLP0_REG(base) ((base)->CLP0)
#define ADC_PGA_REG(base) ((base)->PGA)
#define ADC_CLMD_REG(base) ((base)->CLMD)
#define ADC_CLMS_REG(base) ((base)->CLMS)
#define ADC_CLM4_REG(base) ((base)->CLM4)
#define ADC_CLM3_REG(base) ((base)->CLM3)
#define ADC_CLM2_REG(base) ((base)->CLM2)
#define ADC_CLM1_REG(base) ((base)->CLM1)
#define ADC_CLM0_REG(base) ((base)->CLM0)
/*!
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/* SC1 Bit Fields */
#define ADC_SC1_ADCH_MASK 0x1Fu
#define ADC_SC1_ADCH_SHIFT 0
#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
#define ADC_SC1_DIFF_MASK 0x20u
#define ADC_SC1_DIFF_SHIFT 5
#define ADC_SC1_AIEN_MASK 0x40u
#define ADC_SC1_AIEN_SHIFT 6
#define ADC_SC1_COCO_MASK 0x80u
#define ADC_SC1_COCO_SHIFT 7
/* CFG1 Bit Fields */
#define ADC_CFG1_ADICLK_MASK 0x3u
#define ADC_CFG1_ADICLK_SHIFT 0
#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
#define ADC_CFG1_MODE_MASK 0xCu
#define ADC_CFG1_MODE_SHIFT 2
#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
#define ADC_CFG1_ADLSMP_MASK 0x10u
#define ADC_CFG1_ADLSMP_SHIFT 4
#define ADC_CFG1_ADIV_MASK 0x60u
#define ADC_CFG1_ADIV_SHIFT 5
#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
#define ADC_CFG1_ADLPC_MASK 0x80u
#define ADC_CFG1_ADLPC_SHIFT 7
/* CFG2 Bit Fields */
#define ADC_CFG2_ADLSTS_MASK 0x3u
#define ADC_CFG2_ADLSTS_SHIFT 0
#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
#define ADC_CFG2_ADHSC_MASK 0x4u
#define ADC_CFG2_ADHSC_SHIFT 2
#define ADC_CFG2_ADACKEN_MASK 0x8u
#define ADC_CFG2_ADACKEN_SHIFT 3
#define ADC_CFG2_MUXSEL_MASK 0x10u
#define ADC_CFG2_MUXSEL_SHIFT 4
/* R Bit Fields */
#define ADC_R_D_MASK 0xFFFFu
#define ADC_R_D_SHIFT 0
#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
/* CV1 Bit Fields */
#define ADC_CV1_CV_MASK 0xFFFFu
#define ADC_CV1_CV_SHIFT 0
#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
/* CV2 Bit Fields */
#define ADC_CV2_CV_MASK 0xFFFFu
#define ADC_CV2_CV_SHIFT 0
#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
/* SC2 Bit Fields */
#define ADC_SC2_REFSEL_MASK 0x3u
#define ADC_SC2_REFSEL_SHIFT 0
#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
#define ADC_SC2_DMAEN_MASK 0x4u
#define ADC_SC2_DMAEN_SHIFT 2
#define ADC_SC2_ACREN_MASK 0x8u
#define ADC_SC2_ACREN_SHIFT 3
#define ADC_SC2_ACFGT_MASK 0x10u
#define ADC_SC2_ACFGT_SHIFT 4
#define ADC_SC2_ACFE_MASK 0x20u
#define ADC_SC2_ACFE_SHIFT 5
#define ADC_SC2_ADTRG_MASK 0x40u
#define ADC_SC2_ADTRG_SHIFT 6
#define ADC_SC2_ADACT_MASK 0x80u
#define ADC_SC2_ADACT_SHIFT 7
/* SC3 Bit Fields */
#define ADC_SC3_AVGS_MASK 0x3u
#define ADC_SC3_AVGS_SHIFT 0
#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
#define ADC_SC3_AVGE_MASK 0x4u
#define ADC_SC3_AVGE_SHIFT 2
#define ADC_SC3_ADCO_MASK 0x8u
#define ADC_SC3_ADCO_SHIFT 3
#define ADC_SC3_CALF_MASK 0x40u
#define ADC_SC3_CALF_SHIFT 6
#define ADC_SC3_CAL_MASK 0x80u
#define ADC_SC3_CAL_SHIFT 7
/* OFS Bit Fields */
#define ADC_OFS_OFS_MASK 0xFFFFu
#define ADC_OFS_OFS_SHIFT 0
#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
/* PG Bit Fields */
#define ADC_PG_PG_MASK 0xFFFFu
#define ADC_PG_PG_SHIFT 0
#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
/* MG Bit Fields */
#define ADC_MG_MG_MASK 0xFFFFu
#define ADC_MG_MG_SHIFT 0
#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
/* CLPD Bit Fields */
#define ADC_CLPD_CLPD_MASK 0x3Fu
#define ADC_CLPD_CLPD_SHIFT 0
#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
/* CLPS Bit Fields */
#define ADC_CLPS_CLPS_MASK 0x3Fu
#define ADC_CLPS_CLPS_SHIFT 0
#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
/* CLP4 Bit Fields */
#define ADC_CLP4_CLP4_MASK 0x3FFu
#define ADC_CLP4_CLP4_SHIFT 0
#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
/* CLP3 Bit Fields */
#define ADC_CLP3_CLP3_MASK 0x1FFu
#define ADC_CLP3_CLP3_SHIFT 0
#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
/* CLP2 Bit Fields */
#define ADC_CLP2_CLP2_MASK 0xFFu
#define ADC_CLP2_CLP2_SHIFT 0
#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
/* CLP1 Bit Fields */
#define ADC_CLP1_CLP1_MASK 0x7Fu
#define ADC_CLP1_CLP1_SHIFT 0
#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
/* CLP0 Bit Fields */
#define ADC_CLP0_CLP0_MASK 0x3Fu
#define ADC_CLP0_CLP0_SHIFT 0
#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
/* PGA Bit Fields */
#define ADC_PGA_PGAG_MASK 0xF0000u
#define ADC_PGA_PGAG_SHIFT 16
#define ADC_PGA_PGAG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PGA_PGAG_SHIFT))&ADC_PGA_PGAG_MASK)
#define ADC_PGA_PGALPb_MASK 0x100000u
#define ADC_PGA_PGALPb_SHIFT 20
#define ADC_PGA_PGAEN_MASK 0x800000u
#define ADC_PGA_PGAEN_SHIFT 23
/* CLMD Bit Fields */
#define ADC_CLMD_CLMD_MASK 0x3Fu
#define ADC_CLMD_CLMD_SHIFT 0
#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
/* CLMS Bit Fields */
#define ADC_CLMS_CLMS_MASK 0x3Fu
#define ADC_CLMS_CLMS_SHIFT 0
#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
/* CLM4 Bit Fields */
#define ADC_CLM4_CLM4_MASK 0x3FFu
#define ADC_CLM4_CLM4_SHIFT 0
#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
/* CLM3 Bit Fields */
#define ADC_CLM3_CLM3_MASK 0x1FFu
#define ADC_CLM3_CLM3_SHIFT 0
#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
/* CLM2 Bit Fields */
#define ADC_CLM2_CLM2_MASK 0xFFu
#define ADC_CLM2_CLM2_SHIFT 0
#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
/* CLM1 Bit Fields */
#define ADC_CLM1_CLM1_MASK 0x7Fu
#define ADC_CLM1_CLM1_SHIFT 0
#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
/* CLM0 Bit Fields */
#define ADC_CLM0_CLM0_MASK 0x3Fu
#define ADC_CLM0_CLM0_SHIFT 0
#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
/*!
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base pointer */
#define ADC0_BASE_PTR ((ADC_MemMapPtr)0x4003B000u)
/** Peripheral ADC1 base pointer */
#define ADC1_BASE_PTR ((ADC_MemMapPtr)0x400BB000u)
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS { ADC0_BASE_PTR, ADC1_BASE_PTR }
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
* @{
*/
/* ADC - Register instance definitions */
/* ADC0 */
#define ADC0_SC1A ADC_SC1_REG(ADC0_BASE_PTR,0)
#define ADC0_SC1B ADC_SC1_REG(ADC0_BASE_PTR,1)
#define ADC0_CFG1 ADC_CFG1_REG(ADC0_BASE_PTR)
#define ADC0_CFG2 ADC_CFG2_REG(ADC0_BASE_PTR)
#define ADC0_RA ADC_R_REG(ADC0_BASE_PTR,0)
#define ADC0_RB ADC_R_REG(ADC0_BASE_PTR,1)
#define ADC0_CV1 ADC_CV1_REG(ADC0_BASE_PTR)
#define ADC0_CV2 ADC_CV2_REG(ADC0_BASE_PTR)
#define ADC0_SC2 ADC_SC2_REG(ADC0_BASE_PTR)
#define ADC0_SC3 ADC_SC3_REG(ADC0_BASE_PTR)
#define ADC0_OFS ADC_OFS_REG(ADC0_BASE_PTR)
#define ADC0_PG ADC_PG_REG(ADC0_BASE_PTR)
#define ADC0_MG ADC_MG_REG(ADC0_BASE_PTR)
#define ADC0_CLPD ADC_CLPD_REG(ADC0_BASE_PTR)
#define ADC0_CLPS ADC_CLPS_REG(ADC0_BASE_PTR)
#define ADC0_CLP4 ADC_CLP4_REG(ADC0_BASE_PTR)
#define ADC0_CLP3 ADC_CLP3_REG(ADC0_BASE_PTR)
#define ADC0_CLP2 ADC_CLP2_REG(ADC0_BASE_PTR)
#define ADC0_CLP1 ADC_CLP1_REG(ADC0_BASE_PTR)
#define ADC0_CLP0 ADC_CLP0_REG(ADC0_BASE_PTR)
#define ADC0_PGA ADC_PGA_REG(ADC0_BASE_PTR)
#define ADC0_CLMD ADC_CLMD_REG(ADC0_BASE_PTR)
#define ADC0_CLMS ADC_CLMS_REG(ADC0_BASE_PTR)
#define ADC0_CLM4 ADC_CLM4_REG(ADC0_BASE_PTR)
#define ADC0_CLM3 ADC_CLM3_REG(ADC0_BASE_PTR)
#define ADC0_CLM2 ADC_CLM2_REG(ADC0_BASE_PTR)
#define ADC0_CLM1 ADC_CLM1_REG(ADC0_BASE_PTR)
#define ADC0_CLM0 ADC_CLM0_REG(ADC0_BASE_PTR)
/* ADC1 */
#define ADC1_SC1A ADC_SC1_REG(ADC1_BASE_PTR,0)
#define ADC1_SC1B ADC_SC1_REG(ADC1_BASE_PTR,1)
#define ADC1_CFG1 ADC_CFG1_REG(ADC1_BASE_PTR)
#define ADC1_CFG2 ADC_CFG2_REG(ADC1_BASE_PTR)
#define ADC1_RA ADC_R_REG(ADC1_BASE_PTR,0)
#define ADC1_RB ADC_R_REG(ADC1_BASE_PTR,1)
#define ADC1_CV1 ADC_CV1_REG(ADC1_BASE_PTR)
#define ADC1_CV2 ADC_CV2_REG(ADC1_BASE_PTR)
#define ADC1_SC2 ADC_SC2_REG(ADC1_BASE_PTR)
#define ADC1_SC3 ADC_SC3_REG(ADC1_BASE_PTR)
#define ADC1_OFS ADC_OFS_REG(ADC1_BASE_PTR)
#define ADC1_PG ADC_PG_REG(ADC1_BASE_PTR)
#define ADC1_MG ADC_MG_REG(ADC1_BASE_PTR)
#define ADC1_CLPD ADC_CLPD_REG(ADC1_BASE_PTR)
#define ADC1_CLPS ADC_CLPS_REG(ADC1_BASE_PTR)
#define ADC1_CLP4 ADC_CLP4_REG(ADC1_BASE_PTR)
#define ADC1_CLP3 ADC_CLP3_REG(ADC1_BASE_PTR)
#define ADC1_CLP2 ADC_CLP2_REG(ADC1_BASE_PTR)
#define ADC1_CLP1 ADC_CLP1_REG(ADC1_BASE_PTR)
#define ADC1_CLP0 ADC_CLP0_REG(ADC1_BASE_PTR)
#define ADC1_PGA ADC_PGA_REG(ADC1_BASE_PTR)
#define ADC1_CLMD ADC_CLMD_REG(ADC1_BASE_PTR)
#define ADC1_CLMS ADC_CLMS_REG(ADC1_BASE_PTR)
#define ADC1_CLM4 ADC_CLM4_REG(ADC1_BASE_PTR)
#define ADC1_CLM3 ADC_CLM3_REG(ADC1_BASE_PTR)
#define ADC1_CLM2 ADC_CLM2_REG(ADC1_BASE_PTR)
#define ADC1_CLM1 ADC_CLM1_REG(ADC1_BASE_PTR)
#define ADC1_CLM0 ADC_CLM0_REG(ADC1_BASE_PTR)
/* ADC - Register array accessors */
#define ADC0_SC1(index) ADC_SC1_REG(ADC0_BASE_PTR,index)
#define ADC1_SC1(index) ADC_SC1_REG(ADC1_BASE_PTR,index)
#define ADC0_R(index) ADC_R_REG(ADC0_BASE_PTR,index)
#define ADC1_R(index) ADC_R_REG(ADC1_BASE_PTR,index)
/*!
* @}
*/ /* end of group ADC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group ADC_Peripheral */
/* ----------------------------------------------------------------------------
-- AIPS
---------------------------------------------------------------------------- */
/*!
* @addtogroup AIPS_Peripheral AIPS
* @{
*/
/** AIPS - Peripheral register structure */
typedef struct AIPS_MemMap {
uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
uint8_t RESERVED_0[28];
uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
uint8_t RESERVED_1[16];
uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
} volatile *AIPS_MemMapPtr;
/* ----------------------------------------------------------------------------
-- AIPS - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
* @{
*/
/* AIPS - Register accessors */
#define AIPS_MPRA_REG(base) ((base)->MPRA)
#define AIPS_PACRA_REG(base) ((base)->PACRA)
#define AIPS_PACRB_REG(base) ((base)->PACRB)
#define AIPS_PACRC_REG(base) ((base)->PACRC)
#define AIPS_PACRD_REG(base) ((base)->PACRD)
#define AIPS_PACRE_REG(base) ((base)->PACRE)
#define AIPS_PACRF_REG(base) ((base)->PACRF)
#define AIPS_PACRG_REG(base) ((base)->PACRG)
#define AIPS_PACRH_REG(base) ((base)->PACRH)
#define AIPS_PACRI_REG(base) ((base)->PACRI)
#define AIPS_PACRJ_REG(base) ((base)->PACRJ)
#define AIPS_PACRK_REG(base) ((base)->PACRK)
#define AIPS_PACRL_REG(base) ((base)->PACRL)
#define AIPS_PACRM_REG(base) ((base)->PACRM)
#define AIPS_PACRN_REG(base) ((base)->PACRN)
#define AIPS_PACRO_REG(base) ((base)->PACRO)
#define AIPS_PACRP_REG(base) ((base)->PACRP)
/*!
* @}
*/ /* end of group AIPS_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- AIPS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AIPS_Register_Masks AIPS Register Masks
* @{
*/
/* MPRA Bit Fields */
#define AIPS_MPRA_MPL3_MASK 0x10000u
#define AIPS_MPRA_MPL3_SHIFT 16
#define AIPS_MPRA_MTW3_MASK 0x20000u
#define AIPS_MPRA_MTW3_SHIFT 17
#define AIPS_MPRA_MTR3_MASK 0x40000u
#define AIPS_MPRA_MTR3_SHIFT 18
#define AIPS_MPRA_MPL2_MASK 0x100000u
#define AIPS_MPRA_MPL2_SHIFT 20
#define AIPS_MPRA_MTW2_MASK 0x200000u
#define AIPS_MPRA_MTW2_SHIFT 21
#define AIPS_MPRA_MTR2_MASK 0x400000u
#define AIPS_MPRA_MTR2_SHIFT 22
#define AIPS_MPRA_MPL1_MASK 0x1000000u
#define AIPS_MPRA_MPL1_SHIFT 24
#define AIPS_MPRA_MTW1_MASK 0x2000000u
#define AIPS_MPRA_MTW1_SHIFT 25
#define AIPS_MPRA_MTR1_MASK 0x4000000u
#define AIPS_MPRA_MTR1_SHIFT 26
#define AIPS_MPRA_MPL0_MASK 0x10000000u
#define AIPS_MPRA_MPL0_SHIFT 28
#define AIPS_MPRA_MTW0_MASK 0x20000000u
#define AIPS_MPRA_MTW0_SHIFT 29
#define AIPS_MPRA_MTR0_MASK 0x40000000u
#define AIPS_MPRA_MTR0_SHIFT 30
/* PACRA Bit Fields */
#define AIPS_PACRA_TP7_MASK 0x1u
#define AIPS_PACRA_TP7_SHIFT 0
#define AIPS_PACRA_WP7_MASK 0x2u
#define AIPS_PACRA_WP7_SHIFT 1
#define AIPS_PACRA_SP7_MASK 0x4u
#define AIPS_PACRA_SP7_SHIFT 2
#define AIPS_PACRA_TP6_MASK 0x10u
#define AIPS_PACRA_TP6_SHIFT 4
#define AIPS_PACRA_WP6_MASK 0x20u
#define AIPS_PACRA_WP6_SHIFT 5
#define AIPS_PACRA_SP6_MASK 0x40u
#define AIPS_PACRA_SP6_SHIFT 6
#define AIPS_PACRA_TP5_MASK 0x100u
#define AIPS_PACRA_TP5_SHIFT 8
#define AIPS_PACRA_WP5_MASK 0x200u
#define AIPS_PACRA_WP5_SHIFT 9
#define AIPS_PACRA_SP5_MASK 0x400u
#define AIPS_PACRA_SP5_SHIFT 10
#define AIPS_PACRA_TP4_MASK 0x1000u
#define AIPS_PACRA_TP4_SHIFT 12
#define AIPS_PACRA_WP4_MASK 0x2000u
#define AIPS_PACRA_WP4_SHIFT 13
#define AIPS_PACRA_SP4_MASK 0x4000u
#define AIPS_PACRA_SP4_SHIFT 14
#define AIPS_PACRA_TP3_MASK 0x10000u
#define AIPS_PACRA_TP3_SHIFT 16
#define AIPS_PACRA_WP3_MASK 0x20000u
#define AIPS_PACRA_WP3_SHIFT 17
#define AIPS_PACRA_SP3_MASK 0x40000u
#define AIPS_PACRA_SP3_SHIFT 18
#define AIPS_PACRA_TP2_MASK 0x100000u
#define AIPS_PACRA_TP2_SHIFT 20
#define AIPS_PACRA_WP2_MASK 0x200000u
#define AIPS_PACRA_WP2_SHIFT 21
#define AIPS_PACRA_SP2_MASK 0x400000u
#define AIPS_PACRA_SP2_SHIFT 22
#define AIPS_PACRA_TP1_MASK 0x1000000u
#define AIPS_PACRA_TP1_SHIFT 24
#define AIPS_PACRA_WP1_MASK 0x2000000u
#define AIPS_PACRA_WP1_SHIFT 25
#define AIPS_PACRA_SP1_MASK 0x4000000u
#define AIPS_PACRA_SP1_SHIFT 26
#define AIPS_PACRA_TP0_MASK 0x10000000u
#define AIPS_PACRA_TP0_SHIFT 28
#define AIPS_PACRA_WP0_MASK 0x20000000u
#define AIPS_PACRA_WP0_SHIFT 29
#define AIPS_PACRA_SP0_MASK 0x40000000u
#define AIPS_PACRA_SP0_SHIFT 30
/* PACRB Bit Fields */
#define AIPS_PACRB_TP7_MASK 0x1u
#define AIPS_PACRB_TP7_SHIFT 0
#define AIPS_PACRB_WP7_MASK 0x2u
#define AIPS_PACRB_WP7_SHIFT 1
#define AIPS_PACRB_SP7_MASK 0x4u
#define AIPS_PACRB_SP7_SHIFT 2
#define AIPS_PACRB_TP6_MASK 0x10u
#define AIPS_PACRB_TP6_SHIFT 4
#define AIPS_PACRB_WP6_MASK 0x20u
#define AIPS_PACRB_WP6_SHIFT 5
#define AIPS_PACRB_SP6_MASK 0x40u
#define AIPS_PACRB_SP6_SHIFT 6
#define AIPS_PACRB_TP5_MASK 0x100u
#define AIPS_PACRB_TP5_SHIFT 8
#define AIPS_PACRB_WP5_MASK 0x200u
#define AIPS_PACRB_WP5_SHIFT 9
#define AIPS_PACRB_SP5_MASK 0x400u
#define AIPS_PACRB_SP5_SHIFT 10
#define AIPS_PACRB_TP4_MASK 0x1000u
#define AIPS_PACRB_TP4_SHIFT 12
#define AIPS_PACRB_WP4_MASK 0x2000u
#define AIPS_PACRB_WP4_SHIFT 13
#define AIPS_PACRB_SP4_MASK 0x4000u
#define AIPS_PACRB_SP4_SHIFT 14
#define AIPS_PACRB_TP3_MASK 0x10000u
#define AIPS_PACRB_TP3_SHIFT 16
#define AIPS_PACRB_WP3_MASK 0x20000u
#define AIPS_PACRB_WP3_SHIFT 17
#define AIPS_PACRB_SP3_MASK 0x40000u
#define AIPS_PACRB_SP3_SHIFT 18
#define AIPS_PACRB_TP2_MASK 0x100000u
#define AIPS_PACRB_TP2_SHIFT 20
#define AIPS_PACRB_WP2_MASK 0x200000u
#define AIPS_PACRB_WP2_SHIFT 21
#define AIPS_PACRB_SP2_MASK 0x400000u
#define AIPS_PACRB_SP2_SHIFT 22
#define AIPS_PACRB_TP1_MASK 0x1000000u
#define AIPS_PACRB_TP1_SHIFT 24
#define AIPS_PACRB_WP1_MASK 0x2000000u
#define AIPS_PACRB_WP1_SHIFT 25
#define AIPS_PACRB_SP1_MASK 0x4000000u
#define AIPS_PACRB_SP1_SHIFT 26
#define AIPS_PACRB_TP0_MASK 0x10000000u
#define AIPS_PACRB_TP0_SHIFT 28
#define AIPS_PACRB_WP0_MASK 0x20000000u
#define AIPS_PACRB_WP0_SHIFT 29
#define AIPS_PACRB_SP0_MASK 0x40000000u
#define AIPS_PACRB_SP0_SHIFT 30
/* PACRC Bit Fields */
#define AIPS_PACRC_TP7_MASK 0x1u
#define AIPS_PACRC_TP7_SHIFT 0
#define AIPS_PACRC_WP7_MASK 0x2u
#define AIPS_PACRC_WP7_SHIFT 1
#define AIPS_PACRC_SP7_MASK 0x4u
#define AIPS_PACRC_SP7_SHIFT 2
#define AIPS_PACRC_TP6_MASK 0x10u
#define AIPS_PACRC_TP6_SHIFT 4
#define AIPS_PACRC_WP6_MASK 0x20u
#define AIPS_PACRC_WP6_SHIFT 5
#define AIPS_PACRC_SP6_MASK 0x40u
#define AIPS_PACRC_SP6_SHIFT 6
#define AIPS_PACRC_TP5_MASK 0x100u
#define AIPS_PACRC_TP5_SHIFT 8
#define AIPS_PACRC_WP5_MASK 0x200u
#define AIPS_PACRC_WP5_SHIFT 9
#define AIPS_PACRC_SP5_MASK 0x400u
#define AIPS_PACRC_SP5_SHIFT 10
#define AIPS_PACRC_TP4_MASK 0x1000u
#define AIPS_PACRC_TP4_SHIFT 12
#define AIPS_PACRC_WP4_MASK 0x2000u
#define AIPS_PACRC_WP4_SHIFT 13
#define AIPS_PACRC_SP4_MASK 0x4000u
#define AIPS_PACRC_SP4_SHIFT 14
#define AIPS_PACRC_TP3_MASK 0x10000u
#define AIPS_PACRC_TP3_SHIFT 16
#define AIPS_PACRC_WP3_MASK 0x20000u
#define AIPS_PACRC_WP3_SHIFT 17
#define AIPS_PACRC_SP3_MASK 0x40000u
#define AIPS_PACRC_SP3_SHIFT 18
#define AIPS_PACRC_TP2_MASK 0x100000u
#define AIPS_PACRC_TP2_SHIFT 20
#define AIPS_PACRC_WP2_MASK 0x200000u
#define AIPS_PACRC_WP2_SHIFT 21
#define AIPS_PACRC_SP2_MASK 0x400000u
#define AIPS_PACRC_SP2_SHIFT 22
#define AIPS_PACRC_TP1_MASK 0x1000000u
#define AIPS_PACRC_TP1_SHIFT 24
#define AIPS_PACRC_WP1_MASK 0x2000000u
#define AIPS_PACRC_WP1_SHIFT 25
#define AIPS_PACRC_SP1_MASK 0x4000000u
#define AIPS_PACRC_SP1_SHIFT 26
#define AIPS_PACRC_TP0_MASK 0x10000000u
#define AIPS_PACRC_TP0_SHIFT 28
#define AIPS_PACRC_WP0_MASK 0x20000000u
#define AIPS_PACRC_WP0_SHIFT 29
#define AIPS_PACRC_SP0_MASK 0x40000000u
#define AIPS_PACRC_SP0_SHIFT 30
/* PACRD Bit Fields */
#define AIPS_PACRD_TP7_MASK 0x1u
#define AIPS_PACRD_TP7_SHIFT 0
#define AIPS_PACRD_WP7_MASK 0x2u
#define AIPS_PACRD_WP7_SHIFT 1
#define AIPS_PACRD_SP7_MASK 0x4u
#define AIPS_PACRD_SP7_SHIFT 2
#define AIPS_PACRD_TP6_MASK 0x10u
#define AIPS_PACRD_TP6_SHIFT 4
#define AIPS_PACRD_WP6_MASK 0x20u
#define AIPS_PACRD_WP6_SHIFT 5
#define AIPS_PACRD_SP6_MASK 0x40u
#define AIPS_PACRD_SP6_SHIFT 6
#define AIPS_PACRD_TP5_MASK 0x100u
#define AIPS_PACRD_TP5_SHIFT 8
#define AIPS_PACRD_WP5_MASK 0x200u
#define AIPS_PACRD_WP5_SHIFT 9
#define AIPS_PACRD_SP5_MASK 0x400u
#define AIPS_PACRD_SP5_SHIFT 10
#define AIPS_PACRD_TP4_MASK 0x1000u
#define AIPS_PACRD_TP4_SHIFT 12
#define AIPS_PACRD_WP4_MASK 0x2000u
#define AIPS_PACRD_WP4_SHIFT 13
#define AIPS_PACRD_SP4_MASK 0x4000u
#define AIPS_PACRD_SP4_SHIFT 14
#define AIPS_PACRD_TP3_MASK 0x10000u
#define AIPS_PACRD_TP3_SHIFT 16
#define AIPS_PACRD_WP3_MASK 0x20000u
#define AIPS_PACRD_WP3_SHIFT 17
#define AIPS_PACRD_SP3_MASK 0x40000u
#define AIPS_PACRD_SP3_SHIFT 18
#define AIPS_PACRD_TP2_MASK 0x100000u
#define AIPS_PACRD_TP2_SHIFT 20
#define AIPS_PACRD_WP2_MASK 0x200000u
#define AIPS_PACRD_WP2_SHIFT 21
#define AIPS_PACRD_SP2_MASK 0x400000u
#define AIPS_PACRD_SP2_SHIFT 22
#define AIPS_PACRD_TP1_MASK 0x1000000u
#define AIPS_PACRD_TP1_SHIFT 24
#define AIPS_PACRD_WP1_MASK 0x2000000u
#define AIPS_PACRD_WP1_SHIFT 25
#define AIPS_PACRD_SP1_MASK 0x4000000u
#define AIPS_PACRD_SP1_SHIFT 26
#define AIPS_PACRD_TP0_MASK 0x10000000u
#define AIPS_PACRD_TP0_SHIFT 28
#define AIPS_PACRD_WP0_MASK 0x20000000u
#define AIPS_PACRD_WP0_SHIFT 29
#define AIPS_PACRD_SP0_MASK 0x40000000u
#define AIPS_PACRD_SP0_SHIFT 30
/* PACRE Bit Fields */
#define AIPS_PACRE_TP7_MASK 0x1u
#define AIPS_PACRE_TP7_SHIFT 0
#define AIPS_PACRE_WP7_MASK 0x2u
#define AIPS_PACRE_WP7_SHIFT 1
#define AIPS_PACRE_SP7_MASK 0x4u
#define AIPS_PACRE_SP7_SHIFT 2
#define AIPS_PACRE_TP6_MASK 0x10u
#define AIPS_PACRE_TP6_SHIFT 4
#define AIPS_PACRE_WP6_MASK 0x20u
#define AIPS_PACRE_WP6_SHIFT 5
#define AIPS_PACRE_SP6_MASK 0x40u
#define AIPS_PACRE_SP6_SHIFT 6
#define AIPS_PACRE_TP5_MASK 0x100u
#define AIPS_PACRE_TP5_SHIFT 8
#define AIPS_PACRE_WP5_MASK 0x200u
#define AIPS_PACRE_WP5_SHIFT 9
#define AIPS_PACRE_SP5_MASK 0x400u
#define AIPS_PACRE_SP5_SHIFT 10
#define AIPS_PACRE_TP4_MASK 0x1000u
#define AIPS_PACRE_TP4_SHIFT 12
#define AIPS_PACRE_WP4_MASK 0x2000u
#define AIPS_PACRE_WP4_SHIFT 13
#define AIPS_PACRE_SP4_MASK 0x4000u
#define AIPS_PACRE_SP4_SHIFT 14
#define AIPS_PACRE_TP3_MASK 0x10000u
#define AIPS_PACRE_TP3_SHIFT 16
#define AIPS_PACRE_WP3_MASK 0x20000u
#define AIPS_PACRE_WP3_SHIFT 17
#define AIPS_PACRE_SP3_MASK 0x40000u
#define AIPS_PACRE_SP3_SHIFT 18
#define AIPS_PACRE_TP2_MASK 0x100000u
#define AIPS_PACRE_TP2_SHIFT 20
#define AIPS_PACRE_WP2_MASK 0x200000u
#define AIPS_PACRE_WP2_SHIFT 21
#define AIPS_PACRE_SP2_MASK 0x400000u
#define AIPS_PACRE_SP2_SHIFT 22
#define AIPS_PACRE_TP1_MASK 0x1000000u
#define AIPS_PACRE_TP1_SHIFT 24
#define AIPS_PACRE_WP1_MASK 0x2000000u
#define AIPS_PACRE_WP1_SHIFT 25
#define AIPS_PACRE_SP1_MASK 0x4000000u
#define AIPS_PACRE_SP1_SHIFT 26
#define AIPS_PACRE_TP0_MASK 0x10000000u
#define AIPS_PACRE_TP0_SHIFT 28
#define AIPS_PACRE_WP0_MASK 0x20000000u
#define AIPS_PACRE_WP0_SHIFT 29
#define AIPS_PACRE_SP0_MASK 0x40000000u
#define AIPS_PACRE_SP0_SHIFT 30
/* PACRF Bit Fields */
#define AIPS_PACRF_TP7_MASK 0x1u
#define AIPS_PACRF_TP7_SHIFT 0
#define AIPS_PACRF_WP7_MASK 0x2u
#define AIPS_PACRF_WP7_SHIFT 1
#define AIPS_PACRF_SP7_MASK 0x4u
#define AIPS_PACRF_SP7_SHIFT 2
#define AIPS_PACRF_TP6_MASK 0x10u
#define AIPS_PACRF_TP6_SHIFT 4
#define AIPS_PACRF_WP6_MASK 0x20u
#define AIPS_PACRF_WP6_SHIFT 5
#define AIPS_PACRF_SP6_MASK 0x40u
#define AIPS_PACRF_SP6_SHIFT 6
#define AIPS_PACRF_TP5_MASK 0x100u
#define AIPS_PACRF_TP5_SHIFT 8
#define AIPS_PACRF_WP5_MASK 0x200u
#define AIPS_PACRF_WP5_SHIFT 9
#define AIPS_PACRF_SP5_MASK 0x400u
#define AIPS_PACRF_SP5_SHIFT 10
#define AIPS_PACRF_TP4_MASK 0x1000u
#define AIPS_PACRF_TP4_SHIFT 12
#define AIPS_PACRF_WP4_MASK 0x2000u
#define AIPS_PACRF_WP4_SHIFT 13
#define AIPS_PACRF_SP4_MASK 0x4000u
#define AIPS_PACRF_SP4_SHIFT 14
#define AIPS_PACRF_TP3_MASK 0x10000u
#define AIPS_PACRF_TP3_SHIFT 16
#define AIPS_PACRF_WP3_MASK 0x20000u
#define AIPS_PACRF_WP3_SHIFT 17
#define AIPS_PACRF_SP3_MASK 0x40000u
#define AIPS_PACRF_SP3_SHIFT 18
#define AIPS_PACRF_TP2_MASK 0x100000u
#define AIPS_PACRF_TP2_SHIFT 20
#define AIPS_PACRF_WP2_MASK 0x200000u
#define AIPS_PACRF_WP2_SHIFT 21
#define AIPS_PACRF_SP2_MASK 0x400000u
#define AIPS_PACRF_SP2_SHIFT 22
#define AIPS_PACRF_TP1_MASK 0x1000000u
#define AIPS_PACRF_TP1_SHIFT 24
#define AIPS_PACRF_WP1_MASK 0x2000000u
#define AIPS_PACRF_WP1_SHIFT 25
#define AIPS_PACRF_SP1_MASK 0x4000000u
#define AIPS_PACRF_SP1_SHIFT 26
#define AIPS_PACRF_TP0_MASK 0x10000000u
#define AIPS_PACRF_TP0_SHIFT 28
#define AIPS_PACRF_WP0_MASK 0x20000000u
#define AIPS_PACRF_WP0_SHIFT 29
#define AIPS_PACRF_SP0_MASK 0x40000000u
#define AIPS_PACRF_SP0_SHIFT 30
/* PACRG Bit Fields */
#define AIPS_PACRG_TP7_MASK 0x1u
#define AIPS_PACRG_TP7_SHIFT 0
#define AIPS_PACRG_WP7_MASK 0x2u
#define AIPS_PACRG_WP7_SHIFT 1
#define AIPS_PACRG_SP7_MASK 0x4u
#define AIPS_PACRG_SP7_SHIFT 2
#define AIPS_PACRG_TP6_MASK 0x10u
#define AIPS_PACRG_TP6_SHIFT 4
#define AIPS_PACRG_WP6_MASK 0x20u
#define AIPS_PACRG_WP6_SHIFT 5
#define AIPS_PACRG_SP6_MASK 0x40u
#define AIPS_PACRG_SP6_SHIFT 6
#define AIPS_PACRG_TP5_MASK 0x100u
#define AIPS_PACRG_TP5_SHIFT 8
#define AIPS_PACRG_WP5_MASK 0x200u
#define AIPS_PACRG_WP5_SHIFT 9
#define AIPS_PACRG_SP5_MASK 0x400u
#define AIPS_PACRG_SP5_SHIFT 10
#define AIPS_PACRG_TP4_MASK 0x1000u
#define AIPS_PACRG_TP4_SHIFT 12
#define AIPS_PACRG_WP4_MASK 0x2000u
#define AIPS_PACRG_WP4_SHIFT 13
#define AIPS_PACRG_SP4_MASK 0x4000u
#define AIPS_PACRG_SP4_SHIFT 14
#define AIPS_PACRG_TP3_MASK 0x10000u
#define AIPS_PACRG_TP3_SHIFT 16
#define AIPS_PACRG_WP3_MASK 0x20000u
#define AIPS_PACRG_WP3_SHIFT 17
#define AIPS_PACRG_SP3_MASK 0x40000u
#define AIPS_PACRG_SP3_SHIFT 18
#define AIPS_PACRG_TP2_MASK 0x100000u
#define AIPS_PACRG_TP2_SHIFT 20
#define AIPS_PACRG_WP2_MASK 0x200000u
#define AIPS_PACRG_WP2_SHIFT 21
#define AIPS_PACRG_SP2_MASK 0x400000u
#define AIPS_PACRG_SP2_SHIFT 22
#define AIPS_PACRG_TP1_MASK 0x1000000u
#define AIPS_PACRG_TP1_SHIFT 24
#define AIPS_PACRG_WP1_MASK 0x2000000u
#define AIPS_PACRG_WP1_SHIFT 25
#define AIPS_PACRG_SP1_MASK 0x4000000u
#define AIPS_PACRG_SP1_SHIFT 26
#define AIPS_PACRG_TP0_MASK 0x10000000u
#define AIPS_PACRG_TP0_SHIFT 28
#define AIPS_PACRG_WP0_MASK 0x20000000u
#define AIPS_PACRG_WP0_SHIFT 29
#define AIPS_PACRG_SP0_MASK 0x40000000u
#define AIPS_PACRG_SP0_SHIFT 30
/* PACRH Bit Fields */
#define AIPS_PACRH_TP7_MASK 0x1u
#define AIPS_PACRH_TP7_SHIFT 0
#define AIPS_PACRH_WP7_MASK 0x2u
#define AIPS_PACRH_WP7_SHIFT 1
#define AIPS_PACRH_SP7_MASK 0x4u
#define AIPS_PACRH_SP7_SHIFT 2
#define AIPS_PACRH_TP6_MASK 0x10u
#define AIPS_PACRH_TP6_SHIFT 4
#define AIPS_PACRH_WP6_MASK 0x20u
#define AIPS_PACRH_WP6_SHIFT 5
#define AIPS_PACRH_SP6_MASK 0x40u
#define AIPS_PACRH_SP6_SHIFT 6
#define AIPS_PACRH_TP5_MASK 0x100u
#define AIPS_PACRH_TP5_SHIFT 8
#define AIPS_PACRH_WP5_MASK 0x200u
#define AIPS_PACRH_WP5_SHIFT 9
#define AIPS_PACRH_SP5_MASK 0x400u
#define AIPS_PACRH_SP5_SHIFT 10
#define AIPS_PACRH_TP4_MASK 0x1000u
#define AIPS_PACRH_TP4_SHIFT 12
#define AIPS_PACRH_WP4_MASK 0x2000u
#define AIPS_PACRH_WP4_SHIFT 13
#define AIPS_PACRH_SP4_MASK 0x4000u
#define AIPS_PACRH_SP4_SHIFT 14
#define AIPS_PACRH_TP3_MASK 0x10000u
#define AIPS_PACRH_TP3_SHIFT 16
#define AIPS_PACRH_WP3_MASK 0x20000u
#define AIPS_PACRH_WP3_SHIFT 17
#define AIPS_PACRH_SP3_MASK 0x40000u
#define AIPS_PACRH_SP3_SHIFT 18
#define AIPS_PACRH_TP2_MASK 0x100000u
#define AIPS_PACRH_TP2_SHIFT 20
#define AIPS_PACRH_WP2_MASK 0x200000u
#define AIPS_PACRH_WP2_SHIFT 21
#define AIPS_PACRH_SP2_MASK 0x400000u
#define AIPS_PACRH_SP2_SHIFT 22
#define AIPS_PACRH_TP1_MASK 0x1000000u
#define AIPS_PACRH_TP1_SHIFT 24
#define AIPS_PACRH_WP1_MASK 0x2000000u
#define AIPS_PACRH_WP1_SHIFT 25
#define AIPS_PACRH_SP1_MASK 0x4000000u
#define AIPS_PACRH_SP1_SHIFT 26
#define AIPS_PACRH_TP0_MASK 0x10000000u
#define AIPS_PACRH_TP0_SHIFT 28
#define AIPS_PACRH_WP0_MASK 0x20000000u
#define AIPS_PACRH_WP0_SHIFT 29
#define AIPS_PACRH_SP0_MASK 0x40000000u
#define AIPS_PACRH_SP0_SHIFT 30
/* PACRI Bit Fields */
#define AIPS_PACRI_TP7_MASK 0x1u
#define AIPS_PACRI_TP7_SHIFT 0
#define AIPS_PACRI_WP7_MASK 0x2u
#define AIPS_PACRI_WP7_SHIFT 1
#define AIPS_PACRI_SP7_MASK 0x4u
#define AIPS_PACRI_SP7_SHIFT 2
#define AIPS_PACRI_TP6_MASK 0x10u
#define AIPS_PACRI_TP6_SHIFT 4
#define AIPS_PACRI_WP6_MASK 0x20u
#define AIPS_PACRI_WP6_SHIFT 5
#define AIPS_PACRI_SP6_MASK 0x40u
#define AIPS_PACRI_SP6_SHIFT 6
#define AIPS_PACRI_TP5_MASK 0x100u
#define AIPS_PACRI_TP5_SHIFT 8
#define AIPS_PACRI_WP5_MASK 0x200u
#define AIPS_PACRI_WP5_SHIFT 9
#define AIPS_PACRI_SP5_MASK 0x400u
#define AIPS_PACRI_SP5_SHIFT 10
#define AIPS_PACRI_TP4_MASK 0x1000u
#define AIPS_PACRI_TP4_SHIFT 12
#define AIPS_PACRI_WP4_MASK 0x2000u
#define AIPS_PACRI_WP4_SHIFT 13
#define AIPS_PACRI_SP4_MASK 0x4000u
#define AIPS_PACRI_SP4_SHIFT 14
#define AIPS_PACRI_TP3_MASK 0x10000u
#define AIPS_PACRI_TP3_SHIFT 16
#define AIPS_PACRI_WP3_MASK 0x20000u
#define AIPS_PACRI_WP3_SHIFT 17
#define AIPS_PACRI_SP3_MASK 0x40000u
#define AIPS_PACRI_SP3_SHIFT 18
#define AIPS_PACRI_TP2_MASK 0x100000u
#define AIPS_PACRI_TP2_SHIFT 20
#define AIPS_PACRI_WP2_MASK 0x200000u
#define AIPS_PACRI_WP2_SHIFT 21
#define AIPS_PACRI_SP2_MASK 0x400000u
#define AIPS_PACRI_SP2_SHIFT 22
#define AIPS_PACRI_TP1_MASK 0x1000000u
#define AIPS_PACRI_TP1_SHIFT 24
#define AIPS_PACRI_WP1_MASK 0x2000000u
#define AIPS_PACRI_WP1_SHIFT 25
#define AIPS_PACRI_SP1_MASK 0x4000000u
#define AIPS_PACRI_SP1_SHIFT 26
#define AIPS_PACRI_TP0_MASK 0x10000000u
#define AIPS_PACRI_TP0_SHIFT 28
#define AIPS_PACRI_WP0_MASK 0x20000000u
#define AIPS_PACRI_WP0_SHIFT 29
#define AIPS_PACRI_SP0_MASK 0x40000000u
#define AIPS_PACRI_SP0_SHIFT 30
/* PACRJ Bit Fields */
#define AIPS_PACRJ_TP7_MASK 0x1u
#define AIPS_PACRJ_TP7_SHIFT 0
#define AIPS_PACRJ_WP7_MASK 0x2u
#define AIPS_PACRJ_WP7_SHIFT 1
#define AIPS_PACRJ_SP7_MASK 0x4u
#define AIPS_PACRJ_SP7_SHIFT 2
#define AIPS_PACRJ_TP6_MASK 0x10u
#define AIPS_PACRJ_TP6_SHIFT 4
#define AIPS_PACRJ_WP6_MASK 0x20u
#define AIPS_PACRJ_WP6_SHIFT 5
#define AIPS_PACRJ_SP6_MASK 0x40u
#define AIPS_PACRJ_SP6_SHIFT 6
#define AIPS_PACRJ_TP5_MASK 0x100u
#define AIPS_PACRJ_TP5_SHIFT 8
#define AIPS_PACRJ_WP5_MASK 0x200u
#define AIPS_PACRJ_WP5_SHIFT 9
#define AIPS_PACRJ_SP5_MASK 0x400u
#define AIPS_PACRJ_SP5_SHIFT 10
#define AIPS_PACRJ_TP4_MASK 0x1000u
#define AIPS_PACRJ_TP4_SHIFT 12
#define AIPS_PACRJ_WP4_MASK 0x2000u
#define AIPS_PACRJ_WP4_SHIFT 13
#define AIPS_PACRJ_SP4_MASK 0x4000u
#define AIPS_PACRJ_SP4_SHIFT 14
#define AIPS_PACRJ_TP3_MASK 0x10000u
#define AIPS_PACRJ_TP3_SHIFT 16
#define AIPS_PACRJ_WP3_MASK 0x20000u
#define AIPS_PACRJ_WP3_SHIFT 17
#define AIPS_PACRJ_SP3_MASK 0x40000u
#define AIPS_PACRJ_SP3_SHIFT 18
#define AIPS_PACRJ_TP2_MASK 0x100000u
#define AIPS_PACRJ_TP2_SHIFT 20
#define AIPS_PACRJ_WP2_MASK 0x200000u
#define AIPS_PACRJ_WP2_SHIFT 21
#define AIPS_PACRJ_SP2_MASK 0x400000u
#define AIPS_PACRJ_SP2_SHIFT 22
#define AIPS_PACRJ_TP1_MASK 0x1000000u
#define AIPS_PACRJ_TP1_SHIFT 24
#define AIPS_PACRJ_WP1_MASK 0x2000000u
#define AIPS_PACRJ_WP1_SHIFT 25
#define AIPS_PACRJ_SP1_MASK 0x4000000u
#define AIPS_PACRJ_SP1_SHIFT 26
#define AIPS_PACRJ_TP0_MASK 0x10000000u
#define AIPS_PACRJ_TP0_SHIFT 28
#define AIPS_PACRJ_WP0_MASK 0x20000000u
#define AIPS_PACRJ_WP0_SHIFT 29
#define AIPS_PACRJ_SP0_MASK 0x40000000u
#define AIPS_PACRJ_SP0_SHIFT 30
/* PACRK Bit Fields */
#define AIPS_PACRK_TP7_MASK 0x1u
#define AIPS_PACRK_TP7_SHIFT 0
#define AIPS_PACRK_WP7_MASK 0x2u
#define AIPS_PACRK_WP7_SHIFT 1
#define AIPS_PACRK_SP7_MASK 0x4u
#define AIPS_PACRK_SP7_SHIFT 2
#define AIPS_PACRK_TP6_MASK 0x10u
#define AIPS_PACRK_TP6_SHIFT 4
#define AIPS_PACRK_WP6_MASK 0x20u
#define AIPS_PACRK_WP6_SHIFT 5
#define AIPS_PACRK_SP6_MASK 0x40u
#define AIPS_PACRK_SP6_SHIFT 6
#define AIPS_PACRK_TP5_MASK 0x100u
#define AIPS_PACRK_TP5_SHIFT 8
#define AIPS_PACRK_WP5_MASK 0x200u
#define AIPS_PACRK_WP5_SHIFT 9
#define AIPS_PACRK_SP5_MASK 0x400u
#define AIPS_PACRK_SP5_SHIFT 10
#define AIPS_PACRK_TP4_MASK 0x1000u
#define AIPS_PACRK_TP4_SHIFT 12
#define AIPS_PACRK_WP4_MASK 0x2000u
#define AIPS_PACRK_WP4_SHIFT 13
#define AIPS_PACRK_SP4_MASK 0x4000u
#define AIPS_PACRK_SP4_SHIFT 14
#define AIPS_PACRK_TP3_MASK 0x10000u
#define AIPS_PACRK_TP3_SHIFT 16
#define AIPS_PACRK_WP3_MASK 0x20000u
#define AIPS_PACRK_WP3_SHIFT 17
#define AIPS_PACRK_SP3_MASK 0x40000u
#define AIPS_PACRK_SP3_SHIFT 18
#define AIPS_PACRK_TP2_MASK 0x100000u
#define AIPS_PACRK_TP2_SHIFT 20
#define AIPS_PACRK_WP2_MASK 0x200000u
#define AIPS_PACRK_WP2_SHIFT 21
#define AIPS_PACRK_SP2_MASK 0x400000u
#define AIPS_PACRK_SP2_SHIFT 22
#define AIPS_PACRK_TP1_MASK 0x1000000u
#define AIPS_PACRK_TP1_SHIFT 24
#define AIPS_PACRK_WP1_MASK 0x2000000u
#define AIPS_PACRK_WP1_SHIFT 25
#define AIPS_PACRK_SP1_MASK 0x4000000u
#define AIPS_PACRK_SP1_SHIFT 26
#define AIPS_PACRK_TP0_MASK 0x10000000u
#define AIPS_PACRK_TP0_SHIFT 28
#define AIPS_PACRK_WP0_MASK 0x20000000u
#define AIPS_PACRK_WP0_SHIFT 29
#define AIPS_PACRK_SP0_MASK 0x40000000u
#define AIPS_PACRK_SP0_SHIFT 30
/* PACRL Bit Fields */
#define AIPS_PACRL_TP7_MASK 0x1u
#define AIPS_PACRL_TP7_SHIFT 0
#define AIPS_PACRL_WP7_MASK 0x2u
#define AIPS_PACRL_WP7_SHIFT 1
#define AIPS_PACRL_SP7_MASK 0x4u
#define AIPS_PACRL_SP7_SHIFT 2
#define AIPS_PACRL_TP6_MASK 0x10u
#define AIPS_PACRL_TP6_SHIFT 4
#define AIPS_PACRL_WP6_MASK 0x20u
#define AIPS_PACRL_WP6_SHIFT 5
#define AIPS_PACRL_SP6_MASK 0x40u
#define AIPS_PACRL_SP6_SHIFT 6
#define AIPS_PACRL_TP5_MASK 0x100u
#define AIPS_PACRL_TP5_SHIFT 8
#define AIPS_PACRL_WP5_MASK 0x200u
#define AIPS_PACRL_WP5_SHIFT 9
#define AIPS_PACRL_SP5_MASK 0x400u
#define AIPS_PACRL_SP5_SHIFT 10
#define AIPS_PACRL_TP4_MASK 0x1000u
#define AIPS_PACRL_TP4_SHIFT 12
#define AIPS_PACRL_WP4_MASK 0x2000u
#define AIPS_PACRL_WP4_SHIFT 13
#define AIPS_PACRL_SP4_MASK 0x4000u
#define AIPS_PACRL_SP4_SHIFT 14
#define AIPS_PACRL_TP3_MASK 0x10000u
#define AIPS_PACRL_TP3_SHIFT 16
#define AIPS_PACRL_WP3_MASK 0x20000u
#define AIPS_PACRL_WP3_SHIFT 17
#define AIPS_PACRL_SP3_MASK 0x40000u
#define AIPS_PACRL_SP3_SHIFT 18
#define AIPS_PACRL_TP2_MASK 0x100000u
#define AIPS_PACRL_TP2_SHIFT 20
#define AIPS_PACRL_WP2_MASK 0x200000u
#define AIPS_PACRL_WP2_SHIFT 21
#define AIPS_PACRL_SP2_MASK 0x400000u
#define AIPS_PACRL_SP2_SHIFT 22
#define AIPS_PACRL_TP1_MASK 0x1000000u
#define AIPS_PACRL_TP1_SHIFT 24
#define AIPS_PACRL_WP1_MASK 0x2000000u
#define AIPS_PACRL_WP1_SHIFT 25
#define AIPS_PACRL_SP1_MASK 0x4000000u
#define AIPS_PACRL_SP1_SHIFT 26
#define AIPS_PACRL_TP0_MASK 0x10000000u
#define AIPS_PACRL_TP0_SHIFT 28
#define AIPS_PACRL_WP0_MASK 0x20000000u
#define AIPS_PACRL_WP0_SHIFT 29
#define AIPS_PACRL_SP0_MASK 0x40000000u
#define AIPS_PACRL_SP0_SHIFT 30
/* PACRM Bit Fields */
#define AIPS_PACRM_TP7_MASK 0x1u
#define AIPS_PACRM_TP7_SHIFT 0
#define AIPS_PACRM_WP7_MASK 0x2u
#define AIPS_PACRM_WP7_SHIFT 1
#define AIPS_PACRM_SP7_MASK 0x4u
#define AIPS_PACRM_SP7_SHIFT 2
#define AIPS_PACRM_TP6_MASK 0x10u
#define AIPS_PACRM_TP6_SHIFT 4
#define AIPS_PACRM_WP6_MASK 0x20u
#define AIPS_PACRM_WP6_SHIFT 5
#define AIPS_PACRM_SP6_MASK 0x40u
#define AIPS_PACRM_SP6_SHIFT 6
#define AIPS_PACRM_TP5_MASK 0x100u
#define AIPS_PACRM_TP5_SHIFT 8
#define AIPS_PACRM_WP5_MASK 0x200u
#define AIPS_PACRM_WP5_SHIFT 9
#define AIPS_PACRM_SP5_MASK 0x400u
#define AIPS_PACRM_SP5_SHIFT 10
#define AIPS_PACRM_TP4_MASK 0x1000u
#define AIPS_PACRM_TP4_SHIFT 12
#define AIPS_PACRM_WP4_MASK 0x2000u
#define AIPS_PACRM_WP4_SHIFT 13
#define AIPS_PACRM_SP4_MASK 0x4000u
#define AIPS_PACRM_SP4_SHIFT 14
#define AIPS_PACRM_TP3_MASK 0x10000u
#define AIPS_PACRM_TP3_SHIFT 16
#define AIPS_PACRM_WP3_MASK 0x20000u
#define AIPS_PACRM_WP3_SHIFT 17
#define AIPS_PACRM_SP3_MASK 0x40000u
#define AIPS_PACRM_SP3_SHIFT 18
#define AIPS_PACRM_TP2_MASK 0x100000u
#define AIPS_PACRM_TP2_SHIFT 20
#define AIPS_PACRM_WP2_MASK 0x200000u
#define AIPS_PACRM_WP2_SHIFT 21
#define AIPS_PACRM_SP2_MASK 0x400000u
#define AIPS_PACRM_SP2_SHIFT 22
#define AIPS_PACRM_TP1_MASK 0x1000000u
#define AIPS_PACRM_TP1_SHIFT 24
#define AIPS_PACRM_WP1_MASK 0x2000000u
#define AIPS_PACRM_WP1_SHIFT 25
#define AIPS_PACRM_SP1_MASK 0x4000000u
#define AIPS_PACRM_SP1_SHIFT 26
#define AIPS_PACRM_TP0_MASK 0x10000000u
#define AIPS_PACRM_TP0_SHIFT 28
#define AIPS_PACRM_WP0_MASK 0x20000000u
#define AIPS_PACRM_WP0_SHIFT 29
#define AIPS_PACRM_SP0_MASK 0x40000000u
#define AIPS_PACRM_SP0_SHIFT 30
/* PACRN Bit Fields */
#define AIPS_PACRN_TP7_MASK 0x1u
#define AIPS_PACRN_TP7_SHIFT 0
#define AIPS_PACRN_WP7_MASK 0x2u
#define AIPS_PACRN_WP7_SHIFT 1
#define AIPS_PACRN_SP7_MASK 0x4u
#define AIPS_PACRN_SP7_SHIFT 2
#define AIPS_PACRN_TP6_MASK 0x10u
#define AIPS_PACRN_TP6_SHIFT 4
#define AIPS_PACRN_WP6_MASK 0x20u
#define AIPS_PACRN_WP6_SHIFT 5
#define AIPS_PACRN_SP6_MASK 0x40u
#define AIPS_PACRN_SP6_SHIFT 6
#define AIPS_PACRN_TP5_MASK 0x100u
#define AIPS_PACRN_TP5_SHIFT 8
#define AIPS_PACRN_WP5_MASK 0x200u
#define AIPS_PACRN_WP5_SHIFT 9
#define AIPS_PACRN_SP5_MASK 0x400u
#define AIPS_PACRN_SP5_SHIFT 10
#define AIPS_PACRN_TP4_MASK 0x1000u
#define AIPS_PACRN_TP4_SHIFT 12
#define AIPS_PACRN_WP4_MASK 0x2000u
#define AIPS_PACRN_WP4_SHIFT 13
#define AIPS_PACRN_SP4_MASK 0x4000u
#define AIPS_PACRN_SP4_SHIFT 14
#define AIPS_PACRN_TP3_MASK 0x10000u
#define AIPS_PACRN_TP3_SHIFT 16
#define AIPS_PACRN_WP3_MASK 0x20000u
#define AIPS_PACRN_WP3_SHIFT 17
#define AIPS_PACRN_SP3_MASK 0x40000u
#define AIPS_PACRN_SP3_SHIFT 18
#define AIPS_PACRN_TP2_MASK 0x100000u
#define AIPS_PACRN_TP2_SHIFT 20
#define AIPS_PACRN_WP2_MASK 0x200000u
#define AIPS_PACRN_WP2_SHIFT 21
#define AIPS_PACRN_SP2_MASK 0x400000u
#define AIPS_PACRN_SP2_SHIFT 22
#define AIPS_PACRN_TP1_MASK 0x1000000u
#define AIPS_PACRN_TP1_SHIFT 24
#define AIPS_PACRN_WP1_MASK 0x2000000u
#define AIPS_PACRN_WP1_SHIFT 25
#define AIPS_PACRN_SP1_MASK 0x4000000u
#define AIPS_PACRN_SP1_SHIFT 26
#define AIPS_PACRN_TP0_MASK 0x10000000u
#define AIPS_PACRN_TP0_SHIFT 28
#define AIPS_PACRN_WP0_MASK 0x20000000u
#define AIPS_PACRN_WP0_SHIFT 29
#define AIPS_PACRN_SP0_MASK 0x40000000u
#define AIPS_PACRN_SP0_SHIFT 30
/* PACRO Bit Fields */
#define AIPS_PACRO_TP7_MASK 0x1u
#define AIPS_PACRO_TP7_SHIFT 0
#define AIPS_PACRO_WP7_MASK 0x2u
#define AIPS_PACRO_WP7_SHIFT 1
#define AIPS_PACRO_SP7_MASK 0x4u
#define AIPS_PACRO_SP7_SHIFT 2
#define AIPS_PACRO_TP6_MASK 0x10u
#define AIPS_PACRO_TP6_SHIFT 4
#define AIPS_PACRO_WP6_MASK 0x20u
#define AIPS_PACRO_WP6_SHIFT 5
#define AIPS_PACRO_SP6_MASK 0x40u
#define AIPS_PACRO_SP6_SHIFT 6
#define AIPS_PACRO_TP5_MASK 0x100u
#define AIPS_PACRO_TP5_SHIFT 8
#define AIPS_PACRO_WP5_MASK 0x200u
#define AIPS_PACRO_WP5_SHIFT 9
#define AIPS_PACRO_SP5_MASK 0x400u
#define AIPS_PACRO_SP5_SHIFT 10
#define AIPS_PACRO_TP4_MASK 0x1000u
#define AIPS_PACRO_TP4_SHIFT 12
#define AIPS_PACRO_WP4_MASK 0x2000u
#define AIPS_PACRO_WP4_SHIFT 13
#define AIPS_PACRO_SP4_MASK 0x4000u
#define AIPS_PACRO_SP4_SHIFT 14
#define AIPS_PACRO_TP3_MASK 0x10000u
#define AIPS_PACRO_TP3_SHIFT 16
#define AIPS_PACRO_WP3_MASK 0x20000u
#define AIPS_PACRO_WP3_SHIFT 17
#define AIPS_PACRO_SP3_MASK 0x40000u
#define AIPS_PACRO_SP3_SHIFT 18
#define AIPS_PACRO_TP2_MASK 0x100000u
#define AIPS_PACRO_TP2_SHIFT 20
#define AIPS_PACRO_WP2_MASK 0x200000u
#define AIPS_PACRO_WP2_SHIFT 21
#define AIPS_PACRO_SP2_MASK 0x400000u
#define AIPS_PACRO_SP2_SHIFT 22
#define AIPS_PACRO_TP1_MASK 0x1000000u
#define AIPS_PACRO_TP1_SHIFT 24
#define AIPS_PACRO_WP1_MASK 0x2000000u
#define AIPS_PACRO_WP1_SHIFT 25
#define AIPS_PACRO_SP1_MASK 0x4000000u
#define AIPS_PACRO_SP1_SHIFT 26
#define AIPS_PACRO_TP0_MASK 0x10000000u
#define AIPS_PACRO_TP0_SHIFT 28
#define AIPS_PACRO_WP0_MASK 0x20000000u
#define AIPS_PACRO_WP0_SHIFT 29
#define AIPS_PACRO_SP0_MASK 0x40000000u
#define AIPS_PACRO_SP0_SHIFT 30
/* PACRP Bit Fields */
#define AIPS_PACRP_TP7_MASK 0x1u
#define AIPS_PACRP_TP7_SHIFT 0
#define AIPS_PACRP_WP7_MASK 0x2u
#define AIPS_PACRP_WP7_SHIFT 1
#define AIPS_PACRP_SP7_MASK 0x4u
#define AIPS_PACRP_SP7_SHIFT 2
#define AIPS_PACRP_TP6_MASK 0x10u
#define AIPS_PACRP_TP6_SHIFT 4
#define AIPS_PACRP_WP6_MASK 0x20u
#define AIPS_PACRP_WP6_SHIFT 5
#define AIPS_PACRP_SP6_MASK 0x40u
#define AIPS_PACRP_SP6_SHIFT 6
#define AIPS_PACRP_TP5_MASK 0x100u
#define AIPS_PACRP_TP5_SHIFT 8
#define AIPS_PACRP_WP5_MASK 0x200u
#define AIPS_PACRP_WP5_SHIFT 9
#define AIPS_PACRP_SP5_MASK 0x400u
#define AIPS_PACRP_SP5_SHIFT 10
#define AIPS_PACRP_TP4_MASK 0x1000u
#define AIPS_PACRP_TP4_SHIFT 12
#define AIPS_PACRP_WP4_MASK 0x2000u
#define AIPS_PACRP_WP4_SHIFT 13
#define AIPS_PACRP_SP4_MASK 0x4000u
#define AIPS_PACRP_SP4_SHIFT 14
#define AIPS_PACRP_TP3_MASK 0x10000u
#define AIPS_PACRP_TP3_SHIFT 16
#define AIPS_PACRP_WP3_MASK 0x20000u
#define AIPS_PACRP_WP3_SHIFT 17
#define AIPS_PACRP_SP3_MASK 0x40000u
#define AIPS_PACRP_SP3_SHIFT 18
#define AIPS_PACRP_TP2_MASK 0x100000u
#define AIPS_PACRP_TP2_SHIFT 20
#define AIPS_PACRP_WP2_MASK 0x200000u
#define AIPS_PACRP_WP2_SHIFT 21
#define AIPS_PACRP_SP2_MASK 0x400000u
#define AIPS_PACRP_SP2_SHIFT 22
#define AIPS_PACRP_TP1_MASK 0x1000000u
#define AIPS_PACRP_TP1_SHIFT 24
#define AIPS_PACRP_WP1_MASK 0x2000000u
#define AIPS_PACRP_WP1_SHIFT 25
#define AIPS_PACRP_SP1_MASK 0x4000000u
#define AIPS_PACRP_SP1_SHIFT 26
#define AIPS_PACRP_TP0_MASK 0x10000000u
#define AIPS_PACRP_TP0_SHIFT 28
#define AIPS_PACRP_WP0_MASK 0x20000000u
#define AIPS_PACRP_WP0_SHIFT 29
#define AIPS_PACRP_SP0_MASK 0x40000000u
#define AIPS_PACRP_SP0_SHIFT 30
/*!
* @}
*/ /* end of group AIPS_Register_Masks */
/* AIPS - Peripheral instance base addresses */
/** Peripheral AIPS0 base pointer */
#define AIPS0_BASE_PTR ((AIPS_MemMapPtr)0x40000000u)
/** Peripheral AIPS1 base pointer */
#define AIPS1_BASE_PTR ((AIPS_MemMapPtr)0x40080000u)
/** Array initializer of AIPS peripheral base pointers */
#define AIPS_BASE_PTRS { AIPS0_BASE_PTR, AIPS1_BASE_PTR }
/* ----------------------------------------------------------------------------
-- AIPS - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
* @{
*/
/* AIPS - Register instance definitions */
/* AIPS0 */
#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0_BASE_PTR)
#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0_BASE_PTR)
/* AIPS1 */
#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1_BASE_PTR)
#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1_BASE_PTR)
/*!
* @}
*/ /* end of group AIPS_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group AIPS_Peripheral */
/* ----------------------------------------------------------------------------
-- AXBS
---------------------------------------------------------------------------- */
/*!
* @addtogroup AXBS_Peripheral AXBS
* @{
*/
/** AXBS - Peripheral register structure */
typedef struct AXBS_MemMap {
struct { /* offset: 0x0, array step: 0x100 */
uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
uint8_t RESERVED_0[12];
uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
uint8_t RESERVED_1[236];
} SLAVE[4];
uint8_t RESERVED_0[1024];
uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
uint8_t RESERVED_1[252];
uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
uint8_t RESERVED_2[252];
uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
uint8_t RESERVED_3[252];
uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
} volatile *AXBS_MemMapPtr;
/* ----------------------------------------------------------------------------
-- AXBS - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
* @{
*/
/* AXBS - Register accessors */
#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
#define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
/*!
* @}
*/ /* end of group AXBS_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- AXBS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AXBS_Register_Masks AXBS Register Masks
* @{
*/
/* PRS Bit Fields */
#define AXBS_PRS_M0_MASK 0x7u
#define AXBS_PRS_M0_SHIFT 0
#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
#define AXBS_PRS_M1_MASK 0x70u
#define AXBS_PRS_M1_SHIFT 4
#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
#define AXBS_PRS_M2_MASK 0x700u
#define AXBS_PRS_M2_SHIFT 8
#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
#define AXBS_PRS_M3_MASK 0x7000u
#define AXBS_PRS_M3_SHIFT 12
#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
#define AXBS_PRS_M4_MASK 0x70000u
#define AXBS_PRS_M4_SHIFT 16
#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
#define AXBS_PRS_M5_MASK 0x700000u
#define AXBS_PRS_M5_SHIFT 20
#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
/* CRS Bit Fields */
#define AXBS_CRS_PARK_MASK 0x7u
#define AXBS_CRS_PARK_SHIFT 0
#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
#define AXBS_CRS_PCTL_MASK 0x30u
#define AXBS_CRS_PCTL_SHIFT 4
#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
#define AXBS_CRS_ARB_MASK 0x300u
#define AXBS_CRS_ARB_SHIFT 8
#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
#define AXBS_CRS_HLP_MASK 0x40000000u
#define AXBS_CRS_HLP_SHIFT 30
#define AXBS_CRS_RO_MASK 0x80000000u
#define AXBS_CRS_RO_SHIFT 31
/* MGPCR0 Bit Fields */
#define AXBS_MGPCR0_AULB_MASK 0x7u
#define AXBS_MGPCR0_AULB_SHIFT 0
#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
/* MGPCR1 Bit Fields */
#define AXBS_MGPCR1_AULB_MASK 0x7u
#define AXBS_MGPCR1_AULB_SHIFT 0
#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
/* MGPCR2 Bit Fields */
#define AXBS_MGPCR2_AULB_MASK 0x7u
#define AXBS_MGPCR2_AULB_SHIFT 0
#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
/* MGPCR3 Bit Fields */
#define AXBS_MGPCR3_AULB_MASK 0x7u
#define AXBS_MGPCR3_AULB_SHIFT 0
#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
/*!
* @}
*/ /* end of group AXBS_Register_Masks */
/* AXBS - Peripheral instance base addresses */
/** Peripheral AXBS base pointer */
#define AXBS_BASE_PTR ((AXBS_MemMapPtr)0x40004000u)
/** Array initializer of AXBS peripheral base pointers */
#define AXBS_BASE_PTRS { AXBS_BASE_PTR }
/* ----------------------------------------------------------------------------
-- AXBS - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
* @{
*/
/* AXBS - Register instance definitions */
/* AXBS */
#define AXBS_PRS0 AXBS_PRS_REG(AXBS_BASE_PTR,0)
#define AXBS_CRS0 AXBS_CRS_REG(AXBS_BASE_PTR,0)
#define AXBS_PRS1 AXBS_PRS_REG(AXBS_BASE_PTR,1)
#define AXBS_CRS1 AXBS_CRS_REG(AXBS_BASE_PTR,1)
#define AXBS_PRS2 AXBS_PRS_REG(AXBS_BASE_PTR,2)
#define AXBS_CRS2 AXBS_CRS_REG(AXBS_BASE_PTR,2)
#define AXBS_PRS3 AXBS_PRS_REG(AXBS_BASE_PTR,3)
#define AXBS_CRS3 AXBS_CRS_REG(AXBS_BASE_PTR,3)
#define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS_BASE_PTR)
#define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS_BASE_PTR)
#define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS_BASE_PTR)
#define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS_BASE_PTR)
/* AXBS - Register array accessors */
#define AXBS_PRS(index) AXBS_PRS_REG(AXBS_BASE_PTR,index)
#define AXBS_CRS(index) AXBS_CRS_REG(AXBS_BASE_PTR,index)
/*!
* @}
*/ /* end of group AXBS_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group AXBS_Peripheral */
/* ----------------------------------------------------------------------------
-- CAN
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Peripheral CAN
* @{
*/
/** CAN - Peripheral register structure */
typedef struct CAN_MemMap {
uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */
uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
uint8_t RESERVED_0[4];
uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
uint32_t RX14MASK; /**< Rx 14 Mask Register, offset: 0x14 */
uint32_t RX15MASK; /**< Rx 15 Mask Register, offset: 0x18 */
uint32_t ECR; /**< Error Counter, offset: 0x1C */
uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */
uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */
uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */
uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */
uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */
uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */
uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */
uint8_t RESERVED_1[8];
uint32_t CRCR; /**< CRC Register, offset: 0x44 */
uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */
uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
uint8_t RESERVED_2[48];
struct { /* offset: 0x80, array step: 0x10 */
uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
} MB[16];
uint8_t RESERVED_3[1792];
uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
} volatile *CAN_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CAN - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
* @{
*/
/* CAN - Register accessors */
#define CAN_MCR_REG(base) ((base)->MCR)
#define CAN_CTRL1_REG(base) ((base)->CTRL1)
#define CAN_TIMER_REG(base) ((base)->TIMER)
#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
#define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
#define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
#define CAN_ECR_REG(base) ((base)->ECR)
#define CAN_ESR1_REG(base) ((base)->ESR1)
#define CAN_IMASK2_REG(base) ((base)->IMASK2)
#define CAN_IMASK1_REG(base) ((base)->IMASK1)
#define CAN_IFLAG2_REG(base) ((base)->IFLAG2)
#define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
#define CAN_CTRL2_REG(base) ((base)->CTRL2)
#define CAN_ESR2_REG(base) ((base)->ESR2)
#define CAN_CRCR_REG(base) ((base)->CRCR)
#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
#define CAN_RXFIR_REG(base) ((base)->RXFIR)
#define CAN_CS_REG(base,index) ((base)->MB[index].CS)
#define CAN_ID_REG(base,index) ((base)->MB[index].ID)
#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
/*!
* @}
*/ /* end of group CAN_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CAN Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Register_Masks CAN Register Masks
* @{
*/
/* MCR Bit Fields */
#define CAN_MCR_MAXMB_MASK 0x7Fu
#define CAN_MCR_MAXMB_SHIFT 0
#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
#define CAN_MCR_IDAM_MASK 0x300u
#define CAN_MCR_IDAM_SHIFT 8
#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
#define CAN_MCR_AEN_MASK 0x1000u
#define CAN_MCR_AEN_SHIFT 12
#define CAN_MCR_LPRIOEN_MASK 0x2000u
#define CAN_MCR_LPRIOEN_SHIFT 13
#define CAN_MCR_IRMQ_MASK 0x10000u
#define CAN_MCR_IRMQ_SHIFT 16
#define CAN_MCR_SRXDIS_MASK 0x20000u
#define CAN_MCR_SRXDIS_SHIFT 17
#define CAN_MCR_LPMACK_MASK 0x100000u
#define CAN_MCR_LPMACK_SHIFT 20
#define CAN_MCR_WRNEN_MASK 0x200000u
#define CAN_MCR_WRNEN_SHIFT 21
#define CAN_MCR_SLFWAK_MASK 0x400000u
#define CAN_MCR_SLFWAK_SHIFT 22
#define CAN_MCR_SUPV_MASK 0x800000u
#define CAN_MCR_SUPV_SHIFT 23
#define CAN_MCR_FRZACK_MASK 0x1000000u
#define CAN_MCR_FRZACK_SHIFT 24
#define CAN_MCR_SOFTRST_MASK 0x2000000u
#define CAN_MCR_SOFTRST_SHIFT 25
#define CAN_MCR_WAKMSK_MASK 0x4000000u
#define CAN_MCR_WAKMSK_SHIFT 26
#define CAN_MCR_NOTRDY_MASK 0x8000000u
#define CAN_MCR_NOTRDY_SHIFT 27
#define CAN_MCR_HALT_MASK 0x10000000u
#define CAN_MCR_HALT_SHIFT 28
#define CAN_MCR_RFEN_MASK 0x20000000u
#define CAN_MCR_RFEN_SHIFT 29
#define CAN_MCR_FRZ_MASK 0x40000000u
#define CAN_MCR_FRZ_SHIFT 30
#define CAN_MCR_MDIS_MASK 0x80000000u
#define CAN_MCR_MDIS_SHIFT 31
/* CTRL1 Bit Fields */
#define CAN_CTRL1_PROPSEG_MASK 0x7u
#define CAN_CTRL1_PROPSEG_SHIFT 0
#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
#define CAN_CTRL1_LOM_MASK 0x8u
#define CAN_CTRL1_LOM_SHIFT 3
#define CAN_CTRL1_LBUF_MASK 0x10u
#define CAN_CTRL1_LBUF_SHIFT 4
#define CAN_CTRL1_TSYN_MASK 0x20u
#define CAN_CTRL1_TSYN_SHIFT 5
#define CAN_CTRL1_BOFFREC_MASK 0x40u
#define CAN_CTRL1_BOFFREC_SHIFT 6
#define CAN_CTRL1_SMP_MASK 0x80u
#define CAN_CTRL1_SMP_SHIFT 7
#define CAN_CTRL1_RWRNMSK_MASK 0x400u
#define CAN_CTRL1_RWRNMSK_SHIFT 10
#define CAN_CTRL1_TWRNMSK_MASK 0x800u
#define CAN_CTRL1_TWRNMSK_SHIFT 11
#define CAN_CTRL1_LPB_MASK 0x1000u
#define CAN_CTRL1_LPB_SHIFT 12
#define CAN_CTRL1_CLKSRC_MASK 0x2000u
#define CAN_CTRL1_CLKSRC_SHIFT 13
#define CAN_CTRL1_ERRMSK_MASK 0x4000u
#define CAN_CTRL1_ERRMSK_SHIFT 14
#define CAN_CTRL1_BOFFMSK_MASK 0x8000u
#define CAN_CTRL1_BOFFMSK_SHIFT 15
#define CAN_CTRL1_PSEG2_MASK 0x70000u
#define CAN_CTRL1_PSEG2_SHIFT 16
#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
#define CAN_CTRL1_PSEG1_MASK 0x380000u
#define CAN_CTRL1_PSEG1_SHIFT 19
#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
#define CAN_CTRL1_RJW_MASK 0xC00000u
#define CAN_CTRL1_RJW_SHIFT 22
#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
#define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
#define CAN_CTRL1_PRESDIV_SHIFT 24
#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
/* TIMER Bit Fields */
#define CAN_TIMER_TIMER_MASK 0xFFFFu
#define CAN_TIMER_TIMER_SHIFT 0
#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
/* RXMGMASK Bit Fields */
#define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
#define CAN_RXMGMASK_MG_SHIFT 0
#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
/* RX14MASK Bit Fields */
#define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
#define CAN_RX14MASK_RX14M_SHIFT 0
#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
/* RX15MASK Bit Fields */
#define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
#define CAN_RX15MASK_RX15M_SHIFT 0
#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
/* ECR Bit Fields */
#define CAN_ECR_TXERRCNT_MASK 0xFFu
#define CAN_ECR_TXERRCNT_SHIFT 0
#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
#define CAN_ECR_RXERRCNT_MASK 0xFF00u
#define CAN_ECR_RXERRCNT_SHIFT 8
#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
/* ESR1 Bit Fields */
#define CAN_ESR1_WAKINT_MASK 0x1u
#define CAN_ESR1_WAKINT_SHIFT 0
#define CAN_ESR1_ERRINT_MASK 0x2u
#define CAN_ESR1_ERRINT_SHIFT 1
#define CAN_ESR1_BOFFINT_MASK 0x4u
#define CAN_ESR1_BOFFINT_SHIFT 2
#define CAN_ESR1_RX_MASK 0x8u
#define CAN_ESR1_RX_SHIFT 3
#define CAN_ESR1_FLTCONF_MASK 0x30u
#define CAN_ESR1_FLTCONF_SHIFT 4
#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
#define CAN_ESR1_TX_MASK 0x40u
#define CAN_ESR1_TX_SHIFT 6
#define CAN_ESR1_IDLE_MASK 0x80u
#define CAN_ESR1_IDLE_SHIFT 7
#define CAN_ESR1_RXWRN_MASK 0x100u
#define CAN_ESR1_RXWRN_SHIFT 8
#define CAN_ESR1_TXWRN_MASK 0x200u
#define CAN_ESR1_TXWRN_SHIFT 9
#define CAN_ESR1_STFERR_MASK 0x400u
#define CAN_ESR1_STFERR_SHIFT 10
#define CAN_ESR1_FRMERR_MASK 0x800u
#define CAN_ESR1_FRMERR_SHIFT 11
#define CAN_ESR1_CRCERR_MASK 0x1000u
#define CAN_ESR1_CRCERR_SHIFT 12
#define CAN_ESR1_ACKERR_MASK 0x2000u
#define CAN_ESR1_ACKERR_SHIFT 13
#define CAN_ESR1_BIT0ERR_MASK 0x4000u
#define CAN_ESR1_BIT0ERR_SHIFT 14
#define CAN_ESR1_BIT1ERR_MASK 0x8000u
#define CAN_ESR1_BIT1ERR_SHIFT 15
#define CAN_ESR1_RWRNINT_MASK 0x10000u
#define CAN_ESR1_RWRNINT_SHIFT 16
#define CAN_ESR1_TWRNINT_MASK 0x20000u
#define CAN_ESR1_TWRNINT_SHIFT 17
#define CAN_ESR1_SYNCH_MASK 0x40000u
#define CAN_ESR1_SYNCH_SHIFT 18
/* IMASK2 Bit Fields */
#define CAN_IMASK2_BUFHM_MASK 0xFFFFFFFFu
#define CAN_IMASK2_BUFHM_SHIFT 0
#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK2_BUFHM_SHIFT))&CAN_IMASK2_BUFHM_MASK)
/* IMASK1 Bit Fields */
#define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
#define CAN_IMASK1_BUFLM_SHIFT 0
#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
/* IFLAG2 Bit Fields */
#define CAN_IFLAG2_BUFHI_MASK 0xFFFFFFFFu
#define CAN_IFLAG2_BUFHI_SHIFT 0
#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG2_BUFHI_SHIFT))&CAN_IFLAG2_BUFHI_MASK)
/* IFLAG1 Bit Fields */
#define CAN_IFLAG1_BUF4TO0I_MASK 0x1Fu
#define CAN_IFLAG1_BUF4TO0I_SHIFT 0
#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO0I_SHIFT))&CAN_IFLAG1_BUF4TO0I_MASK)
#define CAN_IFLAG1_BUF5I_MASK 0x20u
#define CAN_IFLAG1_BUF5I_SHIFT 5
#define CAN_IFLAG1_BUF6I_MASK 0x40u
#define CAN_IFLAG1_BUF6I_SHIFT 6
#define CAN_IFLAG1_BUF7I_MASK 0x80u
#define CAN_IFLAG1_BUF7I_SHIFT 7
#define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
#define CAN_IFLAG1_BUF31TO8I_SHIFT 8
#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
/* CTRL2 Bit Fields */
#define CAN_CTRL2_EACEN_MASK 0x10000u
#define CAN_CTRL2_EACEN_SHIFT 16
#define CAN_CTRL2_RRS_MASK 0x20000u
#define CAN_CTRL2_RRS_SHIFT 17
#define CAN_CTRL2_MRP_MASK 0x40000u
#define CAN_CTRL2_MRP_SHIFT 18
#define CAN_CTRL2_TASD_MASK 0xF80000u
#define CAN_CTRL2_TASD_SHIFT 19
#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
#define CAN_CTRL2_RFFN_MASK 0xF000000u
#define CAN_CTRL2_RFFN_SHIFT 24
#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
#define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
#define CAN_CTRL2_WRMFRZ_SHIFT 28
/* ESR2 Bit Fields */
#define CAN_ESR2_IMB_MASK 0x2000u
#define CAN_ESR2_IMB_SHIFT 13
#define CAN_ESR2_VPS_MASK 0x4000u
#define CAN_ESR2_VPS_SHIFT 14
#define CAN_ESR2_LPTM_MASK 0x7F0000u
#define CAN_ESR2_LPTM_SHIFT 16
#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
/* CRCR Bit Fields */
#define CAN_CRCR_TXCRC_MASK 0x7FFFu
#define CAN_CRCR_TXCRC_SHIFT 0
#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
#define CAN_CRCR_MBCRC_MASK 0x7F0000u
#define CAN_CRCR_MBCRC_SHIFT 16
#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
/* RXFGMASK Bit Fields */
#define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
#define CAN_RXFGMASK_FGM_SHIFT 0
#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
/* RXFIR Bit Fields */
#define CAN_RXFIR_IDHIT_MASK 0x1FFu
#define CAN_RXFIR_IDHIT_SHIFT 0
#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
/* CS Bit Fields */
#define CAN_CS_TIME_STAMP_MASK 0xFFFFu
#define CAN_CS_TIME_STAMP_SHIFT 0
#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
#define CAN_CS_DLC_MASK 0xF0000u
#define CAN_CS_DLC_SHIFT 16
#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
#define CAN_CS_RTR_MASK 0x100000u
#define CAN_CS_RTR_SHIFT 20
#define CAN_CS_IDE_MASK 0x200000u
#define CAN_CS_IDE_SHIFT 21
#define CAN_CS_SRR_MASK 0x400000u
#define CAN_CS_SRR_SHIFT 22
#define CAN_CS_CODE_MASK 0xF000000u
#define CAN_CS_CODE_SHIFT 24
#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
/* ID Bit Fields */
#define CAN_ID_EXT_MASK 0x3FFFFu
#define CAN_ID_EXT_SHIFT 0
#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
#define CAN_ID_STD_MASK 0x1FFC0000u
#define CAN_ID_STD_SHIFT 18
#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
#define CAN_ID_PRIO_MASK 0xE0000000u
#define CAN_ID_PRIO_SHIFT 29
#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
/* WORD0 Bit Fields */
#define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
#define CAN_WORD0_DATA_BYTE_3_SHIFT 0
#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
#define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
#define CAN_WORD0_DATA_BYTE_2_SHIFT 8
#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
#define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
#define CAN_WORD0_DATA_BYTE_1_SHIFT 16
#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
#define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
#define CAN_WORD0_DATA_BYTE_0_SHIFT 24
#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
/* WORD1 Bit Fields */
#define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
#define CAN_WORD1_DATA_BYTE_7_SHIFT 0
#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
#define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
#define CAN_WORD1_DATA_BYTE_6_SHIFT 8
#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
#define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
#define CAN_WORD1_DATA_BYTE_5_SHIFT 16
#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
#define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
#define CAN_WORD1_DATA_BYTE_4_SHIFT 24
#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
/* RXIMR Bit Fields */
#define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
#define CAN_RXIMR_MI_SHIFT 0
#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
/*!
* @}
*/ /* end of group CAN_Register_Masks */
/* CAN - Peripheral instance base addresses */
/** Peripheral CAN0 base pointer */
#define CAN0_BASE_PTR ((CAN_MemMapPtr)0x40024000u)
/** Array initializer of CAN peripheral base pointers */
#define CAN_BASE_PTRS { CAN0_BASE_PTR }
/* ----------------------------------------------------------------------------
-- CAN - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
* @{
*/
/* CAN - Register instance definitions */
/* CAN0 */
#define CAN0_MCR CAN_MCR_REG(CAN0_BASE_PTR)
#define CAN0_CTRL1 CAN_CTRL1_REG(CAN0_BASE_PTR)
#define CAN0_TIMER CAN_TIMER_REG(CAN0_BASE_PTR)
#define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0_BASE_PTR)
#define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0_BASE_PTR)
#define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0_BASE_PTR)
#define CAN0_ECR CAN_ECR_REG(CAN0_BASE_PTR)
#define CAN0_ESR1 CAN_ESR1_REG(CAN0_BASE_PTR)
#define CAN0_IMASK2 CAN_IMASK2_REG(CAN0_BASE_PTR)
#define CAN0_IMASK1 CAN_IMASK1_REG(CAN0_BASE_PTR)
#define CAN0_IFLAG2 CAN_IFLAG2_REG(CAN0_BASE_PTR)
#define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0_BASE_PTR)
#define CAN0_CTRL2 CAN_CTRL2_REG(CAN0_BASE_PTR)
#define CAN0_ESR2 CAN_ESR2_REG(CAN0_BASE_PTR)
#define CAN0_CRCR CAN_CRCR_REG(CAN0_BASE_PTR)
#define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0_BASE_PTR)
#define CAN0_RXFIR CAN_RXFIR_REG(CAN0_BASE_PTR)
#define CAN0_CS0 CAN_CS_REG(CAN0_BASE_PTR,0)
#define CAN0_ID0 CAN_ID_REG(CAN0_BASE_PTR,0)
#define CAN0_WORD00 CAN_WORD0_REG(CAN0_BASE_PTR,0)
#define CAN0_WORD10 CAN_WORD1_REG(CAN0_BASE_PTR,0)
#define CAN0_CS1 CAN_CS_REG(CAN0_BASE_PTR,1)
#define CAN0_ID1 CAN_ID_REG(CAN0_BASE_PTR,1)
#define CAN0_WORD01 CAN_WORD0_REG(CAN0_BASE_PTR,1)
#define CAN0_WORD11 CAN_WORD1_REG(CAN0_BASE_PTR,1)
#define CAN0_CS2 CAN_CS_REG(CAN0_BASE_PTR,2)
#define CAN0_ID2 CAN_ID_REG(CAN0_BASE_PTR,2)
#define CAN0_WORD02 CAN_WORD0_REG(CAN0_BASE_PTR,2)
#define CAN0_WORD12 CAN_WORD1_REG(CAN0_BASE_PTR,2)
#define CAN0_CS3 CAN_CS_REG(CAN0_BASE_PTR,3)
#define CAN0_ID3 CAN_ID_REG(CAN0_BASE_PTR,3)
#define CAN0_WORD03 CAN_WORD0_REG(CAN0_BASE_PTR,3)
#define CAN0_WORD13 CAN_WORD1_REG(CAN0_BASE_PTR,3)
#define CAN0_CS4 CAN_CS_REG(CAN0_BASE_PTR,4)
#define CAN0_ID4 CAN_ID_REG(CAN0_BASE_PTR,4)
#define CAN0_WORD04 CAN_WORD0_REG(CAN0_BASE_PTR,4)
#define CAN0_WORD14 CAN_WORD1_REG(CAN0_BASE_PTR,4)
#define CAN0_CS5 CAN_CS_REG(CAN0_BASE_PTR,5)
#define CAN0_ID5 CAN_ID_REG(CAN0_BASE_PTR,5)
#define CAN0_WORD05 CAN_WORD0_REG(CAN0_BASE_PTR,5)
#define CAN0_WORD15 CAN_WORD1_REG(CAN0_BASE_PTR,5)
#define CAN0_CS6 CAN_CS_REG(CAN0_BASE_PTR,6)
#define CAN0_ID6 CAN_ID_REG(CAN0_BASE_PTR,6)
#define CAN0_WORD06 CAN_WORD0_REG(CAN0_BASE_PTR,6)
#define CAN0_WORD16 CAN_WORD1_REG(CAN0_BASE_PTR,6)
#define CAN0_CS7 CAN_CS_REG(CAN0_BASE_PTR,7)
#define CAN0_ID7 CAN_ID_REG(CAN0_BASE_PTR,7)
#define CAN0_WORD07 CAN_WORD0_REG(CAN0_BASE_PTR,7)
#define CAN0_WORD17 CAN_WORD1_REG(CAN0_BASE_PTR,7)
#define CAN0_CS8 CAN_CS_REG(CAN0_BASE_PTR,8)
#define CAN0_ID8 CAN_ID_REG(CAN0_BASE_PTR,8)
#define CAN0_WORD08 CAN_WORD0_REG(CAN0_BASE_PTR,8)
#define CAN0_WORD18 CAN_WORD1_REG(CAN0_BASE_PTR,8)
#define CAN0_CS9 CAN_CS_REG(CAN0_BASE_PTR,9)
#define CAN0_ID9 CAN_ID_REG(CAN0_BASE_PTR,9)
#define CAN0_WORD09 CAN_WORD0_REG(CAN0_BASE_PTR,9)
#define CAN0_WORD19 CAN_WORD1_REG(CAN0_BASE_PTR,9)
#define CAN0_CS10 CAN_CS_REG(CAN0_BASE_PTR,10)
#define CAN0_ID10 CAN_ID_REG(CAN0_BASE_PTR,10)
#define CAN0_WORD010 CAN_WORD0_REG(CAN0_BASE_PTR,10)
#define CAN0_WORD110 CAN_WORD1_REG(CAN0_BASE_PTR,10)
#define CAN0_CS11 CAN_CS_REG(CAN0_BASE_PTR,11)
#define CAN0_ID11 CAN_ID_REG(CAN0_BASE_PTR,11)
#define CAN0_WORD011 CAN_WORD0_REG(CAN0_BASE_PTR,11)
#define CAN0_WORD111 CAN_WORD1_REG(CAN0_BASE_PTR,11)
#define CAN0_CS12 CAN_CS_REG(CAN0_BASE_PTR,12)
#define CAN0_ID12 CAN_ID_REG(CAN0_BASE_PTR,12)
#define CAN0_WORD012 CAN_WORD0_REG(CAN0_BASE_PTR,12)
#define CAN0_WORD112 CAN_WORD1_REG(CAN0_BASE_PTR,12)
#define CAN0_CS13 CAN_CS_REG(CAN0_BASE_PTR,13)
#define CAN0_ID13 CAN_ID_REG(CAN0_BASE_PTR,13)
#define CAN0_WORD013 CAN_WORD0_REG(CAN0_BASE_PTR,13)
#define CAN0_WORD113 CAN_WORD1_REG(CAN0_BASE_PTR,13)
#define CAN0_CS14 CAN_CS_REG(CAN0_BASE_PTR,14)
#define CAN0_ID14 CAN_ID_REG(CAN0_BASE_PTR,14)
#define CAN0_WORD014 CAN_WORD0_REG(CAN0_BASE_PTR,14)
#define CAN0_WORD114 CAN_WORD1_REG(CAN0_BASE_PTR,14)
#define CAN0_CS15 CAN_CS_REG(CAN0_BASE_PTR,15)
#define CAN0_ID15 CAN_ID_REG(CAN0_BASE_PTR,15)
#define CAN0_WORD015 CAN_WORD0_REG(CAN0_BASE_PTR,15)
#define CAN0_WORD115 CAN_WORD1_REG(CAN0_BASE_PTR,15)
#define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0_BASE_PTR,0)
#define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0_BASE_PTR,1)
#define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0_BASE_PTR,2)
#define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0_BASE_PTR,3)
#define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0_BASE_PTR,4)
#define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0_BASE_PTR,5)
#define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0_BASE_PTR,6)
#define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0_BASE_PTR,7)
#define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0_BASE_PTR,8)
#define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0_BASE_PTR,9)
#define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0_BASE_PTR,10)
#define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0_BASE_PTR,11)
#define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0_BASE_PTR,12)
#define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0_BASE_PTR,13)
#define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0_BASE_PTR,14)
#define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0_BASE_PTR,15)
/* CAN - Register array accessors */
#define CAN0_CS(index) CAN_CS_REG(CAN0_BASE_PTR,index)
#define CAN0_ID(index) CAN_ID_REG(CAN0_BASE_PTR,index)
#define CAN0_WORD0(index) CAN_WORD0_REG(CAN0_BASE_PTR,index)
#define CAN0_WORD1(index) CAN_WORD1_REG(CAN0_BASE_PTR,index)
#define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0_BASE_PTR,index)
/*!
* @}
*/ /* end of group CAN_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CAN_Peripheral */
/* ----------------------------------------------------------------------------
-- CMP
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Peripheral CMP
* @{
*/
/** CMP - Peripheral register structure */
typedef struct CMP_MemMap {
uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
} volatile *CMP_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CMP - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
* @{
*/
/* CMP - Register accessors */
#define CMP_CR0_REG(base) ((base)->CR0)
#define CMP_CR1_REG(base) ((base)->CR1)
#define CMP_FPR_REG(base) ((base)->FPR)
#define CMP_SCR_REG(base) ((base)->SCR)
#define CMP_DACCR_REG(base) ((base)->DACCR)
#define CMP_MUXCR_REG(base) ((base)->MUXCR)
/*!
* @}
*/ /* end of group CMP_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CMP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
/* CR0 Bit Fields */
#define CMP_CR0_HYSTCTR_MASK 0x3u
#define CMP_CR0_HYSTCTR_SHIFT 0
#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
#define CMP_CR0_FILTER_CNT_MASK 0x70u
#define CMP_CR0_FILTER_CNT_SHIFT 4
#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
/* CR1 Bit Fields */
#define CMP_CR1_EN_MASK 0x1u
#define CMP_CR1_EN_SHIFT 0
#define CMP_CR1_OPE_MASK 0x2u
#define CMP_CR1_OPE_SHIFT 1
#define CMP_CR1_COS_MASK 0x4u
#define CMP_CR1_COS_SHIFT 2
#define CMP_CR1_INV_MASK 0x8u
#define CMP_CR1_INV_SHIFT 3
#define CMP_CR1_PMODE_MASK 0x10u
#define CMP_CR1_PMODE_SHIFT 4
#define CMP_CR1_WE_MASK 0x40u
#define CMP_CR1_WE_SHIFT 6
#define CMP_CR1_SE_MASK 0x80u
#define CMP_CR1_SE_SHIFT 7
/* FPR Bit Fields */
#define CMP_FPR_FILT_PER_MASK 0xFFu
#define CMP_FPR_FILT_PER_SHIFT 0
#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
/* SCR Bit Fields */
#define CMP_SCR_COUT_MASK 0x1u
#define CMP_SCR_COUT_SHIFT 0
#define CMP_SCR_CFF_MASK 0x2u
#define CMP_SCR_CFF_SHIFT 1
#define CMP_SCR_CFR_MASK 0x4u
#define CMP_SCR_CFR_SHIFT 2
#define CMP_SCR_IEF_MASK 0x8u
#define CMP_SCR_IEF_SHIFT 3
#define CMP_SCR_IER_MASK 0x10u
#define CMP_SCR_IER_SHIFT 4
#define CMP_SCR_DMAEN_MASK 0x40u
#define CMP_SCR_DMAEN_SHIFT 6
/* DACCR Bit Fields */
#define CMP_DACCR_VOSEL_MASK 0x3Fu
#define CMP_DACCR_VOSEL_SHIFT 0
#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
#define CMP_DACCR_VRSEL_MASK 0x40u
#define CMP_DACCR_VRSEL_SHIFT 6
#define CMP_DACCR_DACEN_MASK 0x80u
#define CMP_DACCR_DACEN_SHIFT 7
/* MUXCR Bit Fields */
#define CMP_MUXCR_MSEL_MASK 0x7u
#define CMP_MUXCR_MSEL_SHIFT 0
#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
#define CMP_MUXCR_PSEL_MASK 0x38u
#define CMP_MUXCR_PSEL_SHIFT 3
#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
/*!
* @}
*/ /* end of group CMP_Register_Masks */
/* CMP - Peripheral instance base addresses */
/** Peripheral CMP0 base pointer */
#define CMP0_BASE_PTR ((CMP_MemMapPtr)0x40073000u)
/** Peripheral CMP1 base pointer */
#define CMP1_BASE_PTR ((CMP_MemMapPtr)0x40073008u)
/** Peripheral CMP2 base pointer */
#define CMP2_BASE_PTR ((CMP_MemMapPtr)0x40073010u)
/** Array initializer of CMP peripheral base pointers */
#define CMP_BASE_PTRS { CMP0_BASE_PTR, CMP1_BASE_PTR, CMP2_BASE_PTR }
/* ----------------------------------------------------------------------------
-- CMP - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
* @{
*/
/* CMP - Register instance definitions */
/* CMP0 */
#define CMP0_CR0 CMP_CR0_REG(CMP0_BASE_PTR)
#define CMP0_CR1 CMP_CR1_REG(CMP0_BASE_PTR)
#define CMP0_FPR CMP_FPR_REG(CMP0_BASE_PTR)
#define CMP0_SCR CMP_SCR_REG(CMP0_BASE_PTR)
#define CMP0_DACCR CMP_DACCR_REG(CMP0_BASE_PTR)
#define CMP0_MUXCR CMP_MUXCR_REG(CMP0_BASE_PTR)
/* CMP1 */
#define CMP1_CR0 CMP_CR0_REG(CMP1_BASE_PTR)
#define CMP1_CR1 CMP_CR1_REG(CMP1_BASE_PTR)
#define CMP1_FPR CMP_FPR_REG(CMP1_BASE_PTR)
#define CMP1_SCR CMP_SCR_REG(CMP1_BASE_PTR)
#define CMP1_DACCR CMP_DACCR_REG(CMP1_BASE_PTR)
#define CMP1_MUXCR CMP_MUXCR_REG(CMP1_BASE_PTR)
/* CMP2 */
#define CMP2_CR0 CMP_CR0_REG(CMP2_BASE_PTR)
#define CMP2_CR1 CMP_CR1_REG(CMP2_BASE_PTR)
#define CMP2_FPR CMP_FPR_REG(CMP2_BASE_PTR)
#define CMP2_SCR CMP_SCR_REG(CMP2_BASE_PTR)
#define CMP2_DACCR CMP_DACCR_REG(CMP2_BASE_PTR)
#define CMP2_MUXCR CMP_MUXCR_REG(CMP2_BASE_PTR)
/*!
* @}
*/ /* end of group CMP_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CMP_Peripheral */
/* ----------------------------------------------------------------------------
-- CMT
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMT_Peripheral CMT
* @{
*/
/** CMT - Peripheral register structure */
typedef struct CMT_MemMap {
uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
} volatile *CMT_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CMT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
* @{
*/
/* CMT - Register accessors */
#define CMT_CGH1_REG(base) ((base)->CGH1)
#define CMT_CGL1_REG(base) ((base)->CGL1)
#define CMT_CGH2_REG(base) ((base)->CGH2)
#define CMT_CGL2_REG(base) ((base)->CGL2)
#define CMT_OC_REG(base) ((base)->OC)
#define CMT_MSC_REG(base) ((base)->MSC)
#define CMT_CMD1_REG(base) ((base)->CMD1)
#define CMT_CMD2_REG(base) ((base)->CMD2)
#define CMT_CMD3_REG(base) ((base)->CMD3)
#define CMT_CMD4_REG(base) ((base)->CMD4)
#define CMT_PPS_REG(base) ((base)->PPS)
#define CMT_DMA_REG(base) ((base)->DMA)
/*!
* @}
*/ /* end of group CMT_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CMT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMT_Register_Masks CMT Register Masks
* @{
*/
/* CGH1 Bit Fields */
#define CMT_CGH1_PH_MASK 0xFFu
#define CMT_CGH1_PH_SHIFT 0
#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
/* CGL1 Bit Fields */
#define CMT_CGL1_PL_MASK 0xFFu
#define CMT_CGL1_PL_SHIFT 0
#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
/* CGH2 Bit Fields */
#define CMT_CGH2_SH_MASK 0xFFu
#define CMT_CGH2_SH_SHIFT 0
#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
/* CGL2 Bit Fields */
#define CMT_CGL2_SL_MASK 0xFFu
#define CMT_CGL2_SL_SHIFT 0
#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
/* OC Bit Fields */
#define CMT_OC_IROPEN_MASK 0x20u
#define CMT_OC_IROPEN_SHIFT 5
#define CMT_OC_CMTPOL_MASK 0x40u
#define CMT_OC_CMTPOL_SHIFT 6
#define CMT_OC_IROL_MASK 0x80u
#define CMT_OC_IROL_SHIFT 7
/* MSC Bit Fields */
#define CMT_MSC_MCGEN_MASK 0x1u
#define CMT_MSC_MCGEN_SHIFT 0
#define CMT_MSC_EOCIE_MASK 0x2u
#define CMT_MSC_EOCIE_SHIFT 1
#define CMT_MSC_FSK_MASK 0x4u
#define CMT_MSC_FSK_SHIFT 2
#define CMT_MSC_BASE_MASK 0x8u
#define CMT_MSC_BASE_SHIFT 3
#define CMT_MSC_EXSPC_MASK 0x10u
#define CMT_MSC_EXSPC_SHIFT 4
#define CMT_MSC_CMTDIV_MASK 0x60u
#define CMT_MSC_CMTDIV_SHIFT 5
#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
#define CMT_MSC_EOCF_MASK 0x80u
#define CMT_MSC_EOCF_SHIFT 7
/* CMD1 Bit Fields */
#define CMT_CMD1_MB_MASK 0xFFu
#define CMT_CMD1_MB_SHIFT 0
#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
/* CMD2 Bit Fields */
#define CMT_CMD2_MB_MASK 0xFFu
#define CMT_CMD2_MB_SHIFT 0
#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
/* CMD3 Bit Fields */
#define CMT_CMD3_SB_MASK 0xFFu
#define CMT_CMD3_SB_SHIFT 0
#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
/* CMD4 Bit Fields */
#define CMT_CMD4_SB_MASK 0xFFu
#define CMT_CMD4_SB_SHIFT 0
#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
/* PPS Bit Fields */
#define CMT_PPS_PPSDIV_MASK 0xFu
#define CMT_PPS_PPSDIV_SHIFT 0
#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
/* DMA Bit Fields */
#define CMT_DMA_DMA_MASK 0x1u
#define CMT_DMA_DMA_SHIFT 0
/*!
* @}
*/ /* end of group CMT_Register_Masks */
/* CMT - Peripheral instance base addresses */
/** Peripheral CMT base pointer */
#define CMT_BASE_PTR ((CMT_MemMapPtr)0x40062000u)
/** Array initializer of CMT peripheral base pointers */
#define CMT_BASE_PTRS { CMT_BASE_PTR }
/* ----------------------------------------------------------------------------
-- CMT - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
* @{
*/
/* CMT - Register instance definitions */
/* CMT */
#define CMT_CGH1 CMT_CGH1_REG(CMT_BASE_PTR)
#define CMT_CGL1 CMT_CGL1_REG(CMT_BASE_PTR)
#define CMT_CGH2 CMT_CGH2_REG(CMT_BASE_PTR)
#define CMT_CGL2 CMT_CGL2_REG(CMT_BASE_PTR)
#define CMT_OC CMT_OC_REG(CMT_BASE_PTR)
#define CMT_MSC CMT_MSC_REG(CMT_BASE_PTR)
#define CMT_CMD1 CMT_CMD1_REG(CMT_BASE_PTR)
#define CMT_CMD2 CMT_CMD2_REG(CMT_BASE_PTR)
#define CMT_CMD3 CMT_CMD3_REG(CMT_BASE_PTR)
#define CMT_CMD4 CMT_CMD4_REG(CMT_BASE_PTR)
#define CMT_PPS CMT_PPS_REG(CMT_BASE_PTR)
#define CMT_DMA CMT_DMA_REG(CMT_BASE_PTR)
/*!
* @}
*/ /* end of group CMT_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CMT_Peripheral */
/* ----------------------------------------------------------------------------
-- CRC
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Peripheral CRC
* @{
*/
/** CRC - Peripheral register structure */
typedef struct CRC_MemMap {
union { /* offset: 0x0 */
struct { /* offset: 0x0 */
uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
} ACCESS16BIT;
uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
struct { /* offset: 0x0 */
uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
} ACCESS8BIT;
};
union { /* offset: 0x4 */
struct { /* offset: 0x4 */
uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
} GPOLY_ACCESS16BIT;
uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
struct { /* offset: 0x4 */
uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
} GPOLY_ACCESS8BIT;
};
union { /* offset: 0x8 */
uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
struct { /* offset: 0x8 */
uint8_t RESERVED_0[3];
uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
} CTRL_ACCESS8BIT;
};
} volatile *CRC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CRC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
* @{
*/
/* CRC - Register accessors */
#define CRC_CRCL_REG(base) ((base)->ACCESS16BIT.CRCL)
#define CRC_CRCH_REG(base) ((base)->ACCESS16BIT.CRCH)
#define CRC_CRC_REG(base) ((base)->CRC)
#define CRC_CRCLL_REG(base) ((base)->ACCESS8BIT.CRCLL)
#define CRC_CRCLU_REG(base) ((base)->ACCESS8BIT.CRCLU)
#define CRC_CRCHL_REG(base) ((base)->ACCESS8BIT.CRCHL)
#define CRC_CRCHU_REG(base) ((base)->ACCESS8BIT.CRCHU)
#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
#define CRC_GPOLY_REG(base) ((base)->GPOLY)
#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
#define CRC_CTRL_REG(base) ((base)->CTRL)
#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
/*!
* @}
*/ /* end of group CRC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Masks CRC Register Masks
* @{
*/
/* CRCL Bit Fields */
#define CRC_CRCL_CRCL_MASK 0xFFFFu
#define CRC_CRCL_CRCL_SHIFT 0
#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
/* CRCH Bit Fields */
#define CRC_CRCH_CRCH_MASK 0xFFFFu
#define CRC_CRCH_CRCH_SHIFT 0
#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
/* CRC Bit Fields */
#define CRC_CRC_LL_MASK 0xFFu
#define CRC_CRC_LL_SHIFT 0
#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
#define CRC_CRC_LU_MASK 0xFF00u
#define CRC_CRC_LU_SHIFT 8
#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
#define CRC_CRC_HL_MASK 0xFF0000u
#define CRC_CRC_HL_SHIFT 16
#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
#define CRC_CRC_HU_MASK 0xFF000000u
#define CRC_CRC_HU_SHIFT 24
#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
/* CRCLL Bit Fields */
#define CRC_CRCLL_CRCLL_MASK 0xFFu
#define CRC_CRCLL_CRCLL_SHIFT 0
#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
/* CRCLU Bit Fields */
#define CRC_CRCLU_CRCLU_MASK 0xFFu
#define CRC_CRCLU_CRCLU_SHIFT 0
#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
/* CRCHL Bit Fields */
#define CRC_CRCHL_CRCHL_MASK 0xFFu
#define CRC_CRCHL_CRCHL_SHIFT 0
#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
/* CRCHU Bit Fields */
#define CRC_CRCHU_CRCHU_MASK 0xFFu
#define CRC_CRCHU_CRCHU_SHIFT 0
#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
/* GPOLYL Bit Fields */
#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
#define CRC_GPOLYL_GPOLYL_SHIFT 0
#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
/* GPOLYH Bit Fields */
#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
#define CRC_GPOLYH_GPOLYH_SHIFT 0
#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
/* GPOLY Bit Fields */
#define CRC_GPOLY_LOW_MASK 0xFFFFu
#define CRC_GPOLY_LOW_SHIFT 0
#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
#define CRC_GPOLY_HIGH_SHIFT 16
#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
/* GPOLYLL Bit Fields */
#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
/* GPOLYLU Bit Fields */
#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
/* GPOLYHL Bit Fields */
#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
/* GPOLYHU Bit Fields */
#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
/* CTRL Bit Fields */
#define CRC_CTRL_TCRC_MASK 0x1000000u
#define CRC_CTRL_TCRC_SHIFT 24
#define CRC_CTRL_WAS_MASK 0x2000000u
#define CRC_CTRL_WAS_SHIFT 25
#define CRC_CTRL_FXOR_MASK 0x4000000u
#define CRC_CTRL_FXOR_SHIFT 26
#define CRC_CTRL_TOTR_MASK 0x30000000u
#define CRC_CTRL_TOTR_SHIFT 28
#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
#define CRC_CTRL_TOT_MASK 0xC0000000u
#define CRC_CTRL_TOT_SHIFT 30
#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
/* CTRLHU Bit Fields */
#define CRC_CTRLHU_TCRC_MASK 0x1u
#define CRC_CTRLHU_TCRC_SHIFT 0
#define CRC_CTRLHU_WAS_MASK 0x2u
#define CRC_CTRLHU_WAS_SHIFT 1
#define CRC_CTRLHU_FXOR_MASK 0x4u
#define CRC_CTRLHU_FXOR_SHIFT 2
#define CRC_CTRLHU_TOTR_MASK 0x30u
#define CRC_CTRLHU_TOTR_SHIFT 4
#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
#define CRC_CTRLHU_TOT_MASK 0xC0u
#define CRC_CTRLHU_TOT_SHIFT 6
#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
/*!
* @}
*/ /* end of group CRC_Register_Masks */
/* CRC - Peripheral instance base addresses */
/** Peripheral CRC base pointer */
#define CRC_BASE_PTR ((CRC_MemMapPtr)0x40032000u)
/** Array initializer of CRC peripheral base pointers */
#define CRC_BASE_PTRS { CRC_BASE_PTR }
/* ----------------------------------------------------------------------------
-- CRC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
* @{
*/
/* CRC - Register instance definitions */
/* CRC */
#define CRC_CRC CRC_CRC_REG(CRC_BASE_PTR)
#define CRC_CRCL CRC_CRCL_REG(CRC_BASE_PTR)
#define CRC_CRCLL CRC_CRCLL_REG(CRC_BASE_PTR)
#define CRC_CRCLU CRC_CRCLU_REG(CRC_BASE_PTR)
#define CRC_CRCH CRC_CRCH_REG(CRC_BASE_PTR)
#define CRC_CRCHL CRC_CRCHL_REG(CRC_BASE_PTR)
#define CRC_CRCHU CRC_CRCHU_REG(CRC_BASE_PTR)
#define CRC_GPOLY CRC_GPOLY_REG(CRC_BASE_PTR)
#define CRC_GPOLYL CRC_GPOLYL_REG(CRC_BASE_PTR)
#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC_BASE_PTR)
#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC_BASE_PTR)
#define CRC_GPOLYH CRC_GPOLYH_REG(CRC_BASE_PTR)
#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC_BASE_PTR)
#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC_BASE_PTR)
#define CRC_CTRL CRC_CTRL_REG(CRC_BASE_PTR)
#define CRC_CTRLHU CRC_CTRLHU_REG(CRC_BASE_PTR)
/*!
* @}
*/ /* end of group CRC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CRC_Peripheral */
/* ----------------------------------------------------------------------------
-- CoreDebug
---------------------------------------------------------------------------- */
/*!
* @addtogroup CoreDebug_Peripheral CoreDebug
* @{
*/
/** CoreDebug - Peripheral register structure */
typedef struct CoreDebug_MemMap {
union { /* offset: 0x0 */
uint32_t base_DHCSR_Read; /**< Debug Halting Control and Status Register, offset: 0x0 */
uint32_t base_DHCSR_Write; /**< Debug Halting Control and Status Register, offset: 0x0 */
};
uint32_t base_DCRSR; /**< Debug Core Register Selector Register, offset: 0x4 */
uint32_t base_DCRDR; /**< Debug Core Register Data Register, offset: 0x8 */
uint32_t base_DEMCR; /**< Debug Exception and Monitor Control Register, offset: 0xC */
} volatile *CoreDebug_MemMapPtr;
/* ----------------------------------------------------------------------------
-- CoreDebug - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros
* @{
*/
/* CoreDebug - Register accessors */
#define CoreDebug_base_DHCSR_Read_REG(base) ((base)->base_DHCSR_Read)
#define CoreDebug_base_DHCSR_Write_REG(base) ((base)->base_DHCSR_Write)
#define CoreDebug_base_DCRSR_REG(base) ((base)->base_DCRSR)
#define CoreDebug_base_DCRDR_REG(base) ((base)->base_DCRDR)
#define CoreDebug_base_DEMCR_REG(base) ((base)->base_DEMCR)
/*!
* @}
*/ /* end of group CoreDebug_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- CoreDebug Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CoreDebug_Register_Masks CoreDebug Register Masks
* @{
*/
/*!
* @}
*/ /* end of group CoreDebug_Register_Masks */
/* CoreDebug - Peripheral instance base addresses */
/** Peripheral CoreDebug base pointer */
#define CoreDebug_BASE_PTR ((CoreDebug_MemMapPtr)0xE000EDF0u)
/** Array initializer of CoreDebug peripheral base pointers */
#define CoreDebug_BASE_PTRS { CoreDebug_BASE_PTR }
/* ----------------------------------------------------------------------------
-- CoreDebug - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros
* @{
*/
/* CoreDebug - Register instance definitions */
/* CoreDebug */
#define DHCSR_Read CoreDebug_base_DHCSR_Read_REG(CoreDebug_BASE_PTR)
#define DHCSR_Write CoreDebug_base_DHCSR_Write_REG(CoreDebug_BASE_PTR)
#define DCRSR CoreDebug_base_DCRSR_REG(CoreDebug_BASE_PTR)
#define DCRDR CoreDebug_base_DCRDR_REG(CoreDebug_BASE_PTR)
#define DEMCR CoreDebug_base_DEMCR_REG(CoreDebug_BASE_PTR)
/*!
* @}
*/ /* end of group CoreDebug_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group CoreDebug_Peripheral */
/* ----------------------------------------------------------------------------
-- DAC
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Peripheral DAC
* @{
*/
/** DAC - Peripheral register structure */
typedef struct DAC_MemMap {
struct { /* offset: 0x0, array step: 0x2 */
uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
} DAT[16];
uint8_t SR; /**< DAC Status Register, offset: 0x20 */
uint8_t C0; /**< DAC Control Register, offset: 0x21 */
uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
} volatile *DAC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DAC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
* @{
*/
/* DAC - Register accessors */
#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
#define DAC_SR_REG(base) ((base)->SR)
#define DAC_C0_REG(base) ((base)->C0)
#define DAC_C1_REG(base) ((base)->C1)
#define DAC_C2_REG(base) ((base)->C2)
/*!
* @}
*/ /* end of group DAC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DAC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Masks DAC Register Masks
* @{
*/
/* DATL Bit Fields */
#define DAC_DATL_DATA_MASK 0xFFu
#define DAC_DATL_DATA_SHIFT 0
#define DAC_DATL_DATA(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA_SHIFT))&DAC_DATL_DATA_MASK)
/* DATH Bit Fields */
#define DAC_DATH_DATA_MASK 0xFu
#define DAC_DATH_DATA_SHIFT 0
#define DAC_DATH_DATA(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA_SHIFT))&DAC_DATH_DATA_MASK)
/* SR Bit Fields */
#define DAC_SR_DACBFRPBF_MASK 0x1u
#define DAC_SR_DACBFRPBF_SHIFT 0
#define DAC_SR_DACBFRPTF_MASK 0x2u
#define DAC_SR_DACBFRPTF_SHIFT 1
#define DAC_SR_DACBFWMF_MASK 0x4u
#define DAC_SR_DACBFWMF_SHIFT 2
/* C0 Bit Fields */
#define DAC_C0_DACBBIEN_MASK 0x1u
#define DAC_C0_DACBBIEN_SHIFT 0
#define DAC_C0_DACBTIEN_MASK 0x2u
#define DAC_C0_DACBTIEN_SHIFT 1
#define DAC_C0_DACBWIEN_MASK 0x4u
#define DAC_C0_DACBWIEN_SHIFT 2
#define DAC_C0_LPEN_MASK 0x8u
#define DAC_C0_LPEN_SHIFT 3
#define DAC_C0_DACSWTRG_MASK 0x10u
#define DAC_C0_DACSWTRG_SHIFT 4
#define DAC_C0_DACTRGSEL_MASK 0x20u
#define DAC_C0_DACTRGSEL_SHIFT 5
#define DAC_C0_DACRFS_MASK 0x40u
#define DAC_C0_DACRFS_SHIFT 6
#define DAC_C0_DACEN_MASK 0x80u
#define DAC_C0_DACEN_SHIFT 7
/* C1 Bit Fields */
#define DAC_C1_DACBFEN_MASK 0x1u
#define DAC_C1_DACBFEN_SHIFT 0
#define DAC_C1_DACBFMD_MASK 0x6u
#define DAC_C1_DACBFMD_SHIFT 1
#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
#define DAC_C1_DACBFWM_MASK 0x18u
#define DAC_C1_DACBFWM_SHIFT 3
#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
#define DAC_C1_DMAEN_MASK 0x80u
#define DAC_C1_DMAEN_SHIFT 7
/* C2 Bit Fields */
#define DAC_C2_DACBFUP_MASK 0xFu
#define DAC_C2_DACBFUP_SHIFT 0
#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
#define DAC_C2_DACBFRP_MASK 0xF0u
#define DAC_C2_DACBFRP_SHIFT 4
#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
/*!
* @}
*/ /* end of group DAC_Register_Masks */
/* DAC - Peripheral instance base addresses */
/** Peripheral DAC0 base pointer */
#define DAC0_BASE_PTR ((DAC_MemMapPtr)0x400CC000u)
/** Array initializer of DAC peripheral base pointers */
#define DAC_BASE_PTRS { DAC0_BASE_PTR }
/* ----------------------------------------------------------------------------
-- DAC - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
* @{
*/
/* DAC - Register instance definitions */
/* DAC0 */
#define DAC0_DAT0L DAC_DATL_REG(DAC0_BASE_PTR,0)
#define DAC0_DAT0H DAC_DATH_REG(DAC0_BASE_PTR,0)
#define DAC0_DAT1L DAC_DATL_REG(DAC0_BASE_PTR,1)
#define DAC0_DAT1H DAC_DATH_REG(DAC0_BASE_PTR,1)
#define DAC0_DAT2L DAC_DATL_REG(DAC0_BASE_PTR,2)
#define DAC0_DAT2H DAC_DATH_REG(DAC0_BASE_PTR,2)
#define DAC0_DAT3L DAC_DATL_REG(DAC0_BASE_PTR,3)
#define DAC0_DAT3H DAC_DATH_REG(DAC0_BASE_PTR,3)
#define DAC0_DAT4L DAC_DATL_REG(DAC0_BASE_PTR,4)
#define DAC0_DAT4H DAC_DATH_REG(DAC0_BASE_PTR,4)
#define DAC0_DAT5L DAC_DATL_REG(DAC0_BASE_PTR,5)
#define DAC0_DAT5H DAC_DATH_REG(DAC0_BASE_PTR,5)
#define DAC0_DAT6L DAC_DATL_REG(DAC0_BASE_PTR,6)
#define DAC0_DAT6H DAC_DATH_REG(DAC0_BASE_PTR,6)
#define DAC0_DAT7L DAC_DATL_REG(DAC0_BASE_PTR,7)
#define DAC0_DAT7H DAC_DATH_REG(DAC0_BASE_PTR,7)
#define DAC0_DAT8L DAC_DATL_REG(DAC0_BASE_PTR,8)
#define DAC0_DAT8H DAC_DATH_REG(DAC0_BASE_PTR,8)
#define DAC0_DAT9L DAC_DATL_REG(DAC0_BASE_PTR,9)
#define DAC0_DAT9H DAC_DATH_REG(DAC0_BASE_PTR,9)
#define DAC0_DAT10L DAC_DATL_REG(DAC0_BASE_PTR,10)
#define DAC0_DAT10H DAC_DATH_REG(DAC0_BASE_PTR,10)
#define DAC0_DAT11L DAC_DATL_REG(DAC0_BASE_PTR,11)
#define DAC0_DAT11H DAC_DATH_REG(DAC0_BASE_PTR,11)
#define DAC0_DAT12L DAC_DATL_REG(DAC0_BASE_PTR,12)
#define DAC0_DAT12H DAC_DATH_REG(DAC0_BASE_PTR,12)
#define DAC0_DAT13L DAC_DATL_REG(DAC0_BASE_PTR,13)
#define DAC0_DAT13H DAC_DATH_REG(DAC0_BASE_PTR,13)
#define DAC0_DAT14L DAC_DATL_REG(DAC0_BASE_PTR,14)
#define DAC0_DAT14H DAC_DATH_REG(DAC0_BASE_PTR,14)
#define DAC0_DAT15L DAC_DATL_REG(DAC0_BASE_PTR,15)
#define DAC0_DAT15H DAC_DATH_REG(DAC0_BASE_PTR,15)
#define DAC0_SR DAC_SR_REG(DAC0_BASE_PTR)
#define DAC0_C0 DAC_C0_REG(DAC0_BASE_PTR)
#define DAC0_C1 DAC_C1_REG(DAC0_BASE_PTR)
#define DAC0_C2 DAC_C2_REG(DAC0_BASE_PTR)
/* DAC - Register array accessors */
#define DAC0_DATL(index) DAC_DATL_REG(DAC0_BASE_PTR,index)
#define DAC0_DATH(index) DAC_DATH_REG(DAC0_BASE_PTR,index)
/*!
* @}
*/ /* end of group DAC_Register_Accessor_Macros */
/*!
* @}
*/ /* end of group DAC_Peripheral */
/* ----------------------------------------------------------------------------
-- DMA
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Peripheral DMA
* @{
*/
/** DMA - Peripheral register structure */
typedef struct DMA_MemMap {
uint32_t CR; /**< Control Register, offset: 0x0 */
uint32_t ES; /**< Error Status Register, offset: 0x4 */
uint8_t RESERVED_0[4];
uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
uint8_t RESERVED_1[4];
uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
uint8_t RESERVED_2[4];
uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
uint8_t RESERVED_3[4];
uint32_t ERR; /**< Error Register, offset: 0x2C */
uint8_t RESERVED_4[4];
uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
uint8_t RESERVED_5[200];
uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
uint8_t RESERVED_6[3824];
struct { /* offset: 0x1000, array step: 0x20 */
uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
union { /* offset: 0x1008, array step: 0x20 */
uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
};
uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
union { /* offset: 0x1016, array step: 0x20 */
uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
};
uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
union { /* offset: 0x101E, array step: 0x20 */
uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
};
} TCD[16];
} volatile *DMA_MemMapPtr;
/* ----------------------------------------------------------------------------
-- DMA - Register accessor macros
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
* @{
*/
/* DMA - Register accessors */
#define DMA_CR_REG(base) ((base)->CR)
#define DMA_ES_REG(base) ((base)->ES)
#define DMA_ERQ_REG(base) ((base)->ERQ)
#define DMA_EEI_REG(base) ((base)->EEI)
#define DMA_CEEI_REG(base) ((base)->CEEI)
#define DMA_SEEI_REG(base) ((base)->SEEI)
#define DMA_CERQ_REG(base) ((base)->CERQ)
#define DMA_SERQ_REG(base) ((base)->SERQ)
#define DMA_CDNE_REG(base) ((base)->CDNE)
#define DMA_SSRT_REG(base) ((base)->SSRT)
#define DMA_CERR_REG(base) ((base)->CERR)
#define DMA_CINT_REG(base) ((base)->CINT)
#define DMA_INT_REG(base) ((base)->INT)
#define DMA_ERR_REG(base) ((base)->ERR)
#define DMA_HRS_REG(base) ((base)->HRS)
#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
/*!
* @}
*/ /* end of group DMA_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- DMA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Masks DMA Register Masks
* @{
*/
/* CR Bit Fields */
#define DMA_CR_EDBG_MASK 0x2u
#define DMA_CR_EDBG_SHIFT 1
#define DMA_CR_ERCA_MASK 0x4u
#define DMA_CR_ERCA_SHIFT 2
#define DMA_CR_HOE_MASK 0x10u
#define DMA_CR_HOE_SHIFT 4
#define DMA_CR_HALT_MASK 0x20u
#define DMA_CR_HALT_SHIFT 5
#define DMA_CR_CLM_MASK 0x40u
#define DMA_CR_CLM_SHIFT 6
#define DMA_CR_EMLM_MASK 0x80u
#define DMA_CR_EMLM_SHIFT 7
#define DMA_CR_ECX_MASK 0x10000u
#define DMA_CR_ECX_SHIFT 16
#define DMA_CR_CX_MASK 0x20000u
#define DMA_CR_CX_SHIFT 17
/* ES Bit Fields */
#define DMA_ES_DBE_MASK 0x1u
#define DMA_ES_DBE_SHIFT 0
#define DMA_ES_SBE_MASK 0x2u
#define DMA_ES_SBE_SHIFT 1
#define DMA_ES_SGE_MASK 0x4u
#define DMA_ES_SGE_SHIFT 2
#define DMA_ES_NCE_MASK 0x8u
#define DMA_ES_NCE_SHIFT 3
#define DMA_ES_DOE_MASK 0x10u
#define DMA_ES_DOE_SHIFT 4
#define DMA_ES_DAE_MASK 0x20u
#define DMA_ES_DAE_SHIFT 5
#define DMA_ES_SOE_MASK 0x40u
#define DMA_ES_SOE_SHIFT 6
#define DMA_ES_SAE_MASK 0x80u
#define DMA_ES_SAE_SHIFT 7
#define DMA_ES_ERRCHN_MASK 0xF00u
#define DMA_ES_ERRCHN_SHIFT 8
#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
#define DMA_ES_CPE_MASK 0x4000u
#define DMA_ES_CPE_SHIFT 14
#define DMA_ES_ECX_MASK 0x10000u
#define DMA_ES_ECX_SHIFT 16
#define DMA_ES_VLD_MASK 0x80000000u
#define DMA_ES_VLD_SHIFT 31
/* ERQ Bit Fields */
#define DMA_ERQ_ERQ0_MASK 0x1u
#define DMA_ERQ_ERQ0_SHIFT 0
#define DMA_ERQ_ERQ1_MASK 0x2u
#define DMA_ERQ_ERQ1_SHIFT 1
#define DMA_ERQ_ERQ2_MASK 0x4u
#define DMA_ERQ_ERQ2_SHIFT 2
#define DMA_ERQ_ERQ3_MASK 0x8u
#define DMA_ERQ_ERQ3_SHIFT 3
#define DMA_ERQ_ERQ4_MASK 0x10u
#define DMA_ERQ_ERQ4_SHIFT 4
#define DMA_ERQ_ERQ5_MASK 0x20u
#define DMA_ERQ_ERQ5_SHIFT 5
#define DMA_ERQ_ERQ6_MASK 0x40u
#define DMA_ERQ_ERQ6_SHIFT 6
#define DMA_ERQ_ERQ7_MASK 0x80u
#define DMA_ERQ_ERQ7_SHIFT 7
#define DMA_ERQ_ERQ8_MASK 0x100u
#define DMA_ERQ_ERQ8_SHIFT 8
#define DMA_ERQ_ERQ9_MASK 0x200u
#define DMA_ERQ_ERQ9_SHIFT 9
#define DMA_ERQ_ERQ10_MASK 0x400u
#define DMA_ERQ_ERQ10_SHIFT 10
#define DMA_ERQ_ERQ11_MASK 0x800u
#define DMA_ERQ_ERQ11_SHIFT 11
#define DMA_ERQ_ERQ12_MASK 0x1000u
#define DMA_ERQ_ERQ12_SHIFT 12
#define DMA_ERQ_ERQ13_MASK 0x2000u
#define DMA_ERQ_ERQ13_SHIFT 13
#define DMA_ERQ_ERQ14_MASK 0x4000u
#define DMA_ERQ_ERQ14_SHIFT 14
#define DMA_ERQ_ERQ15_MASK 0x8000u
#define DMA_ERQ_ERQ15_SHIFT 15
/* EEI Bit Fields */
#define DMA_EEI_EEI0_MASK 0x1u
#define DMA_EEI_EEI0_SHIFT 0
#define DMA_EEI_EEI1_MASK 0x2u
#define DMA_EEI_EEI1_SHIFT 1
#define DMA_EEI_EEI2_MASK 0x4u
#define DMA_EEI_EEI2_SHIFT 2
#define DMA_EEI_EEI3_MASK 0x8u
#define DMA_EEI_EEI3_SHIFT 3
#define DMA_EEI_EEI4_MASK 0x10u
#define DMA_EEI_EEI4_SHIFT 4
#define DMA_EEI_EEI5_MASK 0x20u
#define DMA_EEI_EEI5_SHIFT 5
#define DMA_EEI_EEI6_MASK 0x40u
#define DMA_EEI_EEI6_SHIFT 6
#define DMA_EEI_EEI7_MASK 0x80u
#define DMA_EEI_EEI7_SHIFT 7
#define DMA_EEI_EEI8_MASK 0x100u
#define DMA_EEI_EEI8_SHIFT 8
#define DMA_EEI_EEI9_MASK 0x200u
#define DMA_EEI_EEI9_SHIFT 9
#define DMA_EEI_EEI10_MASK 0x400u
#define DMA_EEI_EEI10_SHIFT 10
#define DMA_EEI_EEI11_MASK 0x800u
#define DMA_EEI_EEI11_SHIFT 11
#define DMA_EEI_EEI12_MASK 0x1000u
#define DMA_EEI_EEI12_SHIFT 12
#define DMA_EEI_EEI13_MASK 0x2000u
#define DMA_EEI_EEI13_SHIFT 13
#define DMA_EEI_EEI14_MASK 0x4000u
#define DMA_EEI_EEI14_SHIFT 14
#define DMA_EEI_EEI15_MASK 0x8000u
#define DMA_EEI_EEI15_SHIFT 15
/* CEEI Bit Fields */
#define DMA_CEEI_CEEI_MASK 0xFu
#define DMA_CEEI_CEEI_SHIFT 0
#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
#define DMA_CEEI_CAEE_MASK 0x40u
#define DMA_CEEI_CAEE_SHIFT 6
#define DMA_CEEI_NOP_MASK 0x80u
#define DMA_CEEI_NOP_SHIFT 7
/* SEEI Bit Fields */
#define DMA_SEEI_SEEI_MASK 0xFu
#define DMA_SEEI_SEEI_SHIFT 0
#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
#define DMA_SEEI_SAEE_MASK 0x40u
#define DMA_SEEI_SAEE_SHIFT 6
#define DMA_SEEI_NOP_MASK 0x80u
#define DMA_SEEI_NOP_SHIFT 7
/* CERQ Bit Fields */
#define DMA_CERQ_CERQ_MASK 0xFu
#define DMA_CERQ_CERQ_SHIFT 0
#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
#define DMA_CERQ_CAER_MASK 0x40u
#define DMA_CERQ_CAER_SHIFT 6
#define DMA_CERQ_NOP_MASK 0x80u
#define DMA_CERQ_NOP_SHIFT 7
/* SERQ Bit Fields */
#define DMA_SERQ_SERQ_MASK 0xFu
#define DMA_SERQ_SERQ_SHIFT 0
#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
#define DMA_SERQ_SAER_MASK 0x40u
#define DMA_SERQ_SAER_SHIFT 6
#define DMA_SERQ_NOP_MASK 0x80u
#define DMA_SERQ_NOP_SHIFT 7
/* CDNE Bit Fields */
#define DMA_CDNE_CDNE_MASK 0xFu
#define DMA_CDNE_CDNE_SHIFT 0
#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
#define DMA_CDNE_CADN_MASK 0x40u
#define DMA_CDNE_CADN_SHIFT 6
#define DMA_CDNE_NOP_MASK 0x80u
#define DMA_CDNE_NOP_SHIFT 7
/* SSRT Bit Fields */
#define DMA_SSRT_SSRT_MASK 0xFu
#define DMA_SSRT_SSRT_SHIFT 0
#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
#define DMA_SSRT_SAST_MASK 0x40u
#define DMA_SSRT_SAST_SHIFT 6
#define DMA_SSRT_NOP_MASK 0x80u
#define DMA_SSRT_NOP_SHIFT 7
/* CERR Bit Fields */
#define DMA_CERR_CERR_MASK 0xFu
#define DMA_CERR_CERR_SHIFT 0
#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
#define DMA_CERR_CAEI_MASK 0x40u
#define DMA_CERR_CAEI_SHIFT 6
#define DMA_CERR_NOP_MASK 0x80u
#define DMA_CERR_NOP_SHIFT 7
/* CINT Bit Fields */
#define DMA_CINT_CINT_MASK 0xFu
#define DMA_CINT_CINT_SHIFT 0
#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
#define DMA_CINT_CAIR_MASK 0x40u