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r82xx: register caching
1 parent a7caaac commit 4198f7d

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2 files changed

+14
-5
lines changed

2 files changed

+14
-5
lines changed

include/tuner_r82xx.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,7 @@ struct r82xx_priv {
8686
int has_lock;
8787
int init_done;
8888
int disable_dither;
89+
int reg_cache;
8990

9091
/* Store current mode */
9192
uint32_t delsys;

src/tuner_r82xx.c

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -286,11 +286,6 @@ static int r82xx_write(struct r82xx_priv *priv, uint8_t reg, const uint8_t *val,
286286
return 0;
287287
}
288288

289-
static int r82xx_write_reg(struct r82xx_priv *priv, uint8_t reg, uint8_t val)
290-
{
291-
return r82xx_write(priv, reg, &val, 1);
292-
}
293-
294289
static int r82xx_read_cache_reg(struct r82xx_priv *priv, int reg)
295290
{
296291
reg -= REG_SHADOW_START;
@@ -301,6 +296,13 @@ static int r82xx_read_cache_reg(struct r82xx_priv *priv, int reg)
301296
return -1;
302297
}
303298

299+
static int r82xx_write_reg(struct r82xx_priv *priv, uint8_t reg, uint8_t val)
300+
{
301+
if (priv->reg_cache && r82xx_read_cache_reg(priv, reg) == val)
302+
return 0;
303+
return r82xx_write(priv, reg, &val, 1);
304+
}
305+
304306
static int r82xx_write_reg_mask(struct r82xx_priv *priv, uint8_t reg, uint8_t val,
305307
uint8_t bit_mask)
306308
{
@@ -311,6 +313,8 @@ static int r82xx_write_reg_mask(struct r82xx_priv *priv, uint8_t reg, uint8_t va
311313

312314
val = (rc & ~bit_mask) | (val & bit_mask);
313315

316+
if (priv->reg_cache && r82xx_read_cache_reg(priv, reg) == val)
317+
return 0;
314318
return r82xx_write(priv, reg, &val, 1);
315319
}
316320

@@ -1090,6 +1094,7 @@ int r82xx_standby(struct r82xx_priv *priv)
10901094
if (!priv->init_done)
10911095
return 0;
10921096

1097+
priv->reg_cache = 0;
10931098
rc = r82xx_write_reg(priv, 0x06, 0xb1);
10941099
if (rc < 0)
10951100
return rc;
@@ -1125,6 +1130,7 @@ int r82xx_standby(struct r82xx_priv *priv)
11251130
/* Force initial calibration */
11261131
priv->type = -1;
11271132

1133+
priv->reg_cache = 1;
11281134
return rc;
11291135
}
11301136

@@ -1199,6 +1205,7 @@ int r82xx_init(struct r82xx_priv *priv)
11991205
priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
12001206

12011207
/* Initialize registers */
1208+
priv->reg_cache = 0;
12021209
rc = r82xx_write(priv, 0x05,
12031210
r82xx_init_array, sizeof(r82xx_init_array));
12041211

@@ -1212,6 +1219,7 @@ int r82xx_init(struct r82xx_priv *priv)
12121219
rc |= r82xx_sysfreq_sel(priv, 0, TUNER_DIGITAL_TV, SYS_DVBT);
12131220

12141221
priv->init_done = 1;
1222+
priv->reg_cache = 1;
12151223

12161224
err:
12171225
if (rc < 0)

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