From 07856eb0478a394b065e8a9a9966cdd4df206f4f Mon Sep 17 00:00:00 2001
From: Keiichi Watanabe <keiichiw@chromium.org>
Date: Mon, 26 Oct 2020 16:26:39 +0900
Subject: [PATCH] implement `RegId` for x86_64

This is one of action items in issue #29.
---
 src/arch/x86/mod.rs    |  9 +++-----
 src/arch/x86/reg/id.rs | 47 ++++++++++++++++++++++++++++++++++++++++--
 2 files changed, 48 insertions(+), 8 deletions(-)

diff --git a/src/arch/x86/mod.rs b/src/arch/x86/mod.rs
index 2d94e34d..f0e1fdfe 100644
--- a/src/arch/x86/mod.rs
+++ b/src/arch/x86/mod.rs
@@ -10,15 +10,12 @@ pub mod reg;
 /// Check out the [module level docs](../index.html#whats-with-regidimpl) for
 /// more info about the `RegIdImpl` type parameter.
 #[allow(non_camel_case_types)]
-pub enum X86_64_SSE<RegIdImpl: RegId> {
-    #[doc(hidden)]
-    _Marker(core::marker::PhantomData<RegIdImpl>),
-}
+pub enum X86_64_SSE {}
 
-impl<RegIdImpl: RegId> Arch for X86_64_SSE<RegIdImpl> {
+impl Arch for X86_64_SSE {
     type Usize = u64;
     type Registers = reg::X86_64CoreRegs;
-    type RegId = RegIdImpl;
+    type RegId = reg::id::X86_64CoreRegId;
 
     fn target_description_xml() -> Option<&'static str> {
         Some(
diff --git a/src/arch/x86/reg/id.rs b/src/arch/x86/reg/id.rs
index 4cbbb100..0025cbfc 100644
--- a/src/arch/x86/reg/id.rs
+++ b/src/arch/x86/reg/id.rs
@@ -1,5 +1,48 @@
+use crate::arch::RegId;
+
 // TODO: Add proper `RegId` implementation. See [issue #29](https://github.com/daniel5151/gdbstub/issues/29)
 // pub enum X86RegId {}
 
-// TODO: Add proper `RegId` implementation. See [issue #29](https://github.com/daniel5151/gdbstub/issues/29)
-// pub enum X86_64RegId {}
+/// 64-bit x86 core + SSE register identifier.
+///
+/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-core.xml
+/// Additionally: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-sse.xml
+#[derive(Debug, Clone, Copy)]
+#[non_exhaustive]
+pub enum X86_64CoreRegId {
+    /// General purpose registers: RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, r8-r15
+    Gpr(u8),
+    /// Instruction pointer
+    Rip,
+    /// Status register
+    Eflags,
+    /// Segment registers: CS, SS, DS, ES, FS, GS
+    Segment(u8),
+    /// FPU registers: ST0 through ST7
+    St(u8),
+    /// FPU internal registers: FCTRL, FSTAT, FTAG, FISEG, FIOFF, FOSEG, FOOFF, FOP
+    Fpu(u8),
+    /// SIMD Registers: XMM0 through XMM15
+    Xmm(u8),
+    /// SSE Status/Control Register
+    Mxcsr,
+}
+
+impl RegId for X86_64CoreRegId {
+    fn from_raw_id(id: usize) -> Option<(Self, usize)> {
+        use crate::arch::x86::reg::id::X86_64CoreRegId::*;
+
+        let r = match id {
+            0..=15 => (Gpr(id as u8), 8),
+            16 => (Rip, 4),
+            17 => (Eflags, 8),
+            18..=23 => (Segment(id as u8), 4),
+            24..=31 => (St(id as u8), 10),
+            32..=40 => (Fpu(id as u8), 4),
+            41..=55 => (Xmm(id as u8), 16),
+            56 => (Mxcsr, 4),
+            _ => return None,
+        };
+        Some(r)
+    }
+}