--# reset_generator.vhdl - Reset generator for testbench stimuli
--#
--# DEPENDENCIES: 
--#
--# DESCRIPTION:
--#  
--#  
--------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;

entity reset_generator is
  generic(
  
    RESET_ACTIVE_LEVEL : std_logic := '1'; --# Asynchronous reset level
    PERIOD : time := 20 ns;                --# Reset time
    LENGTH : natural := 1                  --# Reset hold length
  
  );
  port(
  
    rst : out std_logic  --# Reset signal
  
  );
end entity reset_generator;

architecture archi of reset_generator is

begin

  Rst <= RESET_ACTIVE_LEVEL , not RESET_ACTIVE_LEVEL after LENGTH * PERIOD;

end architecture archi;