diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index c3cc0c0f41..3f5c8bb303 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -557,15 +557,6 @@ Environment variables
   The register would be flushed to HW usually when the write-combining buffer
   becomes full, but it depends on CPU design.
 
-  Except for vectorized Tx burst routines, a write memory barrier is enforced
-  after updating the register so that the update can be immediately visible to
-  HW.
-
-  When vectorized Tx burst is called, the barrier is set only if the burst size
-  is not aligned to MLX5_VPMD_TX_MAX_BURST. However, setting this environmental
-  variable will bring better latency even though the maximum throughput can
-  slightly decline.
-
 Run-time configuration
 ~~~~~~~~~~~~~~~~~~~~~~