From a8cd194a66b988bcdfa76b77b7e918d3fa8da28a Mon Sep 17 00:00:00 2001 From: Dhiru Kholia Date: Fri, 14 Jan 2022 10:55:22 +0530 Subject: [PATCH] Misc. dirty hacks - Fix for https://github.com/buserror/simavr/issues/461 Borrowed from https://stuvel.eu/post/2021-04-27-atmega328pb-on-gcc/ - Add easy to understand usage instructions - Add `ArduinoUniqueID` example and binaries - Fix for reading the 'Serial Number' from ATmega328P --- ArduinoUniqueID.ino.elf | Bin 0 -> 24136 bytes ArduinoUniqueID.ino.hex | 117 +++ ArduinoUniqueID/ArduinoUniqueID.ino | 24 + README.md | 166 +++- simavr/cores/avr/iom328pb.h | 1220 +++++++++++++++++++++++++++ simavr/sim/sim_core.c | 9 +- 6 files changed, 1525 insertions(+), 11 deletions(-) create mode 100755 ArduinoUniqueID.ino.elf create mode 100644 ArduinoUniqueID.ino.hex create mode 100644 ArduinoUniqueID/ArduinoUniqueID.ino create mode 100644 simavr/cores/avr/iom328pb.h diff --git a/ArduinoUniqueID.ino.elf b/ArduinoUniqueID.ino.elf new file mode 100755 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+:0C0700000590F491E02D0994F894FFCFCF +:10070C0000000000FF005F008C004C01BD009B004E +:10071C00AF003000696E2073657475702829000D68 +:0C072C000A00696E206C6F6F70282900B5 +:00000001FF diff --git a/ArduinoUniqueID/ArduinoUniqueID.ino b/ArduinoUniqueID/ArduinoUniqueID.ino new file mode 100644 index 000000000..063477fe7 --- /dev/null +++ b/ArduinoUniqueID/ArduinoUniqueID.ino @@ -0,0 +1,24 @@ +// https://microchipsupport.force.com/s/article/Serial-number-in-AVR---Mega-Tiny-devices + +#include + +void setup() +{ + Serial.begin(9600); + Serial.println("in setup()"); +} + +void loop() +{ + delay(1000); + Serial.println("in loop()"); + + unsigned int UniqueIDsize = 9; + for (size_t i = 0; i < UniqueIDsize; i++) + { + byte n = boot_signature_byte_get(0x0E + i + (UniqueIDsize == 9 && i > 5 ? 1 : 0)); + Serial.print(n < 16 ? "0" : ""); + Serial.print(n, HEX); + } + Serial.println(); +} diff --git a/README.md b/README.md index 489ddf1a5..60b9114bc 100644 --- a/README.md +++ b/README.md @@ -1,13 +1,13 @@ simavr - a lean and mean Atmel AVR simulator for linux ====== -_simavr_ is a new AVR simulator for linux, or any platform that uses avr-gcc. It uses +_simavr_ is a new AVR simulator for linux, or any platform that uses avr-gcc. It uses avr-gcc's own register definition to simplify creating new targets for supported AVR -devices. The core was made to be small and compact, and hackable so allow quick -prototyping of an AVR project. The AVR core is now stable for use with parts -with <= 128KB flash, and with preliminary support for the bigger parts. The -simulator loads ELF files directly, and there is even a way to specify simulation -parameters directly in the emulated code using an .elf section. You can also +devices. The core was made to be small and compact, and hackable so allow quick +prototyping of an AVR project. The AVR core is now stable for use with parts +with <= 128KB flash, and with preliminary support for the bigger parts. The +simulator loads ELF files directly, and there is even a way to specify simulation +parameters directly in the emulated code using an .elf section. You can also load multipart HEX files. Installation @@ -60,7 +60,7 @@ Emulated Cores (very easy to add new ones!) Extras: ------- * fully working _gdb_ support including some pretty cool “passive modes”. -* There is also very easy support for “VCD” (Value Change Dump) that can be visualized +* There is also very easy support for “VCD” (Value Change Dump) that can be visualized graphically as “waveforms” with tools like _gtkwave_ (see below). * There are a few examples of real life firmwares running on simavr, including OpenGL rendering of the display… * There is support for _Arduino_, but no IDE integration @@ -78,7 +78,7 @@ Contributing Patches are always welcome! Please submit your changes via Github pull requests. -VCD Support -- built in logic analyzer +VCD Support -- built in logic analyzer ----------- _simavr_ can output most of its pins, firmware variables, interrupts and a few other things as signals to be dumped into a file that can be plotted using gtkwave for @@ -117,12 +117,12 @@ And when the file is loaded in gtkwave, you see: ![gtkwave](https://github.com/buserror-uk/simavr/raw/master/doc/img/gtkwave1.png) You get a very precise timing breakdown of any change that you add to the trace, down -to the AVR cycle. +to the AVR cycle. Example: -------- _simavr_ is really made to be the center for emulating your own AVR projects, not just -a debugger, but also the emulating the peripherals you will use in your firmware, so +a debugger, but also the emulating the peripherals you will use in your firmware, so you can test and develop offline, and now and then try it on the hardware. You can also use _simavr_ to do test units on your shipping firmware to validate it @@ -149,3 +149,149 @@ And this is a gtkwave trace of what the firmware is doing. You can zoom in, meas in gtkwave, select trades to see etc. Quite a few other examples are available! + +Usage +----- + +Install build dependencies: + +``` +sudo apt-get install libelf-dev freeglut3 freeglut3-dev gcc-avr avr-libc gcc make +``` + +Clone and build the latest `simavr` code: + +``` +git clone https://github.com/kholia/simavr.git + +cd simavr + +make +``` + +Run sample programs: + +``` +./simavr/run_avr -f 16000000 -m atmega328p ArduinoUniqueID.ino.elf + +./simavr/run_avr -f 16000000 -m atmega328p ArduinoUniqueID.ino.hex +``` + +Sample run: + +``` +$ ./simavr/run_avr -f 16000000 -m atmega328p ArduinoUniqueID.ino.hex +Loaded 1966 .text at address 0x0 +Loaded 42 .data +in setup().. +in loop().. +5D000C945D00945D00.. +in loop().. +5D000C945D00945D00.. +in loop().. +5D000C945D00945D00.. +in loop().. +5D000C945D00945D00.. +... +``` + +GDB usage: + +``` +$ ./simavr/run_avr -g -f 16000000 -m atmega328p ArduinoUniqueID.ino.elf +Loaded 1966 .text at address 0x0 +Loaded 42 .data +avr_gdb_init listening on port 1234 +... + +$ avr-gdb ArduinoUniqueID.ino.elf +GNU gdb (GDB) 10.1.90.20210103-git +... +(gdb) target remote :1234 +Remote debugging using :1234 +0x00000000 in __vectors () +(gdb) break main +(gdb) c +Continuing. + +Breakpoint 1, main () at /home/.../hardware/avr/1.8.4/cores/arduino/main.cpp:35 +35 init(); +(gdb) +``` + + +``` +$ avr-objdump -S -j .sec1 -d -C -m avr5 ArduinoUniqueID.ino.hex +... + 616: 10 f4 brcc .+4 ; 0x61c + 618: f0 e0 ldi r31, 0x00 ; 0 + 61a: e0 e0 ldi r30, 0x00 ; 0 + 61c: be 01 movw r22, r28 + 61e: 62 5f subi r22, 0xF2 ; 242 + 620: 7f 4f sbci r23, 0xFF ; 255 + 622: e6 0f add r30, r22 + 624: f7 1f adc r31, r23 + 626: 10 93 57 00 sts 0x0057, r17 ; 0x800057 <-- try to find this ;) + 62a: e4 91 lpm r30, Z + 62c: 6e 2f mov r22, r30 + 62e: 70 e0 ldi r23, 0x00 ; 0 + 630: 90 e0 ldi r25, 0x00 ; 0 + 632: 80 e0 ldi r24, 0x00 ; 0 + 634: 4a e0 ldi r20, 0x0A ; 10 + 636: 0e 94 9e 01 call 0x33c ; 0x33c +``` + +Tracing patch: + +```diff +diff --git a/simavr/sim/sim_core.c b/simavr/sim/sim_core.c +index 4bb2543..118afb5 100644 +--- a/simavr/sim/sim_core.c ++++ b/simavr/sim/sim_core.c +@@ -1013,6 +1013,8 @@ run_one_again: + uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8); + int op = opcode & 1; + STATE("lpm %s, (Z[%04x]%s)\n", avr_regname(d), z, op ? "+" : ""); ++ printf("Opcode -> %x\n", opcode); ++ printf("lpm %s, (Z[%04x]%s)\n", avr_regname(d), z, op ? "+" : ""); + _avr_set_r(avr, d, avr->flash[z]); + if (op) { + z++; +``` + +``` +$ ./simavr/run_avr -m atmega328pb -f 16000000 ArduinoUniqueID8.ino.elf +Loaded 1878 .text at address 0x0 +Loaded 34 .data +... +Opcode -> 91e4 +lpm ZL, (Z[000e]) +Opcode -> 91e4 +lpm ZL, (Z[000f]) +Opcode -> 91e4 +lpm ZL, (Z[0010]) +Opcode -> 91e4 +lpm ZL, (Z[0011]) +Opcode -> 91e4 +lpm ZL, (Z[0012]) +Opcode -> 91e4 +lpm ZL, (Z[0013]) +Opcode -> 91e4 +lpm ZL, (Z[0015]) +Opcode -> 91e4 +lpm ZL, (Z[0016]) +Opcode -> 91e4 +lpm ZL, (Z[0017]) +UniqueID: 00 0C 94 5D 00 94 5D 00 .. +... +``` + +``` +$ avr-objdump -d ArduinoUniqueID8.ino.elf | grep -B 5 "e4 91" + 55a: 30 e0 ldi r19, 0x00 ; 0 + 55c: 20 e0 ldi r18, 0x00 ; 0 + 55e: e2 0f add r30, r18 + 560: f3 1f adc r31, r19 + 562: 40 93 57 00 sts 0x0057, r20 ; 0x800057 <__TEXT_REGION_LENGTH__+0x7e0057> + 566: e4 91 lpm r30, Z +``` diff --git a/simavr/cores/avr/iom328pb.h b/simavr/cores/avr/iom328pb.h new file mode 100644 index 000000000..0edc9fbe0 --- /dev/null +++ b/simavr/cores/avr/iom328pb.h @@ -0,0 +1,1220 @@ +/* + * Copyright (C) 2020, Microchip Technology Inc. and its subsidiaries ("Microchip") + * All rights reserved. + * + * This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip"). + * + * Redistribution and use in source and binary forms, with or without modification, are + * permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list of + * conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this list + * of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. Publication is not required when + * this file is used in an embedded application. + * + * 3. Microchip's name may not be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _AVR_ATMEGA328PB_H_INCLUDED +#define _AVR_ATMEGA328PB_H_INCLUDED + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom328pb.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +/* Reserved [0x0F..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define ICF4 5 + +/* Reserved [0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR0 _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR0 _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR0 _SFR_IO8(0x2E) + +#define ACSRB _SFR_IO8(0x2F) +#define ACOE 0 + +#define ACSRA _SFR_IO8(0x30) + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define XFDCSR _SFR_MEM8(0x62) +#define XFDIE 0 +#define XFDIF 1 + +/* Reserved [0x63] */ + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI0 2 +#define PRTIM1 3 +#define PRUSART1 4 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI0 7 + +#define __AVR_HAVE_PRR0 ((1<data[R_ZL] | (avr->data[R_ZH] << 8); int op = opcode & 1; STATE("lpm %s, (Z[%04x]%s)\n", avr_regname(d), z, op ? "+" : ""); - _avr_set_r(avr, d, avr->flash[z]); + printf("Opcode -> %x z -> %hu\n", opcode, z); + printf("lpm %s, (Z[%04x]%s)\n", avr_regname(d), z, op ? "+" : ""); + if (z >= 14 && z <= 23) { + _avr_set_r(avr, d, 0); + } + else { + _avr_set_r(avr, d, avr->flash[z]); + } if (op) { z++; _avr_set_r16le_hl(avr, R_ZL, z);