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1 parent 8c37bb7 commit cab600f79ccd9ba6f82b34eb23e07ec51cc05514 kiarashplusplus committed Dec 13, 2012
Showing 541 changed files with 3,211 additions and 502 deletions.
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@@ -1,12 +1,14 @@
-/*
-
- user input:
+////////////////////////////////////////////////////////////////////////////////
+// Engineer: Kiarash Adl
+// Module Name: Session Module
+////////////////////////////////////////////////////////////////////////////////
+/*
+ possible user input:
call phone number 5'h1
answer call 5'h2
disconnect phone number 5'h5
voicmail 5'h3
-
*/
module session (input clk, input reset, input [7:0] phoneNum, input [4:0] userInp,
@@ -24,17 +26,17 @@ module session (input clk, input reset, input [7:0] phoneNum, input [4:0] userIn
reg [3:0] state=0;
- assign current_state = state;
+ assign current_state = state;
- parameter s_idle=4'd0;
+ parameter s_idle=4'd0;
parameter s_calling=4'd1;
parameter s_connected=4'd2;
parameter s_noAnswer=4'd3;
parameter s_voicemail=4'd4;
parameter s_connectedToVoice=4'd5;
parameter s_ringing=4'd6;
- reg [7:0] phone;
+ reg [7:0] phone;
reg spkBuffer_wr_en=0;
wire [15:0] spkBufferIn;
@@ -171,7 +173,7 @@ module session (input clk, input reset, input [7:0] phoneNum, input [4:0] userIn
end
- s_noAnswer: begin
+ s_noAnswer: begin //UI needs this state change
state<=s_idle;
end
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@@ -1,23 +1,8 @@
-//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 17:21:17 12/11/2012
-// Design Name:
-// Module Name: combinedTransport
-// Project Name:
-// Target Devices:
-// Tool versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
+// Engineer: Kiarash Adl
+// Module: combinedTransport
//////////////////////////////////////////////////////////////////////////////////
+
module combinedTransport #(parameter packetSize=16) //in bytes
(input clk, input reset, input [1:0] cmd, input [15:0] data,
output [7:0] packetOut, input dummyBufferRd,output busy,
@@ -1,26 +1,7 @@
-`timescale 1ns / 1ps
-
-////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 17:43:30 12/11/2012
-// Design Name: combinedTransport
-// Module Name: /afs/athena.mit.edu/user/k/i/kiarash/Documents/6.111/FPGA_Telephony/my jizz//combinedTransport_tb.v
-// Project Name: transport
-// Target Device:
-// Tool versions:
-// Description:
-//
-// Verilog Test Fixture created by ISE for module: combinedTransport
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
-////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////
+// Engineer: Kiarash Adl
+// Module: combinedTransport test bench
+//////////////////////////////////////////////////////////////////////////////////
module combinedTransport_tb;
@@ -1,30 +1,19 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 01:12:05 12/10/2012
-// Design Name:
-// Module Name: connectedSys
-// Project Name:
-// Target Devices:
-// Tool versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
-//////////////////////////////////////////////////////////////////////////////////
-module complete(
- input clk, input reset,
+////////////////////////////////////////////////////////////////////////////////
+// Engineer: Kiarash Adl
+// Module Name: CompleteTest Module
+////////////////////////////////////////////////////////////////////////////////
+
+module complete(
+ input clk, input reset,
input [3:0] oneInp,
input [3:0] twoInp,
output [3:0] onecurrent_state,
output [3:0] twocurrent_state
);
+
+//session "one" is connected to transport "sender" and the result is connected to transportRcv "recieve"
+// then there sesult is connected to session "two" ... session "two" is then outputs data to transport "s2" and the packets will
+// be recieved by transportRcv "r2" which outputs the result to session "one".
wire [4:0] oneuserInp;
assign oneuserInp={1'b0,oneInp};
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@@ -1,25 +1,6 @@
-`timescale 1ns / 1ps
-
////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 15:43:25 12/10/2012
-// Design Name: complete
-// Module Name: /afs/athena.mit.edu/user/k/i/kiarash/Documents/6.111/FPGA_Telephony/my jizz//complete_tb.v
-// Project Name: transport
-// Target Device:
-// Tool versions:
-// Description:
-//
-// Verilog Test Fixture created by ISE for module: complete
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
+// Engineer: Kiarash Adl
+// Module Name: CompleteTest test bench
////////////////////////////////////////////////////////////////////////////////
module complete_tb;
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