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commit cab600f79ccd9ba6f82b34eb23e07ec51cc05514 1 parent 8c37bb7
kiarashplusplus authored
Showing with 2,894 additions and 502 deletions.
  1. 0  {my jizz → session and transport}/1
  2. +10 −8 {my jizz → session and transport}/Session.v
  3. 0  {my jizz → session and transport}/Session.v.bak
  4. 0  {my jizz → session and transport}/Session.v~
  5. 0  {my jizz → session and transport}/_xmsgs/ngcbuild.xmsgs
  6. 0  {my jizz → session and transport}/_xmsgs/xst.xmsgs
  7. 0  {my jizz → session and transport}/audioBuffer.asy
  8. 0  {my jizz → session and transport}/audioBuffer.ngc
  9. 0  {my jizz → session and transport}/audioBuffer.sym
  10. 0  {my jizz → session and transport}/audioBuffer.v
  11. 0  {my jizz → session and transport}/audioBuffer.veo
  12. 0  {my jizz → session and transport}/audioBuffer.vhd
  13. 0  {my jizz → session and transport}/audioBuffer.vho
  14. 0  {my jizz → session and transport}/audioBuffer.xco
  15. 0  {my jizz → session and transport}/audioBuffer_fifo_generator_v4_4_xst_1.ngc_xst.xrpt
  16. 0  {my jizz → session and transport}/audioBuffer_flist.txt
  17. 0  {my jizz → session and transport}/audioBuffer_xmdf.tcl
  18. +3 −18 {my jizz → session and transport}/combinedTransport.v
  19. +4 −23 {my jizz → session and transport}/combinedTransport_tb.v
  20. +11 −22 {my jizz → session and transport}/complete.v
  21. 0  {my jizz → session and transport}/complete.v.bak
  22. 0  {my jizz → session and transport}/complete.v~
  23. +2 −21 {my jizz → session and transport}/complete_tb.v
  24. 0  {my jizz → session and transport}/complete_tb.v~
  25. 0  {my jizz → session and transport}/connectedSys.v.bak
  26. 0  {my jizz → session and transport}/display_16hex.v
  27. 0  {my jizz → session and transport}/dummyBuffer.asy
  28. 0  {my jizz → session and transport}/dummyBuffer.ngc
  29. 0  {my jizz → session and transport}/dummyBuffer.sym
  30. 0  {my jizz → session and transport}/dummyBuffer.v
  31. 0  {my jizz → session and transport}/dummyBuffer.veo
  32. 0  {my jizz → session and transport}/dummyBuffer.vhd
  33. 0  {my jizz → session and transport}/dummyBuffer.vho
  34. 0  {my jizz → session and transport}/dummyBuffer.xco
  35. 0  {my jizz → session and transport}/dummyBuffer_fifo_generator_v4_4_xst_1.ngc_xst.xrpt
  36. 0  {my jizz → session and transport}/dummyBuffer_flist.txt
  37. 0  {my jizz → session and transport}/dummyBuffer_xmdf.tcl
  38. 0  {my jizz/transport → session and transport}/fifo_generator_ug175.pdf
  39. 0  {my jizz → session and transport}/labkit.ucf
  40. +331 −331 {my jizz → session and transport}/labkit.v
  41. 0  {my jizz → session and transport}/rcvPackets.asy
  42. 0  {my jizz → session and transport}/rcvPackets.ngc
  43. 0  {my jizz → session and transport}/rcvPackets.sym
  44. 0  {my jizz → session and transport}/rcvPackets.v
  45. 0  {my jizz → session and transport}/rcvPackets.veo
  46. 0  {my jizz → session and transport}/rcvPackets.vhd
  47. 0  {my jizz → session and transport}/rcvPackets.vho
  48. 0  {my jizz → session and transport}/rcvPackets.xco
  49. 0  {my jizz → session and transport}/rcvPackets_fifo_generator_v4_4_xst_1.ngc_xst.xrpt
  50. 0  {my jizz → session and transport}/rcvPackets_flist.txt
  51. 0  {my jizz → session and transport}/rcvPackets_readme.txt
  52. 0  {my jizz → session and transport}/rcvPackets_xmdf.tcl
  53. +2 −21 {my jizz → session and transport}/session_tb.v
  54. +245 −0 session and transport/sources/Session.v
  55. +82 −0 session and transport/sources/audioBuffer.xco
  56. +37 −0 session and transport/sources/combinedTransport.v
  57. +63 −0 session and transport/sources/combinedTransport_tb.v
  58. +176 −0 session and transport/sources/complete.v
  59. +50 −0 session and transport/sources/complete_tb.v
  60. +82 −0 session and transport/sources/dummyBuffer.xco
  61. +739 −0 session and transport/sources/labkit.ucf
  62. +356 −0 session and transport/sources/labkit.v
  63. 0  {my jizz/transport → session and transport/sources}/packetBuffer.xco
  64. +82 −0 session and transport/sources/rcvPackets.xco
  65. 0  {my jizz/transport → session and transport/sources}/readyPackets.xco
  66. +98 −0 session and transport/sources/session_tb.v
  67. +3 −21 {my jizz → session and transport/sources}/tRcv_tb.v
  68. +2 −21 {my jizz → session and transport/sources}/tSend_tb.v
  69. +5 −5 {my jizz → session and transport/sources}/tranToNet.v
  70. 0  {my jizz → session and transport/sources}/transferFIFO.xco
  71. +11 −10 {my jizz → session and transport/sources}/transportRcv.v
  72. +5 −1 {my jizz → session and transport/sources}/transportSend.v
  73. +104 −0 session and transport/tRcv_tb.v
  74. 0  {my jizz → session and transport}/tRcv_tb.v.bak
  75. +77 −0 session and transport/tSend_tb.v
  76. 0  {my jizz → session and transport}/tSend_tb.v.bak
  77. +68 −0 session and transport/tranToNet.v
  78. 0  {my jizz → session and transport}/transcript
  79. 0  {my jizz → session and transport}/transferFIFO.asy
  80. 0  {my jizz → session and transport}/transferFIFO.ngc
  81. 0  {my jizz → session and transport}/transferFIFO.sym
  82. 0  {my jizz → session and transport}/transferFIFO.v
  83. 0  {my jizz → session and transport}/transferFIFO.veo
  84. 0  {my jizz → session and transport}/transferFIFO.vhd
  85. 0  {my jizz → session and transport}/transferFIFO.vho
  86. +82 −0 session and transport/transferFIFO.xco
  87. 0  {my jizz → session and transport}/transferFIFO_fifo_generator_v4_4_xst_1.ngc_xst.xrpt
  88. 0  {my jizz → session and transport}/transferFIFO_flist.txt
  89. 0  {my jizz → session and transport}/transferFIFO_xmdf.tcl
  90. 0  {my jizz → session and transport}/transport/.lso
  91. 0  {my jizz → session and transport}/transport/combinedTransport.udo
  92. 0  {my jizz → session and transport}/transport/combinedTransport_tb.udo
  93. 0  {my jizz → session and transport}/transport/combinedTransport_tb_wave.fdo
  94. 0  {my jizz → session and transport}/transport/combinedTransport_wave.fdo
  95. 0  {my jizz → session and transport}/transport/complete.do
  96. 0  {my jizz → session and transport}/transport/complete_summary.html
  97. 0  {my jizz → session and transport}/transport/complete_tb.fdo
  98. 0  {my jizz → session and transport}/transport/complete_tb.udo
  99. 0  {my jizz → session and transport}/transport/complete_tb_wave.fdo
  100. 0  {my jizz → session and transport}/transport/compxlib.cfg
  101. 0  {my jizz → session and transport}/transport/connectedSys.spl
  102. 0  {my jizz → session and transport}/transport/connectedSys.sym
  103. 0  {my jizz → session and transport}/transport/connectedSys_summary.html
  104. 0  {my jizz → session and transport/transport}/fifo_generator_ug175.pdf
  105. 0  {my jizz → session and transport}/transport/labkit.ptwx
  106. 0  {my jizz → session and transport}/transport/labkit.ut
  107. 0  {my jizz → session and transport}/transport/labkit_guide.ncd
  108. 0  {my jizz → session and transport}/transport/labkit_map.map
  109. 0  {my jizz → session and transport}/transport/labkit_ngdbuild.xrpt
  110. 0  {my jizz → session and transport}/transport/labkit_prev_built.ngd
  111. 0  {my jizz → session and transport}/transport/labkit_summary.html
  112. 0  {my jizz → session and transport}/transport/labkit_summary.xml
  113. 0  {my jizz → session and transport}/transport/labkit_xst.xrpt
  114. 0  {my jizz → session and transport}/transport/packetBuffer.asy
  115. 0  {my jizz → session and transport}/transport/packetBuffer.cmd_log
  116. 0  {my jizz → session and transport}/transport/packetBuffer.ngc
  117. 0  {my jizz → session and transport}/transport/packetBuffer.sym
  118. 0  {my jizz → session and transport}/transport/packetBuffer.v
  119. 0  {my jizz → session and transport}/transport/packetBuffer.veo
  120. 0  {my jizz → session and transport}/transport/packetBuffer.vhd
  121. 0  {my jizz → session and transport}/transport/packetBuffer.vho
  122. +82 −0 session and transport/transport/packetBuffer.xco
  123. 0  {my jizz → session and transport}/transport/packetBuffer_fifo_generator_v4_4_xst_1.ngc_xst.xrpt
  124. 0  {my jizz → session and transport}/transport/packetBuffer_flist.txt
  125. 0  {my jizz → session and transport}/transport/packetBuffer_map.map
  126. 0  {my jizz → session and transport}/transport/packetBuffer_ngdbuild.xrpt
  127. 0  {my jizz → session and transport}/transport/packetBuffer_prev_built.ngd
  128. 0  {my jizz → session and transport}/transport/packetBuffer_xmdf.tcl
  129. 0  {my jizz → session and transport}/transport/readyPackets.asy
  130. 0  {my jizz → session and transport}/transport/readyPackets.ngc
  131. 0  {my jizz → session and transport}/transport/readyPackets.sym
  132. 0  {my jizz → session and transport}/transport/readyPackets.v
  133. 0  {my jizz → session and transport}/transport/readyPackets.veo
  134. 0  {my jizz → session and transport}/transport/readyPackets.vhd
  135. 0  {my jizz → session and transport}/transport/readyPackets.vho
  136. +82 −0 session and transport/transport/readyPackets.xco
  137. 0  {my jizz → session and transport}/transport/readyPackets_fifo_generator_v4_4_xst_1.ngc_xst.xrpt
  138. 0  {my jizz → session and transport}/transport/readyPackets_flist.txt
  139. 0  {my jizz → session and transport}/transport/readyPackets_xmdf.tcl
  140. 0  {my jizz → session and transport}/transport/receive.do
  141. 0  {my jizz → session and transport}/transport/session.udo
  142. 0  {my jizz → session and transport}/transport/session_tb.udo
  143. 0  {my jizz → session and transport}/transport/session_tb_wave.fdo
  144. 0  {my jizz → session and transport}/transport/session_wave.fdo
  145. 0  {my jizz → session and transport}/transport/sys_tb.udo
  146. 0  {my jizz → session and transport}/transport/sys_tb_wave.fdo
  147. 0  {my jizz → session and transport}/transport/tRcv_tb.udo
  148. 0  {my jizz → session and transport}/transport/tRcv_tb_wave.fdo
  149. 0  {my jizz → session and transport}/transport/tSend_tb.udo
  150. 0  {my jizz → session and transport}/transport/tSend_tb_wave.fdo
  151. 0  {my jizz → session and transport}/transport/templates/coregen.xml
  152. 0  {my jizz → session and transport}/transport/transcript
  153. 0  {my jizz → session and transport}/transport/transport.ise
  154. 0  {my jizz → session and transport}/transport/transport.ntrc_log
  155. 0  {my jizz → session and transport}/transport/transport.restore
  156. 0  {my jizz → session and transport}/transport/transportRcv.udo
  157. 0  {my jizz → session and transport}/transport/transportRcv_summary.html
  158. 0  {my jizz → session and transport}/transport/transportRcv_wave.fdo
  159. 0  {my jizz → session and transport}/transport/transportSend.udo
  160. 0  {my jizz → session and transport}/transport/transportSend.v.bak
  161. 0  {my jizz → session and transport}/transport/transportSend_summary.html
  162. 0  {my jizz → session and transport}/transport/transportSend_wave.fdo
  163. 0  {my jizz → session and transport}/transport/transportSend_xst.xrpt
  164. 0  {my jizz → session and transport}/transport/transport_xdb/tmp/ise.lock
  165. 0  ... session and transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
  166. 0  ...n and transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
  167. 0  ...sion and transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__
  168. 0  ...db → session and transport/transport/transport_xdb}/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl
  169. 0  ...r; session and transport/transport/transport_xdb}/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl
  170. 0  ...ession and transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/__stored_object_table__
  171. 0  ...rr; session and transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/__stored_objects__
  172. 0  ...sion and transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/__stored_objects___StrTbl
  173. 0  ...ssion and transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/NameMap
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  175. 0  ... transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main
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  178. 0  ...ssion and transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/ProjectNavigatorGui/GuiProjectData_StrTbl
  179. 0  ...ession and transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module
  180. 0  ...and transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Current-Module_StrTbl
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  182. 0  ...ansport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-complete_StrTbl
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  186. 0  ...transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-labkit_StrTbl
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  188. 0  ...ort}/transport/transport_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-transportRcv_StrTbl
  189. 0  ...transport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-transportSend
  190. 0  ...rt}/transport/transport_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-Data-transportSend_StrTbl
  191. 0  ...ransport}/transport/transport_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-DataFactory-Default
  192. 0  ...t}/transport/transport_xdb/tmp/ise/__OBJSTORE__/xreport/Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
  193. 0  ...GISTRY__/SrcCtrl → session and transport/transport/transport_xdb/tmp/ise/__REGISTRY__/Autonym}/regkeys
  194. 0  ..._/ProjectNavigatorGui → session and transport/transport/transport_xdb/tmp/ise/__REGISTRY__/Cs}/regkeys
  195. 0  ...r; session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
  196. 0  ...0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/HierarchicalDesign/regkeys
  197. 0  ...o_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys
  198. 0  ...onym → session and transport/transport/transport_xdb/tmp/ise/__REGISTRY__/ProjectNavigatorGui}/regkeys
  199. 0  ...ssion and transport}/transport/transport_xdb/tmp/ise/__REGISTRY__/ProjectSeedData/ProcessProperties/regkeys
  200. 0  ...ssion and transport}/transport/transport_xdb/tmp/ise/__REGISTRY__/ProjectSeedData/ProjectProperties/regkeys
  201. 0  ...; session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/ProjectSeedData/UserLibraries/regkeys
  202. 0  ... session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/ProjectSeedData/UserPartitions/regkeys
  203. 0  ...session and transport}/transport/transport_xdb/tmp/ise/__REGISTRY__/ProjectSeedData/UserSourceFiles/regkeys
  204. 0  ...to_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/ProjectSeedData/regkeys
  205. 0  {my jizz → session and transport}/transport/transport_xdb/tmp/ise/__REGISTRY__/STE/bitgen/regkeys
  206. 0  {my jizz → session and transport}/transport/transport_xdb/tmp/ise/__REGISTRY__/STE/map/regkeys
  207. 0  {my jizz → session and transport}/transport/transport_xdb/tmp/ise/__REGISTRY__/STE/ngdbuild/regkeys
  208. 0  {my jizz → session and transport}/transport/transport_xdb/tmp/ise/__REGISTRY__/STE/par/regkeys
  209. 0  {my jizz → session and transport}/transport/transport_xdb/tmp/ise/__REGISTRY__/STE/regkeys
  210. 0  {my jizz → session and transport}/transport/transport_xdb/tmp/ise/__REGISTRY__/STE/trce/regkeys
  211. 0  {my jizz → session and transport}/transport/transport_xdb/tmp/ise/__REGISTRY__/STE/xst/regkeys
  212. 0  ...EGISTRY__/common → session and transport/transport/transport_xdb/tmp/ise/__REGISTRY__/SrcCtrl}/regkeys
  213. 0  ...x_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/XSLTProcess/regkeys
  214. 0  {my jizz → session and transport}/transport/transport_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys
  215. 0  ...z/xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/bitgen/regkeys
  216. 0  {my jizz → session and transport}/transport/transport_xdb/tmp/ise/__REGISTRY__/common/regkeys
  217. 0  .../xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/cpldfit/regkeys
  218. 0  ...lnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/dumpngdio/regkeys
  219. 0  ...izz/xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/fuse/regkeys
  220. 0  ...z/xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/hprep6/regkeys
  221. 0  ...izz/xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/idem/regkeys
  222. 0  ...jizz/xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/map/regkeys
  223. 0  ...z/xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/netgen/regkeys
  224. 0  ...xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/ngc2edif/regkeys
  225. 0  ...xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/ngcbuild/regkeys
  226. 0  ...xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/ngdbuild/regkeys
  227. 0  ...jizz/xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/par/regkeys
  228. 0  ...z/xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/runner/regkeys
  229. 0  ...xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/taengine/regkeys
  230. 0  ...izz/xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/trce/regkeys
  231. 0  ...izz/xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/tsim/regkeys
  232. 0  .../xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/vhpcomp/regkeys
  233. 0  ...xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/vlogcomp/regkeys
  234. 0  ...izz/xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/xpwr/regkeys
  235. 0  ...erarchicalDesign → session and transport/transport/transport_xdb/tmp/ise/__REGISTRY__/xreport}/regkeys
  236. 0  ...jizz/xlnx_auto_0_xdb → session and transport/transport/transport_xdb}/tmp/ise/__REGISTRY__/xst/regkeys
  237. 0  {my jizz → session and transport}/transport/transport_xdb/tmp/ise/version
  238. 0  {my jizz → session and transport}/transport/vsim.wlf
  239. 0  {my jizz → session and transport}/transport/wave.do
  240. 0  {my jizz → session and transport}/transport/wlft2OX3j1
  241. 0  {my jizz → session and transport}/transport/wlftAMp3rb
  242. 0  {my jizz → session and transport}/transport/wlftC0BBL7
  243. 0  {my jizz → session and transport}/transport/wlftCHQRj9
  244. 0  {my jizz → session and transport}/transport/wlftUz5qtN
  245. 0  {my jizz → session and transport}/transport/wlftWRyubp
  246. 0  {my jizz → session and transport}/transport/wlftZsjQCu
  247. 0  {my jizz → session and transport}/transport/wlftzHaSql
  248. 0  {my jizz → session and transport}/transport/wlftzHsEEb
  249. 0  {my jizz → session and transport}/transport/work/_info
  250. 0  {my jizz → session and transport}/transport/work/_opt/_deps
  251. 0  {my jizz → session and transport}/transport/work/_opt/vopt07snxk
  252. 0  {my jizz → session and transport}/transport/work/_opt/vopt0a8bkt
  253. 0  {my jizz → session and transport}/transport/work/_opt/vopt0csvmh
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  271. 0  {my jizz → session and transport}/transport/work/_opt/voptb4507x
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  279. 0  {my jizz → session and transport}/transport/work/_opt/voptgsrses
  280. 0  {my jizz → session and transport}/transport/work/_opt/vopth2n4ni
  281. 0  {my jizz → session and transport}/transport/work/_opt/voptjy3hh3
  282. 0  {my jizz → session and transport}/transport/work/_opt/voptme3m53
  283. 0  {my jizz → session and transport}/transport/work/_opt/voptnvqr3t
  284. 0  {my jizz → session and transport}/transport/work/_opt/voptq0iri1
  285. 0  {my jizz → session and transport}/transport/work/_opt/voptq176bs
  286. 0  {my jizz → session and transport}/transport/work/_opt/voptq6tkif
  287. 0  {my jizz → session and transport}/transport/work/_opt/voptqhzxxc
  288. 0  {my jizz → session and transport}/transport/work/_opt/voptqvdafr
  289. 0  {my jizz → session and transport}/transport/work/_opt/voptqzjgck
  290. 0  {my jizz → session and transport}/transport/work/_opt/voptrnwnrc
  291. 0  {my jizz → session and transport}/transport/work/_opt/voptsaky0d
  292. 0  {my jizz → session and transport}/transport/work/_opt/voptsmy7mk
  293. 0  {my jizz → session and transport}/transport/work/_opt/voptv7sykm
  294. 0  {my jizz → session and transport}/transport/work/_opt/voptws2d36
  295. 0  {my jizz → session and transport}/transport/work/_opt/voptx2c6gm
  296. 0  {my jizz → session and transport}/transport/work/_opt/voptx885vz
  297. 0  {my jizz → session and transport}/transport/work/_opt/voptx9g63q
  298. 0  {my jizz → session and transport}/transport/work/_opt/voptye0r5q
  299. 0  {my jizz → session and transport}/transport/work/_opt/voptzbyk2y
  300. 0  {my jizz → session and transport}/transport/work/_opt/voptzikdm5
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0  my jizz/1 → session and transport/1
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18 my jizz/Session.v → session and transport/Session.v
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@@ -1,12 +1,14 @@
-/*
-
- user input:
+////////////////////////////////////////////////////////////////////////////////
+// Engineer: Kiarash Adl
+// Module Name: Session Module
+////////////////////////////////////////////////////////////////////////////////
+/*
+ possible user input:
call phone number 5'h1
answer call 5'h2
disconnect phone number 5'h5
voicmail 5'h3
-
*/
module session (input clk, input reset, input [7:0] phoneNum, input [4:0] userInp,
@@ -24,9 +26,9 @@ module session (input clk, input reset, input [7:0] phoneNum, input [4:0] userIn
reg [3:0] state=0;
- assign current_state = state;
+ assign current_state = state;
- parameter s_idle=4'd0;
+ parameter s_idle=4'd0;
parameter s_calling=4'd1;
parameter s_connected=4'd2;
parameter s_noAnswer=4'd3;
@@ -34,7 +36,7 @@ module session (input clk, input reset, input [7:0] phoneNum, input [4:0] userIn
parameter s_connectedToVoice=4'd5;
parameter s_ringing=4'd6;
- reg [7:0] phone;
+ reg [7:0] phone;
reg spkBuffer_wr_en=0;
wire [15:0] spkBufferIn;
@@ -171,7 +173,7 @@ module session (input clk, input reset, input [7:0] phoneNum, input [4:0] userIn
end
- s_noAnswer: begin
+ s_noAnswer: begin //UI needs this state change
state<=s_idle;
end
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0  ...udioBuffer_fifo_generator_v4_4_xst_1.ngc_xst.xrpt → ...udioBuffer_fifo_generator_v4_4_xst_1.ngc_xst.xrpt
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0  my jizz/audioBuffer_flist.txt → session and transport/audioBuffer_flist.txt
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0  my jizz/audioBuffer_xmdf.tcl → session and transport/audioBuffer_xmdf.tcl
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21 my jizz/combinedTransport.v → session and transport/combinedTransport.v
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@@ -1,23 +1,8 @@
-//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 17:21:17 12/11/2012
-// Design Name:
-// Module Name: combinedTransport
-// Project Name:
-// Target Devices:
-// Tool versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
+// Engineer: Kiarash Adl
+// Module: combinedTransport
//////////////////////////////////////////////////////////////////////////////////
+
module combinedTransport #(parameter packetSize=16) //in bytes
(input clk, input reset, input [1:0] cmd, input [15:0] data,
output [7:0] packetOut, input dummyBufferRd,output busy,
27 my jizz/combinedTransport_tb.v → session and transport/combinedTransport_tb.v
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@@ -1,26 +1,7 @@
-`timescale 1ns / 1ps
-
-////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 17:43:30 12/11/2012
-// Design Name: combinedTransport
-// Module Name: /afs/athena.mit.edu/user/k/i/kiarash/Documents/6.111/FPGA_Telephony/my jizz//combinedTransport_tb.v
-// Project Name: transport
-// Target Device:
-// Tool versions:
-// Description:
-//
-// Verilog Test Fixture created by ISE for module: combinedTransport
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
-////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////
+// Engineer: Kiarash Adl
+// Module: combinedTransport test bench
+//////////////////////////////////////////////////////////////////////////////////
module combinedTransport_tb;
33 my jizz/complete.v → session and transport/complete.v
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@@ -1,30 +1,19 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 01:12:05 12/10/2012
-// Design Name:
-// Module Name: connectedSys
-// Project Name:
-// Target Devices:
-// Tool versions:
-// Description:
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
-//////////////////////////////////////////////////////////////////////////////////
-module complete(
- input clk, input reset,
+////////////////////////////////////////////////////////////////////////////////
+// Engineer: Kiarash Adl
+// Module Name: CompleteTest Module
+////////////////////////////////////////////////////////////////////////////////
+
+module complete(
+ input clk, input reset,
input [3:0] oneInp,
input [3:0] twoInp,
output [3:0] onecurrent_state,
output [3:0] twocurrent_state
);
+
+//session "one" is connected to transport "sender" and the result is connected to transportRcv "recieve"
+// then there sesult is connected to session "two" ... session "two" is then outputs data to transport "s2" and the packets will
+// be recieved by transportRcv "r2" which outputs the result to session "one".
wire [4:0] oneuserInp;
assign oneuserInp={1'b0,oneInp};
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23 my jizz/complete_tb.v → session and transport/complete_tb.v
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@@ -1,25 +1,6 @@
-`timescale 1ns / 1ps
-
////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 15:43:25 12/10/2012
-// Design Name: complete
-// Module Name: /afs/athena.mit.edu/user/k/i/kiarash/Documents/6.111/FPGA_Telephony/my jizz//complete_tb.v
-// Project Name: transport
-// Target Device:
-// Tool versions:
-// Description:
-//
-// Verilog Test Fixture created by ISE for module: complete
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
+// Engineer: Kiarash Adl
+// Module Name: CompleteTest test bench
////////////////////////////////////////////////////////////////////////////////
module complete_tb;
0  my jizz/complete_tb.v~ → session and transport/complete_tb.v~
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0  my jizz/display_16hex.v → session and transport/display_16hex.v
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0  my jizz/dummyBuffer.ngc → session and transport/dummyBuffer.ngc
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0  ...ummyBuffer_fifo_generator_v4_4_xst_1.ngc_xst.xrpt → ...ummyBuffer_fifo_generator_v4_4_xst_1.ngc_xst.xrpt
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0  my jizz/dummyBuffer_flist.txt → session and transport/dummyBuffer_flist.txt
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0  my jizz/transport/fifo_generator_ug175.pdf → session and transport/fifo_generator_ug175.pdf
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0  my jizz/labkit.ucf → session and transport/labkit.ucf
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662 my jizz/labkit.v → session and transport/labkit.v
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@@ -1,339 +1,339 @@
-///////////////////////////////////////////////////////////////////////////////
-//
-// 6.111 FPGA Labkit -- Template Toplevel Module
-//
-// For Labkit Revision 004
-//
-//
-// Created: October 31, 2004, from revision 003 file
-// Author: Nathan Ickes
-//
-///////////////////////////////////////////////////////////////////////////////
-//
-// CHANGES FOR BOARD REVISION 004
-//
-// 1) Added signals for logic analyzer pods 2-4.
-// 2) Expanded "tv_in_ycrcb" to 20 bits.
-// 3) Renamed "tv_out_data" to "tv_out_i2c_data" and "tv_out_sclk" to
-// "tv_out_i2c_clock".
-// 4) Reversed disp_data_in and disp_data_out signals, so that "out" is an
-// output of the FPGA, and "in" is an input.
-//
-// CHANGES FOR BOARD REVISION 003
-//
-// 1) Combined flash chip enables into a single signal, flash_ce_b.
-//
-// CHANGES FOR BOARD REVISION 002
-//
-// 1) Added SRAM clock feedback path input and output
-// 2) Renamed "mousedata" to "mouse_data"
-// 3) Renamed some ZBT memory signals. Parity bits are now incorporated into
-// the data bus, and the byte write enables have been combined into the
-// 4-bit ram#_bwe_b bus.
-// 4) Removed the "systemace_clock" net, since the SystemACE clock is now
-// hardwired on the PCB to the oscillator.
-//
-///////////////////////////////////////////////////////////////////////////////
-//
-// Complete change history (including bug fixes)
-//
-// 2006-Mar-08: Corrected default assignments to "vga_out_red", "vga_out_green"
-// and "vga_out_blue". (Was 10'h0, now 8'h0.)
-//
-// 2005-Sep-09: Added missing default assignments to "ac97_sdata_out",
-// "disp_data_out", "analyzer[2-3]_clock" and
-// "analyzer[2-3]_data".
-//
-// 2005-Jan-23: Reduced flash address bus to 24 bits, to match 128Mb devices
-// actually populated on the boards. (The boards support up to
-// 256Mb devices, with 25 address lines.)
-//
-// 2004-Oct-31: Adapted to new revision 004 board.
-//
-// 2004-May-01: Changed "disp_data_in" to be an output, and gave it a default
-// value. (Previous versions of this file declared this port to
-// be an input.)
-//
-// 2004-Apr-29: Reduced SRAM address busses to 19 bits, to match 18Mb devices
-// actually populated on the boards. (The boards support up to
-// 72Mb devices, with 21 address lines.)
-//
-// 2004-Apr-29: Change history started
-//
-///////////////////////////////////////////////////////////////////////////////
-
-module labkit (beep, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch,
- ac97_bit_clock,
-
- vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b,
- vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync,
- vga_out_vsync,
-
- tv_out_ycrcb, tv_out_reset_b, tv_out_clock, tv_out_i2c_clock,
- tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b,
- tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset,
-
- tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1,
- tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff,
- tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read,
- tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock,
-
- ram0_data, ram0_address, ram0_adv_ld, ram0_clk, ram0_cen_b,
- ram0_ce_b, ram0_oe_b, ram0_we_b, ram0_bwe_b,
-
- ram1_data, ram1_address, ram1_adv_ld, ram1_clk, ram1_cen_b,
- ram1_ce_b, ram1_oe_b, ram1_we_b, ram1_bwe_b,
-
- clock_feedback_out, clock_feedback_in,
-
- flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b,
- flash_reset_b, flash_sts, flash_byte_b,
-
- rs232_txd, rs232_rxd, rs232_rts, rs232_cts,
-
- mouse_clock, mouse_data, keyboard_clock, keyboard_data,
-
- clock_27mhz, clock1, clock2,
-
- disp_blank, disp_data_out, disp_clock, disp_rs, disp_ce_b,
- disp_reset_b, disp_data_in,
-
- button0, button1, button2, button3, button_enter, button_right,
- button_left, button_down, button_up,
-
- switch,
-
- led,
-
- user1, user2, user3, user4,
-
- daughtercard,
-
- systemace_data, systemace_address, systemace_ce_b,
- systemace_we_b, systemace_oe_b, systemace_irq, systemace_mpbrdy,
-
- analyzer1_data, analyzer1_clock,
- analyzer2_data, analyzer2_clock,
- analyzer3_data, analyzer3_clock,
- analyzer4_data, analyzer4_clock);
-
- output beep, audio_reset_b, ac97_synch, ac97_sdata_out;
- input ac97_bit_clock, ac97_sdata_in;
-
- output [7:0] vga_out_red, vga_out_green, vga_out_blue;
- output vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock,
- vga_out_hsync, vga_out_vsync;
-
- output [9:0] tv_out_ycrcb;
- output tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data,
- tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b,
- tv_out_subcar_reset;
-
- input [19:0] tv_in_ycrcb;
- input tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef,
- tv_in_hff, tv_in_aff;
- output tv_in_i2c_clock, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso,
- tv_in_reset_b, tv_in_clock;
- inout tv_in_i2c_data;
-
- inout [35:0] ram0_data;
- output [18:0] ram0_address;
- output ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b;
- output [3:0] ram0_bwe_b;
-
- inout [35:0] ram1_data;
- output [18:0] ram1_address;
- output ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b;
- output [3:0] ram1_bwe_b;
-
- input clock_feedback_in;
- output clock_feedback_out;
-
- inout [15:0] flash_data;
- output [23:0] flash_address;
- output flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_byte_b;
- input flash_sts;
-
- output rs232_txd, rs232_rts;
- input rs232_rxd, rs232_cts;
-
- input mouse_clock, mouse_data, keyboard_clock, keyboard_data;
-
- input clock_27mhz, clock1, clock2;
-
- output disp_blank, disp_clock, disp_rs, disp_ce_b, disp_reset_b;
- input disp_data_in;
- output disp_data_out;
-
- input button0, button1, button2, button3, button_enter, button_right,
- button_left, button_down, button_up;
- input [7:0] switch;
- output [7:0] led;
-
- inout [31:0] user1, user2, user3, user4;
-
- inout [43:0] daughtercard;
-
- inout [15:0] systemace_data;
- output [6:0] systemace_address;
- output systemace_ce_b, systemace_we_b, systemace_oe_b;
- input systemace_irq, systemace_mpbrdy;
-
- output [15:0] analyzer1_data, analyzer2_data, analyzer3_data,
- analyzer4_data;
- output analyzer1_clock, analyzer2_clock, analyzer3_clock, analyzer4_clock;
-
- ////////////////////////////////////////////////////////////////////////////
- //
- // I/O Assignments
- //
- ////////////////////////////////////////////////////////////////////////////
-
- // Audio Input and Output
- assign beep= 1'b0;
- assign audio_reset_b = 1'b0;
- assign ac97_synch = 1'b0;
- assign ac97_sdata_out = 1'b0;
- // ac97_sdata_in is an input
-
- // VGA Output
- assign vga_out_red = 8'h0;
- assign vga_out_green = 8'h0;
- assign vga_out_blue = 8'h0;
- assign vga_out_sync_b = 1'b1;
- assign vga_out_blank_b = 1'b1;
- assign vga_out_pixel_clock = 1'b0;
- assign vga_out_hsync = 1'b0;
- assign vga_out_vsync = 1'b0;
-
- // Video Output
- assign tv_out_ycrcb = 10'h0;
- assign tv_out_reset_b = 1'b0;
- assign tv_out_clock = 1'b0;
- assign tv_out_i2c_clock = 1'b0;
- assign tv_out_i2c_data = 1'b0;
- assign tv_out_pal_ntsc = 1'b0;
- assign tv_out_hsync_b = 1'b1;
- assign tv_out_vsync_b = 1'b1;
- assign tv_out_blank_b = 1'b1;
- assign tv_out_subcar_reset = 1'b0;
-
- // Video Input
- assign tv_in_i2c_clock = 1'b0;
- assign tv_in_fifo_read = 1'b0;
- assign tv_in_fifo_clock = 1'b0;
- assign tv_in_iso = 1'b0;
- assign tv_in_reset_b = 1'b0;
- assign tv_in_clock = 1'b0;
- assign tv_in_i2c_data = 1'bZ;
- // tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2,
- // tv_in_aef, tv_in_hff, and tv_in_aff are inputs
-
- // SRAMs
- assign ram0_data = 36'hZ;
- assign ram0_address = 19'h0;
- assign ram0_adv_ld = 1'b0;
- assign ram0_clk = 1'b0;
- assign ram0_cen_b = 1'b1;
- assign ram0_ce_b = 1'b1;
- assign ram0_oe_b = 1'b1;
- assign ram0_we_b = 1'b1;
- assign ram0_bwe_b = 4'hF;
- assign ram1_data = 36'hZ;
- assign ram1_address = 19'h0;
- assign ram1_adv_ld = 1'b0;
- assign ram1_clk = 1'b0;
- assign ram1_cen_b = 1'b1;
- assign ram1_ce_b = 1'b1;
- assign ram1_oe_b = 1'b1;
- assign ram1_we_b = 1'b1;
- assign ram1_bwe_b = 4'hF;
- assign clock_feedback_out = 1'b0;
- // clock_feedback_in is an input
-
- // Flash ROM
- assign flash_data = 16'hZ;
- assign flash_address = 24'h0;
- assign flash_ce_b = 1'b1;
- assign flash_oe_b = 1'b1;
- assign flash_we_b = 1'b1;
- assign flash_reset_b = 1'b0;
- assign flash_byte_b = 1'b1;
- // flash_sts is an input
-
- // RS-232 Interface
- assign rs232_txd = 1'b1;
- assign rs232_rts = 1'b1;
- // rs232_rxd and rs232_cts are inputs
-
- // PS/2 Ports
- // mouse_clock, mouse_data, keyboard_clock, and keyboard_data are inputs
-/*
- // LED Displays
- assign disp_blank = 1'b1;
- assign disp_clock = 1'b0;
- assign disp_rs = 1'b0;
- assign disp_ce_b = 1'b1;
- assign disp_reset_b = 1'b0;
- assign disp_data_out = 1'b0;
- // disp_data_in is an input
+///////////////////////////////////////////////////////////////////////////////
+//
+// 6.111 FPGA Labkit -- Template Toplevel Module
+//
+// For Labkit Revision 004
+//
+//
+// Created: October 31, 2004, from revision 003 file
+// Author: Nathan Ickes
+//
+///////////////////////////////////////////////////////////////////////////////
+//
+// CHANGES FOR BOARD REVISION 004
+//
+// 1) Added signals for logic analyzer pods 2-4.
+// 2) Expanded "tv_in_ycrcb" to 20 bits.
+// 3) Renamed "tv_out_data" to "tv_out_i2c_data" and "tv_out_sclk" to
+// "tv_out_i2c_clock".
+// 4) Reversed disp_data_in and disp_data_out signals, so that "out" is an
+// output of the FPGA, and "in" is an input.
+//
+// CHANGES FOR BOARD REVISION 003
+//
+// 1) Combined flash chip enables into a single signal, flash_ce_b.
+//
+// CHANGES FOR BOARD REVISION 002
+//
+// 1) Added SRAM clock feedback path input and output
+// 2) Renamed "mousedata" to "mouse_data"
+// 3) Renamed some ZBT memory signals. Parity bits are now incorporated into
+// the data bus, and the byte write enables have been combined into the
+// 4-bit ram#_bwe_b bus.
+// 4) Removed the "systemace_clock" net, since the SystemACE clock is now
+// hardwired on the PCB to the oscillator.
+//
+///////////////////////////////////////////////////////////////////////////////
+//
+// Complete change history (including bug fixes)
+//
+// 2006-Mar-08: Corrected default assignments to "vga_out_red", "vga_out_green"
+// and "vga_out_blue". (Was 10'h0, now 8'h0.)
+//
+// 2005-Sep-09: Added missing default assignments to "ac97_sdata_out",
+// "disp_data_out", "analyzer[2-3]_clock" and
+// "analyzer[2-3]_data".
+//
+// 2005-Jan-23: Reduced flash address bus to 24 bits, to match 128Mb devices
+// actually populated on the boards. (The boards support up to
+// 256Mb devices, with 25 address lines.)
+//
+// 2004-Oct-31: Adapted to new revision 004 board.
+//
+// 2004-May-01: Changed "disp_data_in" to be an output, and gave it a default
+// value. (Previous versions of this file declared this port to
+// be an input.)
+//
+// 2004-Apr-29: Reduced SRAM address busses to 19 bits, to match 18Mb devices
+// actually populated on the boards. (The boards support up to
+// 72Mb devices, with 21 address lines.)
+//
+// 2004-Apr-29: Change history started
+//
+///////////////////////////////////////////////////////////////////////////////
+
+module labkit (beep, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch,
+ ac97_bit_clock,
+
+ vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b,
+ vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync,
+ vga_out_vsync,
+
+ tv_out_ycrcb, tv_out_reset_b, tv_out_clock, tv_out_i2c_clock,
+ tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b,
+ tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset,
+
+ tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1,
+ tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff,
+ tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read,
+ tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock,
+
+ ram0_data, ram0_address, ram0_adv_ld, ram0_clk, ram0_cen_b,
+ ram0_ce_b, ram0_oe_b, ram0_we_b, ram0_bwe_b,
+
+ ram1_data, ram1_address, ram1_adv_ld, ram1_clk, ram1_cen_b,
+ ram1_ce_b, ram1_oe_b, ram1_we_b, ram1_bwe_b,
+
+ clock_feedback_out, clock_feedback_in,
+
+ flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b,
+ flash_reset_b, flash_sts, flash_byte_b,
+
+ rs232_txd, rs232_rxd, rs232_rts, rs232_cts,
+
+ mouse_clock, mouse_data, keyboard_clock, keyboard_data,
+
+ clock_27mhz, clock1, clock2,
+
+ disp_blank, disp_data_out, disp_clock, disp_rs, disp_ce_b,
+ disp_reset_b, disp_data_in,
+
+ button0, button1, button2, button3, button_enter, button_right,
+ button_left, button_down, button_up,
+
+ switch,
+
+ led,
+
+ user1, user2, user3, user4,
+
+ daughtercard,
+
+ systemace_data, systemace_address, systemace_ce_b,
+ systemace_we_b, systemace_oe_b, systemace_irq, systemace_mpbrdy,
+
+ analyzer1_data, analyzer1_clock,
+ analyzer2_data, analyzer2_clock,
+ analyzer3_data, analyzer3_clock,
+ analyzer4_data, analyzer4_clock);
+
+ output beep, audio_reset_b, ac97_synch, ac97_sdata_out;
+ input ac97_bit_clock, ac97_sdata_in;
+
+ output [7:0] vga_out_red, vga_out_green, vga_out_blue;
+ output vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock,
+ vga_out_hsync, vga_out_vsync;
+
+ output [9:0] tv_out_ycrcb;
+ output tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data,
+ tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b,
+ tv_out_subcar_reset;
+
+ input [19:0] tv_in_ycrcb;
+ input tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef,
+ tv_in_hff, tv_in_aff;
+ output tv_in_i2c_clock, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso,
+ tv_in_reset_b, tv_in_clock;
+ inout tv_in_i2c_data;
+
+ inout [35:0] ram0_data;
+ output [18:0] ram0_address;
+ output ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b;
+ output [3:0] ram0_bwe_b;
+
+ inout [35:0] ram1_data;
+ output [18:0] ram1_address;
+ output ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b;
+ output [3:0] ram1_bwe_b;
+
+ input clock_feedback_in;
+ output clock_feedback_out;
+
+ inout [15:0] flash_data;
+ output [23:0] flash_address;
+ output flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_byte_b;
+ input flash_sts;
+
+ output rs232_txd, rs232_rts;
+ input rs232_rxd, rs232_cts;
+
+ input mouse_clock, mouse_data, keyboard_clock, keyboard_data;
+
+ input clock_27mhz, clock1, clock2;
+
+ output disp_blank, disp_clock, disp_rs, disp_ce_b, disp_reset_b;
+ input disp_data_in;
+ output disp_data_out;
+
+ input button0, button1, button2, button3, button_enter, button_right,
+ button_left, button_down, button_up;
+ input [7:0] switch;
+ output [7:0] led;
+
+ inout [31:0] user1, user2, user3, user4;
+
+ inout [43:0] daughtercard;
+
+ inout [15:0] systemace_data;
+ output [6:0] systemace_address;
+ output systemace_ce_b, systemace_we_b, systemace_oe_b;
+ input systemace_irq, systemace_mpbrdy;
+
+ output [15:0] analyzer1_data, analyzer2_data, analyzer3_data,
+ analyzer4_data;
+ output analyzer1_clock, analyzer2_clock, analyzer3_clock, analyzer4_clock;
+
+ ////////////////////////////////////////////////////////////////////////////
+ //
+ // I/O Assignments
+ //
+ ////////////////////////////////////////////////////////////////////////////
+
+ // Audio Input and Output
+ assign beep= 1'b0;
+ assign audio_reset_b = 1'b0;
+ assign ac97_synch = 1'b0;
+ assign ac97_sdata_out = 1'b0;
+ // ac97_sdata_in is an input
+
+ // VGA Output
+ assign vga_out_red = 8'h0;
+ assign vga_out_green = 8'h0;
+ assign vga_out_blue = 8'h0;
+ assign vga_out_sync_b = 1'b1;
+ assign vga_out_blank_b = 1'b1;
+ assign vga_out_pixel_clock = 1'b0;
+ assign vga_out_hsync = 1'b0;
+ assign vga_out_vsync = 1'b0;
+
+ // Video Output
+ assign tv_out_ycrcb = 10'h0;
+ assign tv_out_reset_b = 1'b0;
+ assign tv_out_clock = 1'b0;
+ assign tv_out_i2c_clock = 1'b0;
+ assign tv_out_i2c_data = 1'b0;
+ assign tv_out_pal_ntsc = 1'b0;
+ assign tv_out_hsync_b = 1'b1;
+ assign tv_out_vsync_b = 1'b1;
+ assign tv_out_blank_b = 1'b1;
+ assign tv_out_subcar_reset = 1'b0;
+
+ // Video Input
+ assign tv_in_i2c_clock = 1'b0;
+ assign tv_in_fifo_read = 1'b0;
+ assign tv_in_fifo_clock = 1'b0;
+ assign tv_in_iso = 1'b0;
+ assign tv_in_reset_b = 1'b0;
+ assign tv_in_clock = 1'b0;
+ assign tv_in_i2c_data = 1'bZ;
+ // tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2,
+ // tv_in_aef, tv_in_hff, and tv_in_aff are inputs
+
+ // SRAMs
+ assign ram0_data = 36'hZ;
+ assign ram0_address = 19'h0;
+ assign ram0_adv_ld = 1'b0;
+ assign ram0_clk = 1'b0;
+ assign ram0_cen_b = 1'b1;
+ assign ram0_ce_b = 1'b1;
+ assign ram0_oe_b = 1'b1;
+ assign ram0_we_b = 1'b1;
+ assign ram0_bwe_b = 4'hF;
+ assign ram1_data = 36'hZ;
+ assign ram1_address = 19'h0;
+ assign ram1_adv_ld = 1'b0;
+ assign ram1_clk = 1'b0;
+ assign ram1_cen_b = 1'b1;
+ assign ram1_ce_b = 1'b1;
+ assign ram1_oe_b = 1'b1;
+ assign ram1_we_b = 1'b1;
+ assign ram1_bwe_b = 4'hF;
+ assign clock_feedback_out = 1'b0;
+ // clock_feedback_in is an input
+
+ // Flash ROM
+ assign flash_data = 16'hZ;
+ assign flash_address = 24'h0;
+ assign flash_ce_b = 1'b1;
+ assign flash_oe_b = 1'b1;
+ assign flash_we_b = 1'b1;
+ assign flash_reset_b = 1'b0;
+ assign flash_byte_b = 1'b1;
+ // flash_sts is an input
+
+ // RS-232 Interface
+ assign rs232_txd = 1'b1;
+ assign rs232_rts = 1'b1;
+ // rs232_rxd and rs232_cts are inputs
+
+ // PS/2 Ports
+ // mouse_clock, mouse_data, keyboard_clock, and keyboard_data are inputs
+/*
+ // LED Displays
+ assign disp_blank = 1'b1;
+ assign disp_clock = 1'b0;
+ assign disp_rs = 1'b0;
+ assign disp_ce_b = 1'b1;
+ assign disp_reset_b = 1'b0;
+ assign disp_data_out = 1'b0;
+ // disp_data_in is an input
*/
-
- // Buttons, Switches, and Individual LEDs
+
+ // Buttons, Switches, and Individual LEDs
assign led[7:0] = 8'b1111_1111;
-
- // button0, button1, button2, button3, button_enter, button_right,
- // button_left, button_down, button_up, and switches are inputs
-
- // User I/Os
- assign user1 = 32'hZ;
- assign user2 = 32'hZ;
- assign user3 = 32'hZ;
- assign user4 = 32'hZ;
-
- // Daughtercard Connectors
- assign daughtercard = 44'hZ;
-
- // SystemACE Microprocessor Port
- assign systemace_data = 16'hZ;
- assign systemace_address = 7'h0;
- assign systemace_ce_b = 1'b1;
- assign systemace_we_b = 1'b1;
- assign systemace_oe_b = 1'b1;
- // systemace_irq and systemace_mpbrdy are inputs
-
- // Logic Analyzer
- assign analyzer1_data = 16'h0;
- assign analyzer1_clock = 1'b1;
- assign analyzer2_data = 16'h0;
- assign analyzer2_clock = 1'b1;
- assign analyzer3_data = 16'h0;
- assign analyzer3_clock = 1'b1;
- assign analyzer4_data = 16'h0;
- assign analyzer4_clock = 1'b1;
-
-////////////////////////////////////////////////////////////////////////////
- //
- // Reset Generation
- //
- // A shift register primitive is used to generate an active-high reset
- // signal that remains high for 16 clock cycles after configuration finishes
- // and the FPGA's internal clocks begin toggling.
- //
- ////////////////////////////////////////////////////////////////////////////
- wire reset;
- SRL16 reset_sr(.D(1'b0), .CLK(clock_27mhz), .Q(reset),
- .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1));
- defparam reset_sr.INIT = 16'hFFFF;
+
+ // button0, button1, button2, button3, button_enter, button_right,
+ // button_left, button_down, button_up, and switches are inputs
+
+ // User I/Os
+ assign user1 = 32'hZ;
+ assign user2 = 32'hZ;
+ assign user3 = 32'hZ;
+ assign user4 = 32'hZ;
+
+ // Daughtercard Connectors
+ assign daughtercard = 44'hZ;
+
+ // SystemACE Microprocessor Port
+ assign systemace_data = 16'hZ;
+ assign systemace_address = 7'h0;
+ assign systemace_ce_b = 1'b1;
+ assign systemace_we_b = 1'b1;
+ assign systemace_oe_b = 1'b1;
+ // systemace_irq and systemace_mpbrdy are inputs
+
+ // Logic Analyzer
+ assign analyzer1_data = 16'h0;
+ assign analyzer1_clock = 1'b1;
+ assign analyzer2_data = 16'h0;
+ assign analyzer2_clock = 1'b1;
+ assign analyzer3_data = 16'h0;
+ assign analyzer3_clock = 1'b1;
+ assign analyzer4_data = 16'h0;
+ assign analyzer4_clock = 1'b1;
+
+////////////////////////////////////////////////////////////////////////////
+ //
+ // Reset Generation
+ //
+ // A shift register primitive is used to generate an active-high reset
+ // signal that remains high for 16 clock cycles after configuration finishes
+ // and the FPGA's internal clocks begin toggling.
+ //
+ ////////////////////////////////////////////////////////////////////////////
+ wire reset;
+ SRL16 reset_sr(.D(1'b0), .CLK(clock_27mhz), .Q(reset),
+ .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1));
+ defparam reset_sr.INIT = 16'hFFFF;
wire [3:0] oneInp;
wire [3:0] twoInp;
-
+
assign oneInp=switch[7:4];
assign twoInp=switch[3:0];
- wire clk;
-
+ wire clk;
+
assign clk = clock_27mhz;
wire [3:0] twocurrent_state;
@@ -345,12 +345,12 @@ module labkit (beep, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch,
wire [63:0] displayData;
- assign displayData[63:0]={48'd0,4'b0,twocurrent_state, 4'b0,onecurrent_state };
+ assign displayData[63:0]={48'd0,4'b0,twocurrent_state, 4'b0,onecurrent_state };
display_16hex dsp1(.reset(reset), .clock_27mhz(clk), .data(displayData),
.disp_blank(disp_blank), .disp_clock(disp_clock), .disp_rs(disp_rs), .disp_ce_b(disp_ce_b),
.disp_reset_b(disp_reset_b), .disp_data_out(disp_data_out));
-
-endmodule
+
+endmodule
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0  my jizz/rcvPackets.vho → session and transport/rcvPackets.vho
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0  my jizz/rcvPackets.xco → session and transport/rcvPackets.xco
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0  ...rcvPackets_fifo_generator_v4_4_xst_1.ngc_xst.xrpt → ...rcvPackets_fifo_generator_v4_4_xst_1.ngc_xst.xrpt
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0  my jizz/rcvPackets_flist.txt → session and transport/rcvPackets_flist.txt
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0  my jizz/rcvPackets_readme.txt → session and transport/rcvPackets_readme.txt
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0  my jizz/rcvPackets_xmdf.tcl → session and transport/rcvPackets_xmdf.tcl
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23 my jizz/session_tb.v → session and transport/session_tb.v
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@@ -1,25 +1,6 @@
-`timescale 1ns / 1ps
-
////////////////////////////////////////////////////////////////////////////////
-// Company:
-// Engineer:
-//
-// Create Date: 12:24:28 12/10/2012
-// Design Name: session
-// Module Name: /afs/athena.mit.edu/user/k/i/kiarash/Documents/6.111/FPGA_Telephony/my jizz//session_tb.v
-// Project Name: transport
-// Target Device:
-// Tool versions:
-// Description:
-//
-// Verilog Test Fixture created by ISE for module: session
-//
-// Dependencies:
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
+// Engineer: Kiarash Adl
+// Module Name: Session Module Test Bench
////////////////////////////////////////////////////////////////////////////////
module session_tb;
245 session and transport/sources/Session.v
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@@ -0,0 +1,245 @@
+////////////////////////////////////////////////////////////////////////////////
+// Engineer: Kiarash Adl
+// Module Name: Session Module
+////////////////////////////////////////////////////////////////////////////////
+
+/*
+ possible user input:
+ call phone number 5'h1
+ answer call 5'h2
+ disconnect phone number 5'h5
+ voicmail 5'h3
+*/
+
+module session (input clk, input reset, input [7:0] phoneNum, input [4:0] userInp,
+ input [1:0] cmdIn, input [15:0] packetIn, input transportBusy,
+ output reg [1:0] cmd, output reg [15:0] dataOut, output reg sessionBusy,
+ output reg [7:0] phoneOut, output [3:0] current_state,
+
+ input ac97_clk, input [15:0] micBufferIn,
+ output [15:0] spkBufferOut, output micBufferFull, output micBufferEmpty,
+ output spkBufferFull, output spkBufferEmpty
+ );
+
+
+ reg micBuffer_wr_en, spkBuffer_rd_en;
+
+ reg [3:0] state=0;
+
+ assign current_state = state;
+
+ parameter s_idle=4'd0;
+ parameter s_calling=4'd1;
+ parameter s_connected=4'd2;
+ parameter s_noAnswer=4'd3;
+ parameter s_voicemail=4'd4;
+ parameter s_connectedToVoice=4'd5;
+ parameter s_ringing=4'd6;
+
+ reg [7:0] phone;
+
+ reg spkBuffer_wr_en=0;
+ wire [15:0] spkBufferIn;
+ assign spkBufferIn=packetIn;
+
+ wire [15:0] micBufferOut;
+ reg micBuffer_rd_en;
+
+
+ wire [15:0] spkOut;
+
+ audioBuffer micBuffer ( .din(micBufferIn), .rd_clk(clk),.rd_en(micBuffer_rd_en), .rst(reset),
+ .wr_clk(ac97_clk), .wr_en(micBuffer_wr_en), .dout(micBufferOut), .empty(micBufferEmpty), .full(micBufferFull));
+
+
+ audioBuffer spkBuffer ( .din(spkBufferIn), .rd_clk(ac97_clk),.rd_en(spkBuffer_rd_en), .rst(reset),
+ .wr_clk(clk), .wr_en(spkBuffer_wr_en), .dout(spkOut), .empty(spkBufferEmpty), .full(spkBufferFull));
+
+ assign spkBufferOut= spkBufferEmpty? 16'b0 : spkOut;
+
+ always @(posedge clk) begin
+
+ if (reset) begin
+ state<=s_idle;
+ spkBuffer_wr_en<=0;
+ micBuffer_rd_en<=0;
+
+ end else case (state)
+
+ s_idle: begin
+
+ sessionBusy<=0;
+
+ if (userInp==5'h1) begin //call a phone number
+ cmd<=2'b01; //sending a control packet
+ dataOut[15:8]<=phoneNum;
+ dataOut[7:0]<=8'h1;
+ state<=s_calling;
+ phone<=phoneNum;
+ end else if (cmdIn==2'b01 && packetIn[7:0]==8'h1) begin //recieving a call
+ phone<=packetIn[15:8];
+ state<=s_ringing;
+ phoneOut<=packetIn[15:8];
+ cmd<=0;
+ end else begin
+ state<=s_idle;
+ cmd<=0;
+ end
+
+ end
+
+
+ s_calling: begin
+ sessionBusy<=0;
+ cmd<=0;
+
+ if ((cmdIn==2'b01) && (packetIn[7:0]==8'h2)) begin //Answered
+ phone<=packetIn[15:8];
+ state<=s_connected;
+ end else if ((cmdIn==2'b01) && (packetIn[7:0]==8'h3)) begin //Voice-mail
+ phone<=packetIn[15:8];
+ state<=s_connectedToVoice;
+ end else if ((cmdIn==2'b01) && (packetIn[7:0]==8'h5)) begin //rejected
+ state<=s_noAnswer;
+ end else if (userInp==5'h5) begin //user disconnect
+ cmd<=2'b01; //sending a control packet
+ dataOut[15:8]<=phone;
+ dataOut[7:0]<=8'h5;
+ state<=s_idle;
+ end else state<=s_calling;
+
+ end
+
+ s_ringing: begin
+ sessionBusy<=0;
+ phoneOut<=phone; //outputing the caller's number
+ if ((cmdIn==2'b01) && (packetIn[7:0]==8'h5)) begin //rejected
+ state<=s_idle;
+ end else if (userInp==5'h5) begin //reject call
+ state<=s_idle;
+ cmd<=2'b01; //send a control packet
+ dataOut[15:8]<=phone;
+ dataOut[7:0]<=8'h5;
+ end else if (userInp==5'h3) begin //voice-mail
+ cmd<=2'b01;
+ dataOut[15:8]<=phone;
+ dataOut[7:0]<=8'h3;
+ state<=s_voicemail;
+ end else if (userInp==5'h2) begin //user answered
+ cmd<=2'b01;
+ dataOut[15:8]<=phone;
+ dataOut[7:0]<=8'h2;
+ state<=s_connected;
+ end else begin
+ state<=s_ringing;
+ end
+
+ end
+
+ s_connected: begin
+ sessionBusy<=0;
+
+ if (userInp==5'h5) begin //user disconnects the call
+ state<=s_idle;
+ micBuffer_wr_en<=0;
+ cmd<=2'b01;
+ dataOut[7:0]<=8'h5;
+ dataOut[15:8]<=phone;
+ end else if ((cmdIn==2'b01) && (packetIn[7:0]==8'h5)) begin //they hung up
+ micBuffer_wr_en<=0;
+ state<=s_idle;
+ cmd<=0;
+ end else begin
+
+ micBuffer_wr_en<=1;spkBuffer_rd_en<=1;
+
+ if ((!transportBusy) && (!micBufferEmpty)) begin //sending audio
+ micBuffer_rd_en<=1;
+ cmd<=2'b10;
+ dataOut<=micBufferOut;
+ end else begin
+ micBuffer_rd_en<=0;
+ cmd<=0;
+ end
+
+ if (cmdIn==2'b10) begin //incoming audio
+ spkBuffer_wr_en<=1;
+ end else begin
+ spkBuffer_wr_en<=0;
+ end
+
+ state<=s_connected;
+ end
+
+ end
+
+ s_noAnswer: begin //UI needs this state change
+ state<=s_idle;
+ end
+
+ s_voicemail: begin
+ sessionBusy<=0;
+
+ if (userInp==5'h5) begin //user disconnects the call
+
+ cmd<=2'b01;
+ dataOut[7:0]<=8'h5;
+ dataOut[15:8]<=phone;
+ state<=s_idle;
+
+ end else if ((cmdIn==2'b01) && (packetIn[7:0]==8'h5)) begin //they hung up
+ state<=s_idle;
+ cmd<=0;
+ end else if (cmdIn==2'b10) begin //incoming audio
+ spkBuffer_wr_en<=1;
+ state<=s_voicemail;
+ end else begin
+ spkBuffer_wr_en<=0;
+ state<=s_voicemail;
+ end
+
+ end
+
+ s_connectedToVoice: begin
+ sessionBusy<=0;
+ if (userInp==5'h5) begin //user disconnects the call
+ micBuffer_wr_en<=0;
+ cmd<=2'b01;
+ dataOut[7:0]<=8'h5;
+ dataOut[15:8]<=phone;
+ state<=s_idle;
+ end else if ((cmdIn==2'b01) && (packetIn[7:0]==8'h5)) begin //they hung up
+ micBuffer_wr_en<=0;
+ state<=s_idle;
+ cmd<=0;
+ end else begin
+
+ micBuffer_wr_en<=1;spkBuffer_rd_en<=1;
+
+
+ if ((!transportBusy) && (!micBufferEmpty)) begin //sending audio
+ micBuffer_rd_en<=1;
+ cmd<=2'b10;
+ dataOut<=micBufferOut;
+ end else begin
+ micBuffer_rd_en<=0;
+ cmd<=0;
+ end
+
+ state<=s_connectedToVoice;
+
+ end
+
+ end
+
+ endcase
+
+ end
+
+endmodule
+
+
+
+
+
+
82 session and transport/sources/audioBuffer.xco
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@@ -0,0 +1,82 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Mon Dec 10 17:33:41 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc2v6000
+SET devicefamily = virtex2
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = bf957
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -4
+SET verilogsim = True
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.4
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=audioBuffer
+CSET data_count=false
+CSET data_count_width=11
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=2047
+CSET full_threshold_negate_value=2046
+CSET input_data_width=16
+CSET input_depth=2048
+CSET output_data_width=16
+CSET output_depth=2048
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=11
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=false
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=11
+# END Parameters
+GENERATE
+# CRC: d42c4a9b
+
37 session and transport/sources/combinedTransport.v
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@@ -0,0 +1,37 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Engineer: Kiarash Adl
+// Module: combinedTransport
+//////////////////////////////////////////////////////////////////////////////////
+
+module combinedTransport #(parameter packetSize=16) //in bytes
+ (input clk, input reset, input [1:0] cmd, input [15:0] data,
+ output [7:0] packetOut, input dummyBufferRd,output busy,
+ output [7:0] phoneNum, output [9:0] dummyBufferCount, output dummyBufferEmpty);
+
+ wire sending;
+ wire [7:0] sendPacketOut;
+ wire [10:0] ready_data_count;
+ wire sendData;
+
+ transportSend sender (
+ .clk(clk),
+ .reset(reset),
+ .cmd(cmd),
+ .data(data),
+ .sendData(sendData),
+ .sending(sending),
+ .packetOut(sendPacketOut),
+ .busy(busy),
+ .ready_data_count(ready_data_count)
+ );
+
+ wire [2:0] debug;
+
+ tranToNet oneTran
+ (.clk(clk), .reset(reset), .data(sendPacketOut), .sending(sending), .dummyBufferRd(dummyBufferRd),
+ .sendData(sendData), .phoneNum(phoneNum), .packetOut(packetOut),
+ .dummyBufferCount(dummyBufferCount), .dummyBufferEmpty(dummyBufferEmpty),
+ .debug(debug));
+
+
+endmodule
63 session and transport/sources/combinedTransport_tb.v
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@@ -0,0 +1,63 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Engineer: Kiarash Adl
+// Module: combinedTransport test bench
+//////////////////////////////////////////////////////////////////////////////////
+
+module combinedTransport_tb;
+
+ // Inputs
+ reg clk;
+ reg reset;
+ reg [1:0] cmd;
+ reg [15:0] data;
+ reg dummyBufferRd;
+
+ // Outputs
+ wire [7:0] packetOut;
+ wire [7:0] phoneNum;
+ wire [9:0] dummyBufferCount;
+ wire dummyBufferEmpty;
+ wire busy;
+
+ // Instantiate the Unit Under Test (UUT)
+ combinedTransport uut (
+ .clk(clk),
+ .reset(reset),
+ .cmd(cmd),
+ .data(data),
+ .packetOut(packetOut),
+ .dummyBufferRd(dummyBufferRd),
+ .busy(busy),
+ .phoneNum(phoneNum),
+ .dummyBufferCount(dummyBufferCount),
+ .dummyBufferEmpty(dummyBufferEmpty)
+ );
+
+ always #5 clk= !clk;
+
+ initial begin
+ // Initialize Inputs
+ clk = 0;
+ reset = 0;
+ cmd = 0;
+ data = 0;
+ dummyBufferRd=0;
+
+ // Wait 100 ns for global reset to finish
+ #100;
+
+ // Add stimulus here
+ cmd=2'b01;
+ data=16'b1010_0011_1111_0001;
+ #50;
+ cmd=0;
+ #400;
+ dummyBufferRd=1;
+ cmd=2'b10;
+ data=16'b1010_0011_1111_0001;
+
+
+ end
+
+endmodule
+
176 session and transport/sources/complete.v
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@@ -0,0 +1,176 @@
+////////////////////////////////////////////////////////////////////////////////
+// Engineer: Kiarash Adl
+// Module Name: CompleteTest Module
+////////////////////////////////////////////////////////////////////////////////
+
+module complete(
+ input clk, input reset,
+ input [3:0] oneInp,
+ input [3:0] twoInp,
+ output [3:0] onecurrent_state,
+ output [3:0] twocurrent_state
+ );
+
+//session "one" is connected to transport "sender" and the result is connected to transportRcv "recieve"
+// then there sesult is connected to session "two" ... session "two" is then outputs data to transport "s2" and the packets will
+// be recieved by transportRcv "r2" which outputs the result to session "one".
+
+ wire [4:0] oneuserInp;
+ assign oneuserInp={1'b0,oneInp};
+
+ wire [4:0] twouserInp;
+ assign twouserInp={1'b0, twoInp};
+
+
+ wire [1:0] onecmdIn;
+ wire twotransportBusy;
+ wire [7:0] onephoneNum=8'b1111_1111;
+ wire [7:0] twophoneOut;
+
+ wire onetransportBusy;
+
+ wire onemicFlag;
+ wire [1:0] onecmd;
+ wire [15:0] onedataOut;
+ wire onesessionBusy;
+ wire [7:0] onephoneOut;
+
+
+ wire [15:0] onespkBufferOut;
+ wire onemicBufferFull;
+ wire onemicBufferEmpty;
+ wire onespkBufferFull;
+ wire onespkBufferEmpty;
+ wire [15:0] onemicBufferOut;
+
+ wire [15:0] onepacketInp;
+
+
+ session one (
+ .clk(clk),
+ .reset(reset),
+ .phoneNum(onephoneNum),
+ .userInp(oneuserInp),
+ .cmdIn(onecmdIn),
+ .packetIn(onepacketInp),
+ .transportBusy(onetransportBusy),
+ .cmd(onecmd),
+ .dataOut(onedataOut),
+ .sessionBusy(onesessionBusy),
+ .phoneOut(onephoneOut),
+ .current_state(onecurrent_state),
+ .ac97_clk(clk),
+ .micBufferIn(16'b0),
+ .spkBufferOut(onemicBufferOut),
+ .micBufferFull(onemicBufferFull),
+ .micBufferEmpty(onemicBufferEmpty),
+ .spkBufferFull(onespkBufferFull),
+ .spkBufferEmpty(onespkBufferEmpty)
+ );
+
+ wire sending;
+ wire [7:0] sendPacketOut;
+ wire [10:0] senderCounter;
+
+ transportSend sender (
+ .clk(clk),
+ .reset(reset),
+ .cmd(onecmd),
+ .data(onedataOut),
+ .sendData(1'b1),
+ .sending(sending),
+ .packetOut(sendPacketOut),
+ .busy(onetransportBusy),
+ .ready_data_count(senderCounter)
+ );
+
+ wire sessionBusy;
+
+ wire [1:0] sendingToSession;
+ wire [15:0] sessionData;
+ wire [7:0] dafuq;
+ wire [10:0] rcvCounter;
+
+ transportRcv receive (
+ .clk(clk),
+ .reset(reset),
+ .rcvSignal(sending),
+ .packetIn(sendPacketOut),
+ .sessionBusy(sessionBusy),
+ .sendingToSession(sendingToSession),
+ .data(sessionData),
+ .rcv_data_count(rcvCounter),
+ .dafuq(dafuq)
+ );
+
+
+ wire twomicFlag;
+ wire [15:0] twoaudioOut;
+ wire [1:0] twocmd;
+ wire [15:0] twodataOut;
+ wire [7:0] twophoneNum;
+
+
+ wire [15:0] twospkBufferOut;
+ wire twomicBufferFull;
+ wire twomicBufferEmpty;
+ wire twospkBufferFull;
+ wire twospkBufferEmpty;
+ wire [15:0] twomicBufferOut;
+
+ session two (
+ .clk(clk),
+ .reset(reset),
+ .phoneNum(twophoneNum),
+ .userInp(twouserInp),
+ .cmdIn(sendingToSession),
+ .packetIn(sessionData),
+ .transportBusy(twotransportBusy),
+ .cmd(twocmd),
+ .dataOut(twodataOut),
+ .sessionBusy(sessionBusy),
+ .phoneOut(twophoneOut),
+ .current_state(twocurrent_state),
+ .ac97_clk(clk),
+ .micBufferIn(16'b0),
+ .spkBufferOut(twomicBufferOut),
+ .micBufferFull(twomicBufferFull),
+ .micBufferEmpty(twomicBufferEmpty),
+ .spkBufferFull(twospkBufferFull),
+ .spkBufferEmpty(twospkBufferEmpty)
+ );
+
+ wire s2sending;
+ wire [7:0] s2sendPacketOut;
+ wire [10:0] s2senderCounter;
+
+ transportSend s2 (
+ .clk(clk),
+ .reset(reset),
+ .cmd(twocmd),
+ .data(twodataOut),
+ .sendData(1'b1),
+ .sending(s2sending),
+ .packetOut(s2sendPacketOut),
+ .busy(twotransportBusy),
+ .ready_data_count(s2senderCounter)
+ );
+
+
+ wire [7:0] r2dafuq;
+ wire [10:0] r2rcvCounter;
+
+ transportRcv r2 (
+ .clk(clk),
+ .reset(reset),
+ .rcvSignal(s2sending),
+ .packetIn(s2sendPacketOut),
+ .sessionBusy(onesessionBusy),
+ .sendingToSession(onecmdIn),
+ .data(onepacketInp),
+ .rcv_data_count(r2rcvCounter),
+ .dafuq(r2dafuq)
+ );
+
+
+endmodule
50 session and transport/sources/complete_tb.v
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@@ -0,0 +1,50 @@
+////////////////////////////////////////////////////////////////////////////////
+// Engineer: Kiarash Adl
+// Module Name: CompleteTest test bench
+////////////////////////////////////////////////////////////////////////////////
+
+module complete_tb;
+
+ // Inputs
+ reg clk;
+ reg reset;
+ reg [3:0] oneInp;
+ reg [3:0] twoInp;
+
+ // Outputs
+ wire [3:0] onecurrent_state;
+ wire [3:0] twocurrent_state;
+
+ // Instantiate the Unit Under Test (UUT)
+ complete uut (
+ .clk(clk),
+ .reset(reset),
+ .oneInp(oneInp),
+ .twoInp(twoInp),
+ .onecurrent_state(onecurrent_state),
+ .twocurrent_state(twocurrent_state)
+ );
+
+ always #5 clk=!clk;
+
+ initial begin
+ // Initialize Inputs
+ clk = 0;
+ reset = 0;
+ oneInp = 0;
+ twoInp = 0;
+
+ // Wait 100 ns for global reset to finish
+ #100;
+
+ // Add stimulus here
+ oneInp=4'h1;
+ #500;
+ twoInp=4'h5;
+
+
+
+ end
+
+endmodule
+
82 session and transport/sources/dummyBuffer.xco
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@@ -0,0 +1,82 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Tue Dec 11 23:30:28 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc2v6000
+SET devicefamily = virtex2
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = bf957
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -4
+SET verilogsim = True
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.4
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=dummyBuffer
+CSET data_count=true
+CSET data_count_width=10
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Common_Clock_Block_RAM
+CSET full_flags_reset_value=0
+CSET full_threshold_assert_value=1022
+CSET full_threshold_negate_value=1021
+CSET input_data_width=8
+CSET input_depth=1024
+CSET output_data_width=8
+CSET output_depth=1024
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=10
+CSET reset_pin=true
+CSET reset_type=Synchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=10
+# END Parameters
+GENERATE
+# CRC: 434e1b7
+
739 session and transport/sources/labkit.ucf
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@@ -0,0 +1,739 @@
+###############################################################################
+#
+# 6.111 FPGA Labkit -- Constraints File
+#
+# For Labkit Revision 004
+#
+#
+# Created: Oct 30, 2004 from revision 003 contraints file
+# Author: Nathan Ickes and Isaac Cambron
+#
+###############################################################################
+#
+# CHANGES FOR BOARD REVISION 004
+#
+# 1) Added signals for logic analyzer pods 2-4.
+# 2) Expanded tv_in_ycrcy bus to 20 bits.
+# 3) Renamed tv_out_sclk to tv_out_i2c_clock for consistency
+# 4) Renamed tv_out_data to tv_out_i2c_data for consistency
+# 5) Reversed disp_data_in and disp_data_out signals, so that "out" is an
+# output of the FPGA, and "in" is an input.
+#
+# CHANGES FOR BOARD REVISION 003
+#
+# 1) Combined flash chip enables into a single signal, flash_ce_b.
+# 2) Moved SRAM feedback clock loop to FPGA pins AL28 (out) and AJ16 (in).
+# 3) Moved rs232_rts to FPGA pin R3.
+# 4) Moved flash_address<1> to AE14.
+#
+# CHANGES FOR BOARD REVISION 002
+#
+# 1) Moved ZBT_BANK1_CLK signal to pin Y9.
+# 2) Moved user1<30> to J14.
+# 3) Moved user3<29> to J13.
+# 4) Added SRAM clock feedback loop between D15 and H15.
+# 5) Renamed ram#_parity and ram#_we#_b signals.
+# 6) Removed the constraint on "systemace_clock", since this net no longer
+# exists. The SystemACE clock is now hardwired to the 27MHz oscillator
+# on the PCB.
+#
+###############################################################################
+#
+# Complete change history (including bug fixes)
+#
+# 2007-Aug-16: Fixed revision history. (flash_address<1> was actually changed
+# to AE14 for revision 003.)
+#
+# 2005-Sep-09: Added missing IOSTANDARD attribute to "disp_data_out".
+#
+# 2005-Jan-23: Added a pullup to FLASH_STS
+#
+# 2005-Jan-23: Reduced flash address bus to 24 bits, to match 128Mb devices
+# actually populated on the boards. (The boards support up to
+# 256Mb devices, with 25 address lines.)
+#
+# 2005-Jan-23: Change history started.
+#
+###############################################################################
+
+#
+# Audio CODEC
+#
+
+NET "beep" LOC="ac19" | IOSTANDARD=LVDCI_33;
+NET "audio_reset_b" LOC="ae18" | IOSTANDARD=LVTTL;
+NET "ac97_sdata_out" LOC="ac18" | IOSTANDARD=LVDCI_33;
+NET "ac97_sdata_in" LOC="aj24";
+NET "ac97_synch" LOC="ac17" | IOSTANDARD=LVDCI_33;
+NET "ac97_bit_clock" LOC="ah24";
+
+#
+# VGA Output
+#
+
+NET "vga_out_red<7>" LOC="ae9" | IOSTANDARD=LVTTL;
+NET "vga_out_red<6>" LOC="ae8" | IOSTANDARD=LVTTL;
+NET "vga_out_red<5>" LOC="ad12" | IOSTANDARD=LVTTL;
+NET "vga_out_red<4>" LOC="af8" | IOSTANDARD=LVTTL;
+NET "vga_out_red<3>" LOC="af9" | IOSTANDARD=LVTTL;
+NET "vga_out_red<2>" LOC="ag9" | IOSTANDARD=LVTTL;
+NET "vga_out_red<1>" LOC="ag10" | IOSTANDARD=LVTTL;
+NET "vga_out_red<0>" LOC="af11" | IOSTANDARD=LVTTL;
+
+NET "vga_out_green<7>" LOC="ah8" | IOSTANDARD=LVTTL;
+NET "vga_out_green<6>" LOC="ah7" | IOSTANDARD=LVTTL;
+NET "vga_out_green<5>" LOC="aj6" | IOSTANDARD=LVTTL;
+NET "vga_out_green<4>" LOC="ah6" | IOSTANDARD=LVTTL;
+NET "vga_out_green<3>" LOC="ad15" | IOSTANDARD=LVTTL;
+NET "vga_out_green<2>" LOC="ac14" | IOSTANDARD=LVTTL;
+NET "vga_out_green<1>" LOC="ag8" | IOSTANDARD=LVTTL;
+NET "vga_out_green<0>" LOC="ac12" | IOSTANDARD=LVTTL;
+
+NET "vga_out_blue<7>" LOC="ag15" | IOSTANDARD=LVTTL;
+NET "vga_out_blue<6>" LOC="ag14" | IOSTANDARD=LVTTL;
+NET "vga_out_blue<5>" LOC="ag13" | IOSTANDARD=LVTTL;
+NET "vga_out_blue<4>" LOC="ag12" | IOSTANDARD=LVTTL;
+NET "vga_out_blue<3>" LOC="aj11" | IOSTANDARD=LVTTL;
+NET "vga_out_blue<2>" LOC="ah11" | IOSTANDARD=LVTTL;
+NET "vga_out_blue<1>" LOC="aj10" | IOSTANDARD=LVTTL;
+NET "vga_out_blue<0>" LOC="ah9" | IOSTANDARD=LVTTL;
+
+NET "vga_out_sync_b" LOC="aj9" | IOSTANDARD=LVTTL;
+NET "vga_out_blank_b" LOC="aj8" | IOSTANDARD=LVTTL;
+NET "vga_out_pixel_clock" LOC="ac10" | IOSTANDARD=LVTTL;
+NET "vga_out_hsync" LOC="ac13" | IOSTANDARD=LVTTL;
+NET "vga_out_vsync" LOC="ac11" | IOSTANDARD=LVTTL;
+
+#
+# Video Output
+#
+
+NET "tv_out_ycrcb<9>" LOC="p27" | IOSTANDARD=LVDCI_33;
+NET "tv_out_ycrcb<8>" LOC="r27" | IOSTANDARD=LVDCI_33;
+NET "tv_out_ycrcb<7>" LOC="t29" | IOSTANDARD=LVDCI_33;
+NET "tv_out_ycrcb<6>" LOC="h26" | IOSTANDARD=LVDCI_33;
+NET "tv_out_ycrcb<5>" LOC="j26" | IOSTANDARD=LVDCI_33;
+NET "tv_out_ycrcb<4>" LOC="l26" | IOSTANDARD=LVDCI_33;
+NET "tv_out_ycrcb<3>" LOC="m26" | IOSTANDARD=LVDCI_33;
+NET "tv_out_ycrcb<2>" LOC="n26" | IOSTANDARD=LVDCI_33;
+NET "tv_out_ycrcb<1>" LOC="p26" | IOSTANDARD=LVDCI_33;
+NET "tv_out_ycrcb<0>" LOC="r26" | IOSTANDARD=LVDCI_33;
+
+NET "tv_out_reset_b" LOC="g27" | IOSTANDARD=LVDCI_33;
+NET "tv_out_clock" LOC="l27" | IOSTANDARD=LVDCI_33;
+NET "tv_out_i2c_clock" LOC="j27" | IOSTANDARD=LVDCI_33;
+NET "tv_out_i2c_data" LOC="h27" | IOSTANDARD=LVDCI_33;
+NET "tv_out_pal_ntsc" LOC="j25" | IOSTANDARD=LVDCI_33;
+NET "tv_out_hsync_b" LOC="n27" | IOSTANDARD=LVDCI_33;
+NET "tv_out_vsync_b" LOC="m27" | IOSTANDARD=LVDCI_33;
+NET "tv_out_blank_b" LOC="h25" | IOSTANDARD=LVDCI_33;
+NET "tv_out_subcar_reset" LOC="k27" | IOSTANDARD=LVDCI_33;
+
+#
+# Video Input
+#
+
+NET "tv_in_ycrcb<19>" LOC="ag17";
+NET "tv_in_ycrcb<18>" LOC="ag18";
+NET "tv_in_ycrcb<17>" LOC="ag19";
+NET "tv_in_ycrcb<16>" LOC="ag20";
+NET "tv_in_ycrcb<15>" LOC="ae20";
+NET "tv_in_ycrcb<14>" LOC="af21";
+NET "tv_in_ycrcb<13>" LOC="ad20";
+NET "tv_in_ycrcb<12>" LOC="ag23";
+NET "tv_in_ycrcb<11>" LOC="aj26";
+NET "tv_in_ycrcb<10>" LOC="ah26";
+NET "tv_in_ycrcb<9>" LOC="w23";
+NET "tv_in_ycrcb<8>" LOC="v23";
+NET "tv_in_ycrcb<7>" LOC="u23";
+NET "tv_in_ycrcb<6>" LOC="t23";
+NET "tv_in_ycrcb<5>" LOC="t26";
+NET "tv_in_ycrcb<4>" LOC="t24";
+NET "tv_in_ycrcb<3>" LOC="r25";
+NET "tv_in_ycrcb<2>" LOC="l30";
+NET "tv_in_ycrcb<1>" LOC="m31";
+NET "tv_in_ycrcb<0>" LOC="m30";
+
+NET "tv_in_data_valid" LOC="ah25";
+NET "tv_in_line_clock1" LOC="ad16" | IOSTANDARD=LVDCI_33;
+NET "tv_in_line_clock2" LOC="ad17" | IOSTANDARD=LVDCI_33;
+NET "tv_in_aef" LOC="aj23";
+NET "tv_in_hff" LOC="ah23";
+NET "tv_in_aff" LOC="aj22";
+NET "tv_in_i2c_clock" LOC="ad21" | IOSTANDARD=LVDCI_33;
+NET "tv_in_i2c_data" LOC="ad19" | IOSTANDARD=LVDCI_33;
+NET "tv_in_fifo_read" LOC="ac22" | IOSTANDARD=LVDCI_33;
+NET "tv_in_fifo_clock" LOC="ag22" | IOSTANDARD=LVDCI_33;
+NET "tv_in_iso" LOC="aj27" | IOSTANDARD=LVDCI_33;
+NET "tv_in_reset_b" LOC="ag25" | IOSTANDARD=LVDCI_33;
+NET "tv_in_clock" LOC="ab21" | IOSTANDARD=LVDCI_33;
+
+#
+# SRAMs
+#
+
+NET "ram0_data<35>" LOC="ab25" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<34>" LOC="ah29" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<33>" LOC="ag28" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<32>" LOC="ag29" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<31>" LOC="af27" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<30>" LOC="af29" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<29>" LOC="af28" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<28>" LOC="ae28" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<27>" LOC="ad25" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<26>" LOC="aa25" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<25>" LOC="ah30" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<24>" LOC="ah31" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<23>" LOC="ag30" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<22>" LOC="ag31" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<21>" LOC="af30" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<20>" LOC="af31" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<19>" LOC="ae30" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<18>" LOC="ae31" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<17>" LOC="y27" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<16>" LOC="aa28" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<15>" LOC="y29" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<14>" LOC="y28" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<13>" LOC="w29" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<12>" LOC="w28" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<11>" LOC="v28" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<10>" LOC="u29" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<9>" LOC="u28" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<8>" LOC="aa27" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<7>" LOC="ad31" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<6>" LOC="ac30" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<5>" LOC="ac31" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<4>" LOC="ab30" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<3>" LOC="ab31" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<2>" LOC="aa30" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<1>" LOC="aa31" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram0_data<0>" LOC="y30" | IOSTANDARD=LVDCI_33 | NODELAY;
+
+NET "ram0_address<18>" LOC="v31" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<17>" LOC="w31" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<16>" LOC="ad28" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<15>" LOC="ad29" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<14>" LOC="ac24" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<13>" LOC="ad26" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<12>" LOC="ad27" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<11>" LOC="ac27" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<10>" LOC="ab27" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<9>" LOC="y31" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<8>" LOC="w30" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<7>" LOC="y26" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<6>" LOC="y25" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<5>" LOC="ab24" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<4>" LOC="ac25" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<3>" LOC="aa26" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<2>" LOC="aa24" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<1>" LOC="ab29" | IOSTANDARD=LVDCI_33;
+NET "ram0_address<0>" LOC="ac26" | IOSTANDARD=LVDCI_33;
+
+NET "ram0_adv_ld" LOC="v26" | IOSTANDARD=LVDCI_33;
+NET "ram0_clk" LOC="u30" | IOSTANDARD=LVDCI_33;
+NET "ram0_cen_b" LOC="u25" | IOSTANDARD=LVDCI_33;
+NET "ram0_ce_b" LOC="w26" | IOSTANDARD=LVDCI_33;
+NET "ram0_oe_b" LOC="v25" | IOSTANDARD=LVDCI_33;
+NET "ram0_we_b" LOC="u31" | IOSTANDARD=LVDCI_33;
+NET "ram0_bwe_b<0>" LOC="v27" | IOSTANDARD=LVDCI_33;
+NET "ram0_bwe_b<1>" LOC="u27" | IOSTANDARD=LVDCI_33;
+NET "ram0_bwe_b<2>" LOC="w27" | IOSTANDARD=LVDCI_33;
+NET "ram0_bwe_b<3>" LOC="u26" | IOSTANDARD=LVDCI_33;
+
+NET "ram1_data<35>" LOC="aa9" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<34>" LOC="ah2" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<33>" LOC="ah1" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<32>" LOC="ag2" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<31>" LOC="ag1" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<30>" LOC="af2" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<29>" LOC="af1" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<28>" LOC="ae2" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<27>" LOC="ae1" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<26>" LOC="ab9" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<25>" LOC="ah3" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<24>" LOC="ag4" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<23>" LOC="ag3" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<22>" LOC="af4" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<21>" LOC="af3" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<20>" LOC="ae4" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<19>" LOC="ae5" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<18>" LOC="ad5" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<17>" LOC="v2" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<16>" LOC="ad1" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<15>" LOC="ac2" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<14>" LOC="ac1" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<13>" LOC="ab2" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<12>" LOC="ab1" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<11>" LOC="aa2" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<10>" LOC="aa1" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<9>" LOC="y2" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<8>" LOC="v4" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<7>" LOC="ac3" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<6>" LOC="ac4" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<5>" LOC="aa5" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<4>" LOC="aa3" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<3>" LOC="aa4" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<2>" LOC="y3" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<1>" LOC="y4" | IOSTANDARD=LVDCI_33 | NODELAY;
+NET "ram1_data<0>" LOC="w3" | IOSTANDARD=LVDCI_33 | NODELAY;
+
+NET "ram1_address<18>" LOC="ab3" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<17>" LOC="ac5" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<16>" LOC="u6" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<15>" LOC="v6" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<14>" LOC="w6" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<13>" LOC="y6" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<12>" LOC="aa7" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<11>" LOC="ab7" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<10>" LOC="ac6" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<9>" LOC="ad3" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<8>" LOC="ad4" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<7>" LOC="u3" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<6>" LOC="w4" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<5>" LOC="ac8" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<4>" LOC="ab8" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<3>" LOC="aa8" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<2>" LOC="y7" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<1>" LOC="y8" | IOSTANDARD=LVDCI_33;
+NET "ram1_address<0>" LOC="ad7" | IOSTANDARD=LVDCI_33;
+
+NET "ram1_adv_ld" LOC="y5" | IOSTANDARD=LVDCI_33;
+NET "ram1_clk" LOC="y9" | IOSTANDARD=LVDCI_33;
+NET "ram1_cen_b" LOC="v5" | IOSTANDARD=LVDCI_33;
+NET "ram1_ce_b" LOC="u4" | IOSTANDARD=LVDCI_33;
+NET "ram1_oe_b" LOC="w5" | IOSTANDARD=LVDCI_33;
+NET "ram1_we_b" LOC="aa6" | IOSTANDARD=LVDCI_33;
+NET "ram1_bwe_b<0>" LOC="u2" | IOSTANDARD=LVDCI_33;
+NET "ram1_bwe_b<1>" LOC="u1" | IOSTANDARD=LVDCI_33;
+NET "ram1_bwe_b<2>" LOC="v1" | IOSTANDARD=LVDCI_33;
+NET "ram1_bwe_b<3>" LOC="u5" | IOSTANDARD=LVDCI_33;
+
+NET "clock_feedback_out" LOC="al28" | IOSTANDARD=LVDCI_33;
+NET "clock_feedback_in" LOC="aj16";
+
+#
+# Flash
+#
+
+NET "flash_data<15>" LOC="ak10" | IOSTANDARD=LVTTL;
+NET "flash_data<14>" LOC="ak11" | IOSTANDARD=LVTTL;
+NET "flash_data<13>" LOC="ak12" | IOSTANDARD=LVTTL;
+NET "flash_data<12>" LOC="ak13" | IOSTANDARD=LVTTL;
+NET "flash_data<11>" LOC="ak14" | IOSTANDARD=LVTTL;
+NET "flash_data<10>" LOC="ak15" | IOSTANDARD=LVTTL;
+NET "flash_data<9>" LOC="ah12" | IOSTANDARD=LVTTL;
+NET "flash_data<8>" LOC="ah13" | IOSTANDARD=LVTTL;
+NET "flash_data<7>" LOC="al10" | IOSTANDARD=LVTTL;
+NET "flash_data<6>" LOC="al11" | IOSTANDARD=LVTTL;
+NET "flash_data<5>" LOC="al12" | IOSTANDARD=LVTTL;
+NET "flash_data<4>" LOC="al13" | IOSTANDARD=LVTTL;
+NET "flash_data<3>" LOC="al14" | IOSTANDARD=LVTTL;
+NET "flash_data<2>" LOC="al15" | IOSTANDARD=LVTTL;
+NET "flash_data<1>" LOC="aj12" | IOSTANDARD=LVTTL;
+NET "flash_data<0>" LOC="aj13" | IOSTANDARD=LVTTL;
+
+NET "flash_address<24>" LOC="al7";
+NET "flash_address<23>" LOC="aj15";
+NET "flash_address<22>" LOC="al25";
+NET "flash_address<21>" LOC="ak23";
+NET "flash_address<20>" LOC="al23";
+NET "flash_address<19>" LOC="ak22";
+NET "flash_address<18>" LOC="al22";
+NET "flash_address<17>" LOC="ak21";
+NET "flash_address<16>" LOC="al21";
+NET "flash_address<15>" LOC="ak20";
+NET "flash_address<14>" LOC="al20";
+NET "flash_address<13>" LOC="ak19";
+NET "flash_address<12>" LOC="al19";
+NET "flash_address<11>" LOC="al18";
+NET "flash_address<10>" LOC="ak17";
+NET "flash_address<9>" LOC="al17";
+NET "flash_address<8>" LOC="ah21";
+NET "flash_address<7>" LOC="aj20";
+NET "flash_address<6>" LOC="ah20";
+NET "flash_address<5>" LOC="aj19";
+NET "flash_address<4>" LOC="ah19";
+NET "flash_address<3>" LOC="ah18";
+NET "flash_address<2>" LOC="aj17";
+NET "flash_address<1>" LOC="ae14";
+NET "flash_address<0>" LOC="ah14";
+
+NET "flash_ce_b" LOC="aj21" | IOSTANDARD=LVDCI_33;
+
+NET "flash_oe_b" LOC="ak9" | IOSTANDARD=LVDCI_33;
+NET "flash_we_b" LOC="al8" | IOSTANDARD=LVDCI_33;
+NET "flash_reset_b" LOC="ak18" | IOSTANDARD=LVDCI_33;
+NET "flash_sts" LOC="al9" | PULLUP;
+NET "flash_byte_b" LOC="ah15" | IOSTANDARD=LVDCI_33;
+
+#
+# RS-232
+#
+
+NET "rs232_txd" LOC="p4" | IOSTANDARD=LVDCI_33;
+NET "rs232_rxd" LOC="p6";
+NET "rs232_rts" LOC="r3" | IOSTANDARD=LVDCI_33;
+NET "rs232_cts" LOC="n8";
+
+#
+# Mouse and Keyboard
+#
+
+NET "mouse_clock" LOC="ac16";
+NET "mouse_data" LOC="ac15";
+NET "keyboard_clock" LOC="ag16";
+NET "keyboard_data" LOC="af16";
+
+#
+# Clocks
+#
+
+NET "clock_27mhz" LOC="c16";
+NET "clock1" LOC="h16";
+NET "clock2" LOC="c15";
+
+#
+# Alphanumeric Display
+#
+
+NET "disp_blank" LOC="af12" | IOSTANDARD=LVDCI_33;
+NET "disp_data_in" LOC="ae12";
+NET "disp_clock" LOC="af14" | IOSTANDARD=LVDCI_33;
+NET "disp_rs" LOC="af15" | IOSTANDARD=LVDCI_33;
+NET "disp_ce_b" LOC="af13" | IOSTANDARD=LVDCI_33;
+NET "disp_reset_b" LOC="ag11" | IOSTANDARD=LVDCI_33;
+NET "disp_data_out" LOC="ae15" | IOSTANDARD=LVDCI_33;
+
+#
+# Buttons and Switches
+#
+
+NET "button0" LOC="ae11";
+NET "button1" LOC="ae10";
+NET "button2" LOC="ad11";
+NET "button3" LOC="ab12";
+NET "button_enter" LOC="ak7";
+NET "button_right" LOC="al6";
+NET "button_left" LOC="al5";
+NET "button_up" LOC="al4";
+NET "button_down" LOC="ak6";
+
+NET "switch<7>" LOC="ad22";
+NET "switch<6>" LOC="ae23";
+NET "switch<5>" LOC="ac20";
+NET "switch<4>" LOC="ab20";
+NET "switch<3>" LOC="ac21";
+NET "switch<2>" LOC="ak25";
+NET "switch<1>" LOC="al26";
+NET "switch<0>" LOC="ak26";
+
+#
+# Discrete LEDs
+#
+
+NET "led<7>" LOC="ae17" | IOSTANDARD=LVTTL;
+NET "led<6>" LOC="af17" | IOSTANDARD=LVTTL;
+NET "led<5>" LOC="af18" | IOSTANDARD=LVTTL;
+NET "led<4>" LOC="af19" | IOSTANDARD=LVTTL;
+NET "led<3>" LOC="af20" | IOSTANDARD=LVTTL;
+NET "led<2>" LOC="ag21" | IOSTANDARD=LVTTL;
+NET "led<1>" LOC="ae21" | IOSTANDARD=LVTTL;
+NET "led<0>" LOC="ae22" | IOSTANDARD=LVTTL;
+
+
+#
+# User Pins
+#
+
+NET "user1<31>" LOC="j15" | IOSTANDARD=LVTTL;
+NET "user1<30>" LOC="j14" | IOSTANDARD=LVTTL;
+NET "user1<29>" LOC="g15" | IOSTANDARD=LVTTL;
+NET "user1<28>" LOC="f14" | IOSTANDARD=LVTTL;
+NET "user1<27>" LOC="f12" | IOSTANDARD=LVTTL;
+NET "user1<26>" LOC="h11" | IOSTANDARD=LVTTL;
+NET "user1<25>" LOC="g9" | IOSTANDARD=LVTTL;
+NET "user1<24>" LOC="h9" | IOSTANDARD=LVTTL;
+NET "user1<23>" LOC="b15" | IOSTANDARD=LVTTL;
+NET "user1<22>" LOC="b14" | IOSTANDARD=LV