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##############################################################
#
# Xilinx Core Generator version 14.2
# Date: Sun Dec 2 21:17:26 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:div_gen:4.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Divider_Generator xilinx.com:ip:div_gen:4.0
# END Select
# BEGIN Parameters
CSET aclken=false
CSET algorithm_type=Radix2
CSET aresetn=false
CSET clocks_per_division=1
CSET component_name=s26_s13_div
CSET divide_by_zero_detect=false
CSET dividend_and_quotient_width=26
CSET dividend_has_tlast=false
CSET dividend_has_tuser=false
CSET dividend_tuser_width=1
CSET divisor_has_tlast=false
CSET divisor_has_tuser=false
CSET divisor_tuser_width=1
CSET divisor_width=13
CSET flowcontrol=NonBlocking
CSET fractional_width=13
CSET latency=43
CSET latency_configuration=Automatic
CSET operand_sign=Signed
CSET optimizegoal=Performance
CSET outtlastbehv=Null
CSET outtready=false
CSET remainder_type=Fractional
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-06-22T13:39:12Z
# END Extra information
GENERATE
# CRC: e22cc94