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##############################################################
#
# Xilinx Core Generator version 14.2
# Date: Mon Dec 31 18:00:27 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:c_addsub:11.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0
# END Select
# BEGIN Parameters
CSET a_type=Signed
CSET a_width=36
CSET add_mode=Add
CSET ainit_value=0
CSET b_constant=false
CSET b_type=Signed
CSET b_value=000000000000000000000000000000000000
CSET b_width=36
CSET borrow_sense=Active_Low
CSET bypass=false
CSET bypass_ce_priority=CE_Overrides_Bypass
CSET bypass_sense=Active_High
CSET c_in=false
CSET c_out=false
CSET ce=false
CSET component_name=s36_add
CSET implementation=DSP48
CSET latency=0
CSET latency_configuration=Manual
CSET out_width=36
CSET sclr=false
CSET sinit=false
CSET sinit_value=0
CSET sset=false
CSET sync_ce_priority=Sync_Overrides_CE
CSET sync_ctrl_priority=Reset_Overrides_Set
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-06-22T15:32:25Z
# END Extra information
GENERATE
# CRC: 9a22ce39
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