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considering back emf to be done for now, fixed sign issue

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1 parent f50d815 commit 0e141a68ce588a5cb77890fdc44bd7044e5b5cca Josh S committed Dec 22, 2012
Showing with 1,760 additions and 63 deletions.
  1. +9 −9 auto_adc_updater.v
  2. +31 −18 bemf_update.v
  3. BIN kovan.bit
  4. +43 −34 kovan.v
  5. +3 −2 quad_motor.v
  6. +348 −0 s22_add.v
  7. +73 −0 s22_add.xco
  8. +348 −0 s22_sub.v
  9. +73 −0 s22_sub.xco
  10. +343 −0 s26_add.v
  11. +73 −0 s26_add.xco
  12. +343 −0 s26_sub.v
  13. +73 −0 s26_sub.xco
View
18 auto_adc_updater.v
@@ -4,7 +4,7 @@ module auto_adc_updater(
input clk3p2M,
input [9:0] adc_in,
input adc_valid,
- //input bemf_sensing,
+ input bemf_sensing,
output adc_go,
output [3:0] adc_chan,
output [9:0] adc_0_in,
@@ -125,14 +125,14 @@ module auto_adc_updater(
5'd5: adc_5_in_r <= adc_in;
5'd6: adc_6_in_r <= adc_in;
5'd7: adc_7_in_r <= adc_in;
- 5'd8: adc_8_in_r <= adc_in;
- 5'd9: adc_9_in_r <= adc_in;
- 5'd10: adc_10_in_r <= adc_in;
- 5'd11: adc_11_in_r <= adc_in;
- 5'd12: adc_12_in_r <= adc_in;
- 5'd13: adc_13_in_r <= adc_in;
- 5'd14: adc_14_in_r <= adc_in;
- 5'd15: adc_15_in_r <= adc_in;
+ 5'd8: if (bemf_sensing) adc_8_in_r <= adc_in;
+ 5'd9: if (bemf_sensing) adc_9_in_r <= adc_in;
+ 5'd10: if (bemf_sensing) adc_10_in_r <= adc_in;
+ 5'd11: if (bemf_sensing) adc_11_in_r <= adc_in;
+ 5'd12: if (bemf_sensing) adc_12_in_r <= adc_in;
+ 5'd13: if (bemf_sensing) adc_13_in_r <= adc_in;
+ 5'd14: if (bemf_sensing) adc_14_in_r <= adc_in;
+ 5'd15: if (bemf_sensing) adc_15_in_r <= adc_in;
5'd16: adc_16_in_r <= adc_in;
default:;
endcase
View
49 bemf_update.v
@@ -5,10 +5,10 @@ module bemf_update(
input [9:0] bemf_adc_l,
input [1:0] mot_sel_in,
input in_valid,
- input [15:0] bemf_in,
- input [15:0] bemf_calib_in,
+ input [21:0] bemf_in,
+ input [21:0] bemf_calib_in,
input clk,
- output [15:0] bemf_out,
+ output [21:0] bemf_out,
output [1:0] mot_sel_out,
output out_valid
);
@@ -17,30 +17,30 @@ module bemf_update(
// subtract the high and low side of the motor
reg [9:0] bemf_sub_in_a_r = 10'd0;
reg [9:0] bemf_sub_in_b_r = 10'd0;
- wire [15:0] bemf_sub_out;
- s16_sub bemf_sub(
- .a({6'd0, bemf_sub_in_a_r}),
- .b({6'd0, bemf_sub_in_b_r}),
+ wire [21:0] bemf_sub_out;
+ s22_sub bemf_sub(
+ .a({16'd0, bemf_sub_in_a_r}),
+ .b({16'd0, bemf_sub_in_b_r}),
.s(bemf_sub_out)
);
// adjust by the calibration amount
- reg [15:0] calib_sub_in_a_r = 16'd0;
- reg [15:0] calib_sub_in_b_r = 16'd0;
- wire [15:0] calib_sub_out;
- s16_sub calib_sub(
+ reg [21:0] calib_sub_in_a_r = 22'd0;
+ reg [21:0] calib_sub_in_b_r = 22'd0;
+ wire [21:0] calib_sub_out;
+ s22_sub calib_sub(
.a(calib_sub_in_a_r),
.b(calib_sub_in_b_r),
.s(calib_sub_out)
);
// integrate the calibrated back emf readings
- reg [15:0] bemf_integr_in_a_r = 16'd0;
- reg [15:0] bemf_integr_in_b_r = 16'd0;
- wire [15:0] bemf_integr_out;
- s16_add bemf_integr(
+ reg [21:0] bemf_integr_in_a_r = 22'd0;
+ reg [21:0] bemf_integr_in_b_r = 22'd0;
+ wire [21:0] bemf_integr_out;
+ s22_add bemf_integr(
.a(bemf_integr_in_a_r),
.b(bemf_integr_in_b_r),
.s(bemf_integr_out)
@@ -57,7 +57,10 @@ module bemf_update(
reg in_valid_2 = 1'd0;
reg in_valid_3 = 1'd0;
- reg [15:0] bemf_out_r = 16'd0;
+ reg [21:0] bemf_out_r = 22'd0;
+
+ reg [21:0] bemf_in_0 = 22'd0;
+ reg [21:0] bemf_in_1 = 22'd0;
always @ (posedge clk) begin
@@ -66,18 +69,28 @@ module bemf_update(
bemf_sub_in_b_r <= bemf_adc_l;
in_valid_0 <= in_valid;
mot_sel_in_0 <= mot_sel_in;
+ bemf_in_0 <= bemf_in;
// pipeline stage 1: calculated (bemf_high - bemf_low)
calib_sub_in_a_r <= bemf_sub_out;
calib_sub_in_b_r <= bemf_calib_in;
in_valid_1 <= in_valid_0;
mot_sel_in_1 <= mot_sel_in_0;
+ bemf_in_1 <= bemf_in_0;
+
// pipeline stage 2: subtracted the calibration info
- bemf_integr_in_a_r <= calib_sub_out;
- bemf_integr_in_b_r <= bemf_in;
+
+ // deadbanding
+ if (calib_sub_out[21] == 1'b1)
+ bemf_integr_in_a_r <= (~calib_sub_out > 22'd21) ? calib_sub_out : 22'd0; //negative
+ else
+ bemf_integr_in_a_r <= (calib_sub_out > 22'd20) ? calib_sub_out : 22'd0; // positive
+
+ //bemf_integr_in_a_r <= calib_sub_out;
+ bemf_integr_in_b_r <= bemf_in_1;
in_valid_2 <= in_valid_1;
mot_sel_in_2 <= mot_sel_in_1;
View
BIN kovan.bit
Binary file not shown.
View
77 kovan.v
@@ -312,26 +312,26 @@ module kovan (
reg [9:0] adc_15_new;
reg [9:0] adc_16_new;
- wire [15:0] bemf_0;
- wire [15:0] bemf_1;
- wire [15:0] bemf_2;
- wire [15:0] bemf_3;
+ wire [21:0] bemf_0;
+ wire [21:0] bemf_1;
+ wire [21:0] bemf_2;
+ wire [21:0] bemf_3;
- reg [15:0] bemf_0_r;
- reg [15:0] bemf_1_r;
- reg [15:0] bemf_2_r;
- reg [15:0] bemf_3_r;
+ reg [21:0] bemf_0_r;
+ reg [21:0] bemf_1_r;
+ reg [21:0] bemf_2_r;
+ reg [21:0] bemf_3_r;
- reg [15:0] bemf_0_r_208M = 16'd0;
- reg [15:0] bemf_1_r_208M = 16'd0;
- reg [15:0] bemf_2_r_208M = 16'd0;
- reg [15:0] bemf_3_r_208M = 16'd0;
+ reg [21:0] bemf_0_r_208M = 22'd0;
+ reg [21:0] bemf_1_r_208M = 22'd0;
+ reg [21:0] bemf_2_r_208M = 22'd0;
+ reg [21:0] bemf_3_r_208M = 22'd0;
- reg [15:0] bemf_0_calib = 16'd0;
- reg [15:0] bemf_1_calib = 16'd0;
- reg [15:0] bemf_2_calib = 16'd0;
- reg [15:0] bemf_3_calib = 16'd0;
+ reg [21:0] bemf_0_calib = 22'd0;
+ reg [21:0] bemf_1_calib = 22'd0;
+ reg [21:0] bemf_2_calib = 22'd0;
+ reg [21:0] bemf_3_calib = 22'd0;
reg [11:0] mot_duty0_old = 12'd0;
@@ -424,6 +424,9 @@ module kovan (
assign bemf_2 = bemf_2_r_208M;
assign bemf_3 = bemf_3_r_208M;
+ wire bemf_sensing;
+ reg bemf_sensing_r = 1'd0;
+ assign bemf_sensing = bemf_sensing_r;
always @ (posedge clk208M) begin
@@ -503,12 +506,12 @@ module kovan (
reg [9:0] bemf_adc_l = 10'd0;
reg [1:0] bemf_mot_sel_in = 2'd0;
reg bemf_in_valid = 1'd0;
- reg [15:0] bemf_in = 16'd0;
- reg [15:0] bemf_calib_in = 16'd0;
+ reg [21:0] bemf_in = 22'd0;
+ reg [21:0] bemf_calib_in = 22'd0;
wire [1:0] bemf_mot_sel_out;
wire bemf_out_valid;
- wire [15:0] bemf_out;
+ wire [21:0] bemf_out;
reg [15:0] bemf_counter = 16'd0; // can count for up to ~20mS
reg [2:0] bemf_state = 3'd0;
@@ -552,6 +555,7 @@ module kovan (
3'd0: begin
bemf_counter <= bemf_counter + 1'd1;
bemf_in_valid <= 1'd0;
+ bemf_sensing_r <= 1'd0;
if (bemf_counter > 3200) // 1mS
bemf_state <= bemf_state + 1'd1;
@@ -563,7 +567,9 @@ module kovan (
3'd1: begin
bemf_counter <= bemf_counter + 1'd1;
bemf_in_valid <= 1'd0;
- if (bemf_counter > 6400) // 2mS
+ bemf_sensing_r <= 1'd1;
+
+ if (bemf_counter > 12800) // 4mS
bemf_state <= bemf_state + 1'd1;
else
bemf_state <= bemf_state;
@@ -573,11 +579,12 @@ module kovan (
3'd2: begin
bemf_counter <= bemf_counter + 1'd1;
bemf_state <= bemf_state + 1'd1;
- bemf_adc_h <= adc_8_in;
- bemf_adc_l <= adc_9_in;
+ bemf_adc_h <= adc_9_in;
+ bemf_adc_l <= adc_8_in;
bemf_mot_sel_in <= 2'd0;
bemf_in_valid <= 1'd1;
bemf_in <= bemf_0;
+ bemf_sensing_r <= 1'd0;
bemf_calib_in <= bemf_0_calib;
end
@@ -586,8 +593,8 @@ module kovan (
3'd3: begin
bemf_counter <= bemf_counter + 1'd1;
bemf_state <= bemf_state + 1'd1;
- bemf_adc_h <= adc_10_in;
- bemf_adc_l <= adc_11_in;
+ bemf_adc_h <= adc_11_in;
+ bemf_adc_l <= adc_10_in;
bemf_mot_sel_in <= 2'd1;
bemf_in_valid <= 1'd1;
bemf_in <= bemf_1;
@@ -599,8 +606,8 @@ module kovan (
3'd4: begin
bemf_counter <= bemf_counter + 1'd1;
bemf_state <= bemf_state + 1'd1;
- bemf_adc_h <= adc_12_in;
- bemf_adc_l <= adc_13_in;
+ bemf_adc_h <= adc_13_in;
+ bemf_adc_l <= adc_12_in;
bemf_mot_sel_in <= 2'd2;
bemf_in_valid <= 1'd1;
bemf_in <= bemf_2;
@@ -612,8 +619,8 @@ module kovan (
3'd5: begin
bemf_counter <= bemf_counter + 1'd1;
bemf_state <= bemf_state + 1'd1;
- bemf_adc_h <= adc_14_in;
- bemf_adc_l <= adc_15_in;
+ bemf_adc_h <= adc_15_in;
+ bemf_adc_l <= adc_14_in;
bemf_mot_sel_in <= 2'd3;
bemf_in_valid <= 1'd1;
bemf_in <= bemf_3;
@@ -625,7 +632,7 @@ module kovan (
3'd6: begin
bemf_in_valid <= 1'd0;
- if (bemf_counter > 32000) begin// 10mS total
+ if (bemf_counter > 64000) begin// 20mS total
bemf_state <= bemf_state + 1'd1;
bemf_counter <= bemf_counter + 1'd1;
end else begin
@@ -636,6 +643,7 @@ module kovan (
default: begin
bemf_state <= 3'd0;
+ bemf_sensing_r <= 1'd0;
bemf_counter <= 16'd0;
end
endcase
@@ -685,10 +693,10 @@ module kovan (
.adc_15_in(adc_15_old),
.adc_16_in(adc_16_old),
.charge_acp_in(CHG_ACP),
- .bemf_0(bemf_0_r_208M),
- .bemf_1(bemf_1_r_208M),
- .bemf_2(bemf_2_r_208M),
- .bemf_3(bemf_3_r_208M),
+ .bemf_0(bemf_0_r_208M[21:6]),
+ .bemf_1(bemf_1_r_208M[21:6]),
+ .bemf_2(bemf_2_r_208M[21:6]),
+ .bemf_3(bemf_3_r_208M[21:6]),
.servo_pwm0_high(servo_pwm0_old),
.servo_pwm1_high(servo_pwm1_old),
.servo_pwm2_high(servo_pwm2_old),
@@ -775,6 +783,7 @@ module kovan (
.duty2(mot_duty2),
.duty3(mot_duty3),
.drive_code(mot_drive_code),
+ .bemf_sensing(bemf_sensing),
.pwm(MOT_PWM),
.MBOT(MBOT[3:0]),
.MTOP(MTOP[3:0])
@@ -784,7 +793,7 @@ module kovan (
.clk3p2M(clk3p2M),
.adc_in(adc_in),
.adc_valid(adc_valid),
- //.bemf_sensing(bemf_sensing),
+ .bemf_sensing(bemf_sensing),
.adc_go(adc_go),
.adc_chan(adc_chan),
.adc_0_in(adc_0_in),
View
5 quad_motor.v
@@ -31,6 +31,7 @@ module quad_motor(
input [11:0] duty2,
input [11:0] duty3,
input [7:0] drive_code,
+ input bemf_sensing,
output pwm,
output [3:0] MBOT,
output [3:0] MTOP
@@ -41,8 +42,8 @@ module quad_motor(
reg [3:0] MTOP_r = 4'b0000;
reg [11:0] count = 12'h0000;
- assign MBOT[3:0] = MTOP_r[3:0];
- assign MTOP[3:0] = MBOT_r[3:0];
+ assign MBOT[3:0] = MTOP_r[3:0] & {~bemf_sensing,~bemf_sensing,~bemf_sensing,~bemf_sensing};
+ assign MTOP[3:0] = MBOT_r[3:0] & {~bemf_sensing,~bemf_sensing,~bemf_sensing,~bemf_sensing};
reg pwm_r;
assign pwm = pwm_r;
View
348 s22_add.v
@@ -0,0 +1,348 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: P.28xd
+// \ \ Application: netgen
+// / / Filename: s22_add.v
+// /___/ /\ Timestamp: Sat Dec 22 12:41:52 2012
+// \ \ / \
+// \___\/\___\
+//
+// Command : -w -sim -ofmt verilog /home/josh/got/kovan-fpga/tmp/_cg/s22_add.ngc /home/josh/got/kovan-fpga/tmp/_cg/s22_add.v
+// Device : 6slx9csg324-2
+// Input file : /home/josh/got/kovan-fpga/tmp/_cg/s22_add.ngc
+// Output file : /home/josh/got/kovan-fpga/tmp/_cg/s22_add.v
+// # of Modules : 1
+// Design Name : s22_add
+// Xilinx : /opt/Xilinx/14.2/ISE_DS/ISE/
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module s22_add (
+a, b, s
+)/* synthesis syn_black_box syn_noprune=1 */;
+ input [21 : 0] a;
+ input [21 : 0] b;
+ output [21 : 0] s;
+
+ // synthesis translate_off
+
+ wire sig00000001;
+ wire sig00000002;
+ wire NLW_blk00000003_CARRYOUTF_UNCONNECTED;
+ wire NLW_blk00000003_CARRYOUT_UNCONNECTED;
+ wire \NLW_blk00000003_BCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<0>_UNCONNECTED ;
+ VCC blk00000001 (
+ .P(sig00000002)
+ );
+ GND blk00000002 (
+ .G(sig00000001)
+ );
+ DSP48A1 #(
+ .A0REG ( 0 ),
+ .A1REG ( 0 ),
+ .B0REG ( 0 ),
+ .B1REG ( 0 ),
+ .CARRYINREG ( 0 ),
+ .CARRYINSEL ( "OPMODE5" ),
+ .CREG ( 0 ),
+ .DREG ( 0 ),
+ .MREG ( 0 ),
+ .OPMODEREG ( 0 ),
+ .PREG ( 0 ),
+ .RSTTYPE ( "SYNC" ),
+ .CARRYOUTREG ( 0 ))
+ blk00000003 (
+ .CECARRYIN(sig00000001),
+ .RSTC(sig00000001),
+ .RSTCARRYIN(sig00000001),
+ .CED(sig00000001),
+ .RSTD(sig00000001),
+ .CEOPMODE(sig00000001),
+ .CEC(sig00000001),
+ .CARRYOUTF(NLW_blk00000003_CARRYOUTF_UNCONNECTED),
+ .RSTOPMODE(sig00000001),
+ .RSTM(sig00000001),
+ .CLK(sig00000001),
+ .RSTB(sig00000001),
+ .CEM(sig00000001),
+ .CEB(sig00000001),
+ .CARRYIN(sig00000001),
+ .CEP(sig00000001),
+ .CEA(sig00000001),
+ .CARRYOUT(NLW_blk00000003_CARRYOUT_UNCONNECTED),
+ .RSTA(sig00000001),
+ .RSTP(sig00000001),
+ .B({b[17], b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+ .BCOUT({\NLW_blk00000003_BCOUT<17>_UNCONNECTED , \NLW_blk00000003_BCOUT<16>_UNCONNECTED , \NLW_blk00000003_BCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<14>_UNCONNECTED , \NLW_blk00000003_BCOUT<13>_UNCONNECTED , \NLW_blk00000003_BCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<11>_UNCONNECTED , \NLW_blk00000003_BCOUT<10>_UNCONNECTED , \NLW_blk00000003_BCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<8>_UNCONNECTED , \NLW_blk00000003_BCOUT<7>_UNCONNECTED , \NLW_blk00000003_BCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<5>_UNCONNECTED , \NLW_blk00000003_BCOUT<4>_UNCONNECTED , \NLW_blk00000003_BCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<2>_UNCONNECTED , \NLW_blk00000003_BCOUT<1>_UNCONNECTED , \NLW_blk00000003_BCOUT<0>_UNCONNECTED }),
+ .PCIN({sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001}),
+ .C({a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21],
+a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[20], a[19], a[18], a[17], a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6],
+a[5], a[4], a[3], a[2], a[1], a[0]}),
+ .P({\NLW_blk00000003_P<47>_UNCONNECTED , \NLW_blk00000003_P<46>_UNCONNECTED , \NLW_blk00000003_P<45>_UNCONNECTED ,
+\NLW_blk00000003_P<44>_UNCONNECTED , \NLW_blk00000003_P<43>_UNCONNECTED , \NLW_blk00000003_P<42>_UNCONNECTED , \NLW_blk00000003_P<41>_UNCONNECTED ,
+\NLW_blk00000003_P<40>_UNCONNECTED , \NLW_blk00000003_P<39>_UNCONNECTED , \NLW_blk00000003_P<38>_UNCONNECTED , \NLW_blk00000003_P<37>_UNCONNECTED ,
+\NLW_blk00000003_P<36>_UNCONNECTED , \NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED ,
+\NLW_blk00000003_P<32>_UNCONNECTED , \NLW_blk00000003_P<31>_UNCONNECTED , \NLW_blk00000003_P<30>_UNCONNECTED , \NLW_blk00000003_P<29>_UNCONNECTED ,
+\NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED ,
+\NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , s[21], s[20], s[19], s[18], s[17],
+s[16], s[15], s[14], s[13], s[12], s[11], s[10], s[9], s[8], s[7], s[6], s[5], s[4], s[3], s[2], s[1], s[0]}),
+ .OPMODE({sig00000001, sig00000001, sig00000001, sig00000001, sig00000002, sig00000002, sig00000002, sig00000002}),
+ .D({b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21]}),
+ .PCOUT({\NLW_blk00000003_PCOUT<47>_UNCONNECTED , \NLW_blk00000003_PCOUT<46>_UNCONNECTED , \NLW_blk00000003_PCOUT<45>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<44>_UNCONNECTED , \NLW_blk00000003_PCOUT<43>_UNCONNECTED , \NLW_blk00000003_PCOUT<42>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<41>_UNCONNECTED , \NLW_blk00000003_PCOUT<40>_UNCONNECTED , \NLW_blk00000003_PCOUT<39>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<38>_UNCONNECTED , \NLW_blk00000003_PCOUT<37>_UNCONNECTED , \NLW_blk00000003_PCOUT<36>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<35>_UNCONNECTED , \NLW_blk00000003_PCOUT<34>_UNCONNECTED , \NLW_blk00000003_PCOUT<33>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<32>_UNCONNECTED , \NLW_blk00000003_PCOUT<31>_UNCONNECTED , \NLW_blk00000003_PCOUT<30>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<29>_UNCONNECTED , \NLW_blk00000003_PCOUT<28>_UNCONNECTED , \NLW_blk00000003_PCOUT<27>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<26>_UNCONNECTED , \NLW_blk00000003_PCOUT<25>_UNCONNECTED , \NLW_blk00000003_PCOUT<24>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<23>_UNCONNECTED , \NLW_blk00000003_PCOUT<22>_UNCONNECTED , \NLW_blk00000003_PCOUT<21>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<20>_UNCONNECTED , \NLW_blk00000003_PCOUT<19>_UNCONNECTED , \NLW_blk00000003_PCOUT<18>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<17>_UNCONNECTED , \NLW_blk00000003_PCOUT<16>_UNCONNECTED , \NLW_blk00000003_PCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<14>_UNCONNECTED , \NLW_blk00000003_PCOUT<13>_UNCONNECTED , \NLW_blk00000003_PCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<11>_UNCONNECTED , \NLW_blk00000003_PCOUT<10>_UNCONNECTED , \NLW_blk00000003_PCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<8>_UNCONNECTED , \NLW_blk00000003_PCOUT<7>_UNCONNECTED , \NLW_blk00000003_PCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<5>_UNCONNECTED , \NLW_blk00000003_PCOUT<4>_UNCONNECTED , \NLW_blk00000003_PCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<2>_UNCONNECTED , \NLW_blk00000003_PCOUT<1>_UNCONNECTED , \NLW_blk00000003_PCOUT<0>_UNCONNECTED }),
+ .A({b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[20], b[19], b[18]}),
+ .M({\NLW_blk00000003_M<35>_UNCONNECTED , \NLW_blk00000003_M<34>_UNCONNECTED , \NLW_blk00000003_M<33>_UNCONNECTED ,
+\NLW_blk00000003_M<32>_UNCONNECTED , \NLW_blk00000003_M<31>_UNCONNECTED , \NLW_blk00000003_M<30>_UNCONNECTED , \NLW_blk00000003_M<29>_UNCONNECTED ,
+\NLW_blk00000003_M<28>_UNCONNECTED , \NLW_blk00000003_M<27>_UNCONNECTED , \NLW_blk00000003_M<26>_UNCONNECTED , \NLW_blk00000003_M<25>_UNCONNECTED ,
+\NLW_blk00000003_M<24>_UNCONNECTED , \NLW_blk00000003_M<23>_UNCONNECTED , \NLW_blk00000003_M<22>_UNCONNECTED , \NLW_blk00000003_M<21>_UNCONNECTED ,
+\NLW_blk00000003_M<20>_UNCONNECTED , \NLW_blk00000003_M<19>_UNCONNECTED , \NLW_blk00000003_M<18>_UNCONNECTED , \NLW_blk00000003_M<17>_UNCONNECTED ,
+\NLW_blk00000003_M<16>_UNCONNECTED , \NLW_blk00000003_M<15>_UNCONNECTED , \NLW_blk00000003_M<14>_UNCONNECTED , \NLW_blk00000003_M<13>_UNCONNECTED ,
+\NLW_blk00000003_M<12>_UNCONNECTED , \NLW_blk00000003_M<11>_UNCONNECTED , \NLW_blk00000003_M<10>_UNCONNECTED , \NLW_blk00000003_M<9>_UNCONNECTED ,
+\NLW_blk00000003_M<8>_UNCONNECTED , \NLW_blk00000003_M<7>_UNCONNECTED , \NLW_blk00000003_M<6>_UNCONNECTED , \NLW_blk00000003_M<5>_UNCONNECTED ,
+\NLW_blk00000003_M<4>_UNCONNECTED , \NLW_blk00000003_M<3>_UNCONNECTED , \NLW_blk00000003_M<2>_UNCONNECTED , \NLW_blk00000003_M<1>_UNCONNECTED ,
+\NLW_blk00000003_M<0>_UNCONNECTED })
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
View
73 s22_add.xco
@@ -0,0 +1,73 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.2
+# Date: Sat Dec 22 18:41:20 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:c_addsub:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0
+# END Select
+# BEGIN Parameters
+CSET a_type=Signed
+CSET a_width=22
+CSET add_mode=Add
+CSET ainit_value=0
+CSET b_constant=false
+CSET b_type=Signed
+CSET b_value=0000000000000000000000
+CSET b_width=22
+CSET borrow_sense=Active_Low
+CSET bypass=false
+CSET bypass_ce_priority=CE_Overrides_Bypass
+CSET bypass_sense=Active_High
+CSET c_in=false
+CSET c_out=false
+CSET ce=false
+CSET component_name=s22_add
+CSET implementation=DSP48
+CSET latency=0
+CSET latency_configuration=Manual
+CSET out_width=22
+CSET sclr=false
+CSET sinit=false
+CSET sinit_value=0
+CSET sset=false
+CSET sync_ce_priority=Sync_Overrides_CE
+CSET sync_ctrl_priority=Reset_Overrides_Set
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-06-22T15:32:25Z
+# END Extra information
+GENERATE
+# CRC: 1ce7f343
View
348 s22_sub.v
@@ -0,0 +1,348 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: P.28xd
+// \ \ Application: netgen
+// / / Filename: s22_sub.v
+// /___/ /\ Timestamp: Sat Dec 22 12:42:49 2012
+// \ \ / \
+// \___\/\___\
+//
+// Command : -w -sim -ofmt verilog /home/josh/got/kovan-fpga/tmp/_cg/s22_sub.ngc /home/josh/got/kovan-fpga/tmp/_cg/s22_sub.v
+// Device : 6slx9csg324-2
+// Input file : /home/josh/got/kovan-fpga/tmp/_cg/s22_sub.ngc
+// Output file : /home/josh/got/kovan-fpga/tmp/_cg/s22_sub.v
+// # of Modules : 1
+// Design Name : s22_sub
+// Xilinx : /opt/Xilinx/14.2/ISE_DS/ISE/
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module s22_sub (
+a, b, s
+)/* synthesis syn_black_box syn_noprune=1 */;
+ input [21 : 0] a;
+ input [21 : 0] b;
+ output [21 : 0] s;
+
+ // synthesis translate_off
+
+ wire sig00000001;
+ wire sig00000002;
+ wire NLW_blk00000003_CARRYOUTF_UNCONNECTED;
+ wire NLW_blk00000003_CARRYOUT_UNCONNECTED;
+ wire \NLW_blk00000003_BCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<0>_UNCONNECTED ;
+ VCC blk00000001 (
+ .P(sig00000002)
+ );
+ GND blk00000002 (
+ .G(sig00000001)
+ );
+ DSP48A1 #(
+ .A0REG ( 0 ),
+ .A1REG ( 0 ),
+ .B0REG ( 0 ),
+ .B1REG ( 0 ),
+ .CARRYINREG ( 0 ),
+ .CARRYINSEL ( "OPMODE5" ),
+ .CREG ( 0 ),
+ .DREG ( 0 ),
+ .MREG ( 0 ),
+ .OPMODEREG ( 0 ),
+ .PREG ( 0 ),
+ .RSTTYPE ( "SYNC" ),
+ .CARRYOUTREG ( 0 ))
+ blk00000003 (
+ .CECARRYIN(sig00000001),
+ .RSTC(sig00000001),
+ .RSTCARRYIN(sig00000001),
+ .CED(sig00000001),
+ .RSTD(sig00000001),
+ .CEOPMODE(sig00000001),
+ .CEC(sig00000001),
+ .CARRYOUTF(NLW_blk00000003_CARRYOUTF_UNCONNECTED),
+ .RSTOPMODE(sig00000001),
+ .RSTM(sig00000001),
+ .CLK(sig00000001),
+ .RSTB(sig00000001),
+ .CEM(sig00000001),
+ .CEB(sig00000001),
+ .CARRYIN(sig00000001),
+ .CEP(sig00000001),
+ .CEA(sig00000001),
+ .CARRYOUT(NLW_blk00000003_CARRYOUT_UNCONNECTED),
+ .RSTA(sig00000001),
+ .RSTP(sig00000001),
+ .B({b[17], b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+ .BCOUT({\NLW_blk00000003_BCOUT<17>_UNCONNECTED , \NLW_blk00000003_BCOUT<16>_UNCONNECTED , \NLW_blk00000003_BCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<14>_UNCONNECTED , \NLW_blk00000003_BCOUT<13>_UNCONNECTED , \NLW_blk00000003_BCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<11>_UNCONNECTED , \NLW_blk00000003_BCOUT<10>_UNCONNECTED , \NLW_blk00000003_BCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<8>_UNCONNECTED , \NLW_blk00000003_BCOUT<7>_UNCONNECTED , \NLW_blk00000003_BCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<5>_UNCONNECTED , \NLW_blk00000003_BCOUT<4>_UNCONNECTED , \NLW_blk00000003_BCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<2>_UNCONNECTED , \NLW_blk00000003_BCOUT<1>_UNCONNECTED , \NLW_blk00000003_BCOUT<0>_UNCONNECTED }),
+ .PCIN({sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001}),
+ .C({a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[21],
+a[21], a[21], a[21], a[21], a[21], a[21], a[21], a[20], a[19], a[18], a[17], a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6],
+a[5], a[4], a[3], a[2], a[1], a[0]}),
+ .P({\NLW_blk00000003_P<47>_UNCONNECTED , \NLW_blk00000003_P<46>_UNCONNECTED , \NLW_blk00000003_P<45>_UNCONNECTED ,
+\NLW_blk00000003_P<44>_UNCONNECTED , \NLW_blk00000003_P<43>_UNCONNECTED , \NLW_blk00000003_P<42>_UNCONNECTED , \NLW_blk00000003_P<41>_UNCONNECTED ,
+\NLW_blk00000003_P<40>_UNCONNECTED , \NLW_blk00000003_P<39>_UNCONNECTED , \NLW_blk00000003_P<38>_UNCONNECTED , \NLW_blk00000003_P<37>_UNCONNECTED ,
+\NLW_blk00000003_P<36>_UNCONNECTED , \NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED ,
+\NLW_blk00000003_P<32>_UNCONNECTED , \NLW_blk00000003_P<31>_UNCONNECTED , \NLW_blk00000003_P<30>_UNCONNECTED , \NLW_blk00000003_P<29>_UNCONNECTED ,
+\NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED ,
+\NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , s[21], s[20], s[19], s[18], s[17],
+s[16], s[15], s[14], s[13], s[12], s[11], s[10], s[9], s[8], s[7], s[6], s[5], s[4], s[3], s[2], s[1], s[0]}),
+ .OPMODE({sig00000002, sig00000001, sig00000001, sig00000001, sig00000002, sig00000002, sig00000002, sig00000002}),
+ .D({b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21]}),
+ .PCOUT({\NLW_blk00000003_PCOUT<47>_UNCONNECTED , \NLW_blk00000003_PCOUT<46>_UNCONNECTED , \NLW_blk00000003_PCOUT<45>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<44>_UNCONNECTED , \NLW_blk00000003_PCOUT<43>_UNCONNECTED , \NLW_blk00000003_PCOUT<42>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<41>_UNCONNECTED , \NLW_blk00000003_PCOUT<40>_UNCONNECTED , \NLW_blk00000003_PCOUT<39>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<38>_UNCONNECTED , \NLW_blk00000003_PCOUT<37>_UNCONNECTED , \NLW_blk00000003_PCOUT<36>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<35>_UNCONNECTED , \NLW_blk00000003_PCOUT<34>_UNCONNECTED , \NLW_blk00000003_PCOUT<33>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<32>_UNCONNECTED , \NLW_blk00000003_PCOUT<31>_UNCONNECTED , \NLW_blk00000003_PCOUT<30>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<29>_UNCONNECTED , \NLW_blk00000003_PCOUT<28>_UNCONNECTED , \NLW_blk00000003_PCOUT<27>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<26>_UNCONNECTED , \NLW_blk00000003_PCOUT<25>_UNCONNECTED , \NLW_blk00000003_PCOUT<24>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<23>_UNCONNECTED , \NLW_blk00000003_PCOUT<22>_UNCONNECTED , \NLW_blk00000003_PCOUT<21>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<20>_UNCONNECTED , \NLW_blk00000003_PCOUT<19>_UNCONNECTED , \NLW_blk00000003_PCOUT<18>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<17>_UNCONNECTED , \NLW_blk00000003_PCOUT<16>_UNCONNECTED , \NLW_blk00000003_PCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<14>_UNCONNECTED , \NLW_blk00000003_PCOUT<13>_UNCONNECTED , \NLW_blk00000003_PCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<11>_UNCONNECTED , \NLW_blk00000003_PCOUT<10>_UNCONNECTED , \NLW_blk00000003_PCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<8>_UNCONNECTED , \NLW_blk00000003_PCOUT<7>_UNCONNECTED , \NLW_blk00000003_PCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<5>_UNCONNECTED , \NLW_blk00000003_PCOUT<4>_UNCONNECTED , \NLW_blk00000003_PCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<2>_UNCONNECTED , \NLW_blk00000003_PCOUT<1>_UNCONNECTED , \NLW_blk00000003_PCOUT<0>_UNCONNECTED }),
+ .A({b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[21], b[20], b[19], b[18]}),
+ .M({\NLW_blk00000003_M<35>_UNCONNECTED , \NLW_blk00000003_M<34>_UNCONNECTED , \NLW_blk00000003_M<33>_UNCONNECTED ,
+\NLW_blk00000003_M<32>_UNCONNECTED , \NLW_blk00000003_M<31>_UNCONNECTED , \NLW_blk00000003_M<30>_UNCONNECTED , \NLW_blk00000003_M<29>_UNCONNECTED ,
+\NLW_blk00000003_M<28>_UNCONNECTED , \NLW_blk00000003_M<27>_UNCONNECTED , \NLW_blk00000003_M<26>_UNCONNECTED , \NLW_blk00000003_M<25>_UNCONNECTED ,
+\NLW_blk00000003_M<24>_UNCONNECTED , \NLW_blk00000003_M<23>_UNCONNECTED , \NLW_blk00000003_M<22>_UNCONNECTED , \NLW_blk00000003_M<21>_UNCONNECTED ,
+\NLW_blk00000003_M<20>_UNCONNECTED , \NLW_blk00000003_M<19>_UNCONNECTED , \NLW_blk00000003_M<18>_UNCONNECTED , \NLW_blk00000003_M<17>_UNCONNECTED ,
+\NLW_blk00000003_M<16>_UNCONNECTED , \NLW_blk00000003_M<15>_UNCONNECTED , \NLW_blk00000003_M<14>_UNCONNECTED , \NLW_blk00000003_M<13>_UNCONNECTED ,
+\NLW_blk00000003_M<12>_UNCONNECTED , \NLW_blk00000003_M<11>_UNCONNECTED , \NLW_blk00000003_M<10>_UNCONNECTED , \NLW_blk00000003_M<9>_UNCONNECTED ,
+\NLW_blk00000003_M<8>_UNCONNECTED , \NLW_blk00000003_M<7>_UNCONNECTED , \NLW_blk00000003_M<6>_UNCONNECTED , \NLW_blk00000003_M<5>_UNCONNECTED ,
+\NLW_blk00000003_M<4>_UNCONNECTED , \NLW_blk00000003_M<3>_UNCONNECTED , \NLW_blk00000003_M<2>_UNCONNECTED , \NLW_blk00000003_M<1>_UNCONNECTED ,
+\NLW_blk00000003_M<0>_UNCONNECTED })
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
View
73 s22_sub.xco
@@ -0,0 +1,73 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.2
+# Date: Sat Dec 22 18:42:17 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:c_addsub:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0
+# END Select
+# BEGIN Parameters
+CSET a_type=Signed
+CSET a_width=22
+CSET add_mode=Subtract
+CSET ainit_value=0
+CSET b_constant=false
+CSET b_type=Signed
+CSET b_value=0000000000000000000000
+CSET b_width=22
+CSET borrow_sense=Active_Low
+CSET bypass=false
+CSET bypass_ce_priority=CE_Overrides_Bypass
+CSET bypass_sense=Active_High
+CSET c_in=false
+CSET c_out=false
+CSET ce=false
+CSET component_name=s22_sub
+CSET implementation=DSP48
+CSET latency=0
+CSET latency_configuration=Manual
+CSET out_width=22
+CSET sclr=false
+CSET sinit=false
+CSET sinit_value=0
+CSET sset=false
+CSET sync_ce_priority=Sync_Overrides_CE
+CSET sync_ctrl_priority=Reset_Overrides_Set
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-06-22T15:32:25Z
+# END Extra information
+GENERATE
+# CRC: e031245f
View
343 s26_add.v
@@ -0,0 +1,343 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: P.28xd
+// \ \ Application: netgen
+// / / Filename: s26_add.v
+// /___/ /\ Timestamp: Sat Dec 22 12:34:17 2012
+// \ \ / \
+// \___\/\___\
+//
+// Command : -w -sim -ofmt verilog /home/josh/got/kovan-fpga/tmp/_cg/s26_add.ngc /home/josh/got/kovan-fpga/tmp/_cg/s26_add.v
+// Device : 6slx9csg324-2
+// Input file : /home/josh/got/kovan-fpga/tmp/_cg/s26_add.ngc
+// Output file : /home/josh/got/kovan-fpga/tmp/_cg/s26_add.v
+// # of Modules : 1
+// Design Name : s26_add
+// Xilinx : /opt/Xilinx/14.2/ISE_DS/ISE/
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module s26_add (
+a, b, s
+)/* synthesis syn_black_box syn_noprune=1 */;
+ input [25 : 0] a;
+ input [25 : 0] b;
+ output [25 : 0] s;
+
+ // synthesis translate_off
+
+ wire sig00000001;
+ wire sig00000002;
+ wire NLW_blk00000003_CARRYOUTF_UNCONNECTED;
+ wire NLW_blk00000003_CARRYOUT_UNCONNECTED;
+ wire \NLW_blk00000003_BCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<0>_UNCONNECTED ;
+ VCC blk00000001 (
+ .P(sig00000002)
+ );
+ GND blk00000002 (
+ .G(sig00000001)
+ );
+ DSP48A1 #(
+ .A0REG ( 0 ),
+ .A1REG ( 0 ),
+ .B0REG ( 0 ),
+ .B1REG ( 0 ),
+ .CARRYINREG ( 0 ),
+ .CARRYINSEL ( "OPMODE5" ),
+ .CREG ( 0 ),
+ .DREG ( 0 ),
+ .MREG ( 0 ),
+ .OPMODEREG ( 0 ),
+ .PREG ( 0 ),
+ .RSTTYPE ( "SYNC" ),
+ .CARRYOUTREG ( 0 ))
+ blk00000003 (
+ .CECARRYIN(sig00000001),
+ .RSTC(sig00000001),
+ .RSTCARRYIN(sig00000001),
+ .CED(sig00000001),
+ .RSTD(sig00000001),
+ .CEOPMODE(sig00000001),
+ .CEC(sig00000001),
+ .CARRYOUTF(NLW_blk00000003_CARRYOUTF_UNCONNECTED),
+ .RSTOPMODE(sig00000001),
+ .RSTM(sig00000001),
+ .CLK(sig00000001),
+ .RSTB(sig00000001),
+ .CEM(sig00000001),
+ .CEB(sig00000001),
+ .CARRYIN(sig00000001),
+ .CEP(sig00000001),
+ .CEA(sig00000001),
+ .CARRYOUT(NLW_blk00000003_CARRYOUT_UNCONNECTED),
+ .RSTA(sig00000001),
+ .RSTP(sig00000001),
+ .B({b[17], b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+ .BCOUT({\NLW_blk00000003_BCOUT<17>_UNCONNECTED , \NLW_blk00000003_BCOUT<16>_UNCONNECTED , \NLW_blk00000003_BCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<14>_UNCONNECTED , \NLW_blk00000003_BCOUT<13>_UNCONNECTED , \NLW_blk00000003_BCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<11>_UNCONNECTED , \NLW_blk00000003_BCOUT<10>_UNCONNECTED , \NLW_blk00000003_BCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<8>_UNCONNECTED , \NLW_blk00000003_BCOUT<7>_UNCONNECTED , \NLW_blk00000003_BCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<5>_UNCONNECTED , \NLW_blk00000003_BCOUT<4>_UNCONNECTED , \NLW_blk00000003_BCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<2>_UNCONNECTED , \NLW_blk00000003_BCOUT<1>_UNCONNECTED , \NLW_blk00000003_BCOUT<0>_UNCONNECTED }),
+ .PCIN({sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001}),
+ .C({a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25],
+a[25], a[25], a[25], a[24], a[23], a[22], a[21], a[20], a[19], a[18], a[17], a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6],
+a[5], a[4], a[3], a[2], a[1], a[0]}),
+ .P({\NLW_blk00000003_P<47>_UNCONNECTED , \NLW_blk00000003_P<46>_UNCONNECTED , \NLW_blk00000003_P<45>_UNCONNECTED ,
+\NLW_blk00000003_P<44>_UNCONNECTED , \NLW_blk00000003_P<43>_UNCONNECTED , \NLW_blk00000003_P<42>_UNCONNECTED , \NLW_blk00000003_P<41>_UNCONNECTED ,
+\NLW_blk00000003_P<40>_UNCONNECTED , \NLW_blk00000003_P<39>_UNCONNECTED , \NLW_blk00000003_P<38>_UNCONNECTED , \NLW_blk00000003_P<37>_UNCONNECTED ,
+\NLW_blk00000003_P<36>_UNCONNECTED , \NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED ,
+\NLW_blk00000003_P<32>_UNCONNECTED , \NLW_blk00000003_P<31>_UNCONNECTED , \NLW_blk00000003_P<30>_UNCONNECTED , \NLW_blk00000003_P<29>_UNCONNECTED ,
+\NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , s[25], s[24], s[23], s[22], s[21],
+s[20], s[19], s[18], s[17], s[16], s[15], s[14], s[13], s[12], s[11], s[10], s[9], s[8], s[7], s[6], s[5], s[4], s[3], s[2], s[1], s[0]}),
+ .OPMODE({sig00000001, sig00000001, sig00000001, sig00000001, sig00000002, sig00000002, sig00000002, sig00000002}),
+ .D({b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25]}),
+ .PCOUT({\NLW_blk00000003_PCOUT<47>_UNCONNECTED , \NLW_blk00000003_PCOUT<46>_UNCONNECTED , \NLW_blk00000003_PCOUT<45>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<44>_UNCONNECTED , \NLW_blk00000003_PCOUT<43>_UNCONNECTED , \NLW_blk00000003_PCOUT<42>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<41>_UNCONNECTED , \NLW_blk00000003_PCOUT<40>_UNCONNECTED , \NLW_blk00000003_PCOUT<39>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<38>_UNCONNECTED , \NLW_blk00000003_PCOUT<37>_UNCONNECTED , \NLW_blk00000003_PCOUT<36>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<35>_UNCONNECTED , \NLW_blk00000003_PCOUT<34>_UNCONNECTED , \NLW_blk00000003_PCOUT<33>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<32>_UNCONNECTED , \NLW_blk00000003_PCOUT<31>_UNCONNECTED , \NLW_blk00000003_PCOUT<30>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<29>_UNCONNECTED , \NLW_blk00000003_PCOUT<28>_UNCONNECTED , \NLW_blk00000003_PCOUT<27>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<26>_UNCONNECTED , \NLW_blk00000003_PCOUT<25>_UNCONNECTED , \NLW_blk00000003_PCOUT<24>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<23>_UNCONNECTED , \NLW_blk00000003_PCOUT<22>_UNCONNECTED , \NLW_blk00000003_PCOUT<21>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<20>_UNCONNECTED , \NLW_blk00000003_PCOUT<19>_UNCONNECTED , \NLW_blk00000003_PCOUT<18>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<17>_UNCONNECTED , \NLW_blk00000003_PCOUT<16>_UNCONNECTED , \NLW_blk00000003_PCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<14>_UNCONNECTED , \NLW_blk00000003_PCOUT<13>_UNCONNECTED , \NLW_blk00000003_PCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<11>_UNCONNECTED , \NLW_blk00000003_PCOUT<10>_UNCONNECTED , \NLW_blk00000003_PCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<8>_UNCONNECTED , \NLW_blk00000003_PCOUT<7>_UNCONNECTED , \NLW_blk00000003_PCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<5>_UNCONNECTED , \NLW_blk00000003_PCOUT<4>_UNCONNECTED , \NLW_blk00000003_PCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<2>_UNCONNECTED , \NLW_blk00000003_PCOUT<1>_UNCONNECTED , \NLW_blk00000003_PCOUT<0>_UNCONNECTED }),
+ .A({b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[24], b[23], b[22], b[21], b[20], b[19], b[18]}),
+ .M({\NLW_blk00000003_M<35>_UNCONNECTED , \NLW_blk00000003_M<34>_UNCONNECTED , \NLW_blk00000003_M<33>_UNCONNECTED ,
+\NLW_blk00000003_M<32>_UNCONNECTED , \NLW_blk00000003_M<31>_UNCONNECTED , \NLW_blk00000003_M<30>_UNCONNECTED , \NLW_blk00000003_M<29>_UNCONNECTED ,
+\NLW_blk00000003_M<28>_UNCONNECTED , \NLW_blk00000003_M<27>_UNCONNECTED , \NLW_blk00000003_M<26>_UNCONNECTED , \NLW_blk00000003_M<25>_UNCONNECTED ,
+\NLW_blk00000003_M<24>_UNCONNECTED , \NLW_blk00000003_M<23>_UNCONNECTED , \NLW_blk00000003_M<22>_UNCONNECTED , \NLW_blk00000003_M<21>_UNCONNECTED ,
+\NLW_blk00000003_M<20>_UNCONNECTED , \NLW_blk00000003_M<19>_UNCONNECTED , \NLW_blk00000003_M<18>_UNCONNECTED , \NLW_blk00000003_M<17>_UNCONNECTED ,
+\NLW_blk00000003_M<16>_UNCONNECTED , \NLW_blk00000003_M<15>_UNCONNECTED , \NLW_blk00000003_M<14>_UNCONNECTED , \NLW_blk00000003_M<13>_UNCONNECTED ,
+\NLW_blk00000003_M<12>_UNCONNECTED , \NLW_blk00000003_M<11>_UNCONNECTED , \NLW_blk00000003_M<10>_UNCONNECTED , \NLW_blk00000003_M<9>_UNCONNECTED ,
+\NLW_blk00000003_M<8>_UNCONNECTED , \NLW_blk00000003_M<7>_UNCONNECTED , \NLW_blk00000003_M<6>_UNCONNECTED , \NLW_blk00000003_M<5>_UNCONNECTED ,
+\NLW_blk00000003_M<4>_UNCONNECTED , \NLW_blk00000003_M<3>_UNCONNECTED , \NLW_blk00000003_M<2>_UNCONNECTED , \NLW_blk00000003_M<1>_UNCONNECTED ,
+\NLW_blk00000003_M<0>_UNCONNECTED })
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
View
73 s26_add.xco
@@ -0,0 +1,73 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.2
+# Date: Sat Dec 22 18:33:45 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:c_addsub:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0
+# END Select
+# BEGIN Parameters
+CSET a_type=Signed
+CSET a_width=26
+CSET add_mode=Add
+CSET ainit_value=0
+CSET b_constant=false
+CSET b_type=Signed
+CSET b_value=00000000000000000000000000
+CSET b_width=26
+CSET borrow_sense=Active_Low
+CSET bypass=false
+CSET bypass_ce_priority=CE_Overrides_Bypass
+CSET bypass_sense=Active_High
+CSET c_in=false
+CSET c_out=false
+CSET ce=false
+CSET component_name=s26_add
+CSET implementation=DSP48
+CSET latency=0
+CSET latency_configuration=Manual
+CSET out_width=26
+CSET sclr=false
+CSET sinit=false
+CSET sinit_value=0
+CSET sset=false
+CSET sync_ce_priority=Sync_Overrides_CE
+CSET sync_ctrl_priority=Reset_Overrides_Set
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-06-22T15:32:25Z
+# END Extra information
+GENERATE
+# CRC: 27ed27ca
View
343 s26_sub.v
@@ -0,0 +1,343 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: P.28xd
+// \ \ Application: netgen
+// / / Filename: s26_sub.v
+// /___/ /\ Timestamp: Sat Dec 22 12:37:15 2012
+// \ \ / \
+// \___\/\___\
+//
+// Command : -w -sim -ofmt verilog /home/josh/got/kovan-fpga/tmp/_cg/s26_sub.ngc /home/josh/got/kovan-fpga/tmp/_cg/s26_sub.v
+// Device : 6slx9csg324-2
+// Input file : /home/josh/got/kovan-fpga/tmp/_cg/s26_sub.ngc
+// Output file : /home/josh/got/kovan-fpga/tmp/_cg/s26_sub.v
+// # of Modules : 1
+// Design Name : s26_sub
+// Xilinx : /opt/Xilinx/14.2/ISE_DS/ISE/
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module s26_sub (
+a, b, s
+)/* synthesis syn_black_box syn_noprune=1 */;
+ input [25 : 0] a;
+ input [25 : 0] b;
+ output [25 : 0] s;
+
+ // synthesis translate_off
+
+ wire sig00000001;
+ wire sig00000002;
+ wire NLW_blk00000003_CARRYOUTF_UNCONNECTED;
+ wire NLW_blk00000003_CARRYOUT_UNCONNECTED;
+ wire \NLW_blk00000003_BCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<0>_UNCONNECTED ;
+ VCC blk00000001 (
+ .P(sig00000002)
+ );
+ GND blk00000002 (
+ .G(sig00000001)
+ );
+ DSP48A1 #(
+ .A0REG ( 0 ),
+ .A1REG ( 0 ),
+ .B0REG ( 0 ),
+ .B1REG ( 0 ),
+ .CARRYINREG ( 0 ),
+ .CARRYINSEL ( "OPMODE5" ),
+ .CREG ( 0 ),
+ .DREG ( 0 ),
+ .MREG ( 0 ),
+ .OPMODEREG ( 0 ),
+ .PREG ( 0 ),
+ .RSTTYPE ( "SYNC" ),
+ .CARRYOUTREG ( 0 ))
+ blk00000003 (
+ .CECARRYIN(sig00000001),
+ .RSTC(sig00000001),
+ .RSTCARRYIN(sig00000001),
+ .CED(sig00000001),
+ .RSTD(sig00000001),
+ .CEOPMODE(sig00000001),
+ .CEC(sig00000001),
+ .CARRYOUTF(NLW_blk00000003_CARRYOUTF_UNCONNECTED),
+ .RSTOPMODE(sig00000001),
+ .RSTM(sig00000001),
+ .CLK(sig00000001),
+ .RSTB(sig00000001),
+ .CEM(sig00000001),
+ .CEB(sig00000001),
+ .CARRYIN(sig00000001),
+ .CEP(sig00000001),
+ .CEA(sig00000001),
+ .CARRYOUT(NLW_blk00000003_CARRYOUT_UNCONNECTED),
+ .RSTA(sig00000001),
+ .RSTP(sig00000001),
+ .B({b[17], b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+ .BCOUT({\NLW_blk00000003_BCOUT<17>_UNCONNECTED , \NLW_blk00000003_BCOUT<16>_UNCONNECTED , \NLW_blk00000003_BCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<14>_UNCONNECTED , \NLW_blk00000003_BCOUT<13>_UNCONNECTED , \NLW_blk00000003_BCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<11>_UNCONNECTED , \NLW_blk00000003_BCOUT<10>_UNCONNECTED , \NLW_blk00000003_BCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<8>_UNCONNECTED , \NLW_blk00000003_BCOUT<7>_UNCONNECTED , \NLW_blk00000003_BCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<5>_UNCONNECTED , \NLW_blk00000003_BCOUT<4>_UNCONNECTED , \NLW_blk00000003_BCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<2>_UNCONNECTED , \NLW_blk00000003_BCOUT<1>_UNCONNECTED , \NLW_blk00000003_BCOUT<0>_UNCONNECTED }),
+ .PCIN({sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001}),
+ .C({a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25], a[25],
+a[25], a[25], a[25], a[24], a[23], a[22], a[21], a[20], a[19], a[18], a[17], a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6],
+a[5], a[4], a[3], a[2], a[1], a[0]}),
+ .P({\NLW_blk00000003_P<47>_UNCONNECTED , \NLW_blk00000003_P<46>_UNCONNECTED , \NLW_blk00000003_P<45>_UNCONNECTED ,
+\NLW_blk00000003_P<44>_UNCONNECTED , \NLW_blk00000003_P<43>_UNCONNECTED , \NLW_blk00000003_P<42>_UNCONNECTED , \NLW_blk00000003_P<41>_UNCONNECTED ,
+\NLW_blk00000003_P<40>_UNCONNECTED , \NLW_blk00000003_P<39>_UNCONNECTED , \NLW_blk00000003_P<38>_UNCONNECTED , \NLW_blk00000003_P<37>_UNCONNECTED ,
+\NLW_blk00000003_P<36>_UNCONNECTED , \NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED ,
+\NLW_blk00000003_P<32>_UNCONNECTED , \NLW_blk00000003_P<31>_UNCONNECTED , \NLW_blk00000003_P<30>_UNCONNECTED , \NLW_blk00000003_P<29>_UNCONNECTED ,
+\NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , s[25], s[24], s[23], s[22], s[21],
+s[20], s[19], s[18], s[17], s[16], s[15], s[14], s[13], s[12], s[11], s[10], s[9], s[8], s[7], s[6], s[5], s[4], s[3], s[2], s[1], s[0]}),
+ .OPMODE({sig00000002, sig00000001, sig00000001, sig00000001, sig00000002, sig00000002, sig00000002, sig00000002}),
+ .D({b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25]}),
+ .PCOUT({\NLW_blk00000003_PCOUT<47>_UNCONNECTED , \NLW_blk00000003_PCOUT<46>_UNCONNECTED , \NLW_blk00000003_PCOUT<45>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<44>_UNCONNECTED , \NLW_blk00000003_PCOUT<43>_UNCONNECTED , \NLW_blk00000003_PCOUT<42>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<41>_UNCONNECTED , \NLW_blk00000003_PCOUT<40>_UNCONNECTED , \NLW_blk00000003_PCOUT<39>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<38>_UNCONNECTED , \NLW_blk00000003_PCOUT<37>_UNCONNECTED , \NLW_blk00000003_PCOUT<36>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<35>_UNCONNECTED , \NLW_blk00000003_PCOUT<34>_UNCONNECTED , \NLW_blk00000003_PCOUT<33>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<32>_UNCONNECTED , \NLW_blk00000003_PCOUT<31>_UNCONNECTED , \NLW_blk00000003_PCOUT<30>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<29>_UNCONNECTED , \NLW_blk00000003_PCOUT<28>_UNCONNECTED , \NLW_blk00000003_PCOUT<27>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<26>_UNCONNECTED , \NLW_blk00000003_PCOUT<25>_UNCONNECTED , \NLW_blk00000003_PCOUT<24>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<23>_UNCONNECTED , \NLW_blk00000003_PCOUT<22>_UNCONNECTED , \NLW_blk00000003_PCOUT<21>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<20>_UNCONNECTED , \NLW_blk00000003_PCOUT<19>_UNCONNECTED , \NLW_blk00000003_PCOUT<18>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<17>_UNCONNECTED , \NLW_blk00000003_PCOUT<16>_UNCONNECTED , \NLW_blk00000003_PCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<14>_UNCONNECTED , \NLW_blk00000003_PCOUT<13>_UNCONNECTED , \NLW_blk00000003_PCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<11>_UNCONNECTED , \NLW_blk00000003_PCOUT<10>_UNCONNECTED , \NLW_blk00000003_PCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<8>_UNCONNECTED , \NLW_blk00000003_PCOUT<7>_UNCONNECTED , \NLW_blk00000003_PCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<5>_UNCONNECTED , \NLW_blk00000003_PCOUT<4>_UNCONNECTED , \NLW_blk00000003_PCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<2>_UNCONNECTED , \NLW_blk00000003_PCOUT<1>_UNCONNECTED , \NLW_blk00000003_PCOUT<0>_UNCONNECTED }),
+ .A({b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[25], b[24], b[23], b[22], b[21], b[20], b[19], b[18]}),
+ .M({\NLW_blk00000003_M<35>_UNCONNECTED , \NLW_blk00000003_M<34>_UNCONNECTED , \NLW_blk00000003_M<33>_UNCONNECTED ,
+\NLW_blk00000003_M<32>_UNCONNECTED , \NLW_blk00000003_M<31>_UNCONNECTED , \NLW_blk00000003_M<30>_UNCONNECTED , \NLW_blk00000003_M<29>_UNCONNECTED ,
+\NLW_blk00000003_M<28>_UNCONNECTED , \NLW_blk00000003_M<27>_UNCONNECTED , \NLW_blk00000003_M<26>_UNCONNECTED , \NLW_blk00000003_M<25>_UNCONNECTED ,
+\NLW_blk00000003_M<24>_UNCONNECTED , \NLW_blk00000003_M<23>_UNCONNECTED , \NLW_blk00000003_M<22>_UNCONNECTED , \NLW_blk00000003_M<21>_UNCONNECTED ,
+\NLW_blk00000003_M<20>_UNCONNECTED , \NLW_blk00000003_M<19>_UNCONNECTED , \NLW_blk00000003_M<18>_UNCONNECTED , \NLW_blk00000003_M<17>_UNCONNECTED ,
+\NLW_blk00000003_M<16>_UNCONNECTED , \NLW_blk00000003_M<15>_UNCONNECTED , \NLW_blk00000003_M<14>_UNCONNECTED , \NLW_blk00000003_M<13>_UNCONNECTED ,
+\NLW_blk00000003_M<12>_UNCONNECTED , \NLW_blk00000003_M<11>_UNCONNECTED , \NLW_blk00000003_M<10>_UNCONNECTED , \NLW_blk00000003_M<9>_UNCONNECTED ,
+\NLW_blk00000003_M<8>_UNCONNECTED , \NLW_blk00000003_M<7>_UNCONNECTED , \NLW_blk00000003_M<6>_UNCONNECTED , \NLW_blk00000003_M<5>_UNCONNECTED ,
+\NLW_blk00000003_M<4>_UNCONNECTED , \NLW_blk00000003_M<3>_UNCONNECTED , \NLW_blk00000003_M<2>_UNCONNECTED , \NLW_blk00000003_M<1>_UNCONNECTED ,
+\NLW_blk00000003_M<0>_UNCONNECTED })
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
View
73 s26_sub.xco
@@ -0,0 +1,73 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.2
+# Date: Sat Dec 22 18:36:43 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:c_addsub:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0
+# END Select
+# BEGIN Parameters
+CSET a_type=Signed
+CSET a_width=26
+CSET add_mode=Subtract
+CSET ainit_value=0
+CSET b_constant=false
+CSET b_type=Signed
+CSET b_value=00000000000000000000000000
+CSET b_width=26
+CSET borrow_sense=Active_Low
+CSET bypass=false
+CSET bypass_ce_priority=CE_Overrides_Bypass
+CSET bypass_sense=Active_High
+CSET c_in=false
+CSET c_out=false
+CSET ce=false
+CSET component_name=s26_sub
+CSET implementation=DSP48
+CSET latency=0
+CSET latency_configuration=Manual
+CSET out_width=26
+CSET sclr=false
+CSET sinit=false
+CSET sinit_value=0
+CSET sset=false
+CSET sync_ce_priority=Sync_Overrides_CE
+CSET sync_ctrl_priority=Reset_Overrides_Set
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-06-22T15:32:25Z
+# END Extra information
+GENERATE
+# CRC: 974b44f5

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