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using 32bit backemf registers now

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commit 77071768e9c31d0520a44fae6e9207bf65f0a1aa 1 parent ec672a7
@jsoutherland jsoutherland authored
View
48 bemf_update.v
@@ -5,11 +5,11 @@ module bemf_update(
input [9:0] bemf_adc_l,
input [1:0] mot_sel_in,
input in_valid,
- input [19:0] bemf_in,
- input [19:0] bemf_calib_in,
+ input [35:0] bemf_in,
+ input [35:0] bemf_calib_in,
input clk,
- output [19:0] bemf_out,
- output [19:0] bemf_vel_out,
+ output [35:0] bemf_out,
+ //output [35:0] bemf_vel_out,
output [1:0] mot_sel_out,
output out_valid
);
@@ -18,19 +18,19 @@ module bemf_update(
// subtract the high and low side of the motor
reg [9:0] bemf_sub_in_a_r = 10'd0;
reg [9:0] bemf_sub_in_b_r = 10'd0;
- wire [19:0] bemf_sub_out;
- s20_sub bemf_sub(
- .a({10'd0, bemf_sub_in_a_r}),
- .b({10'd0, bemf_sub_in_b_r}),
+ wire [35:0] bemf_sub_out;
+ s36_sub bemf_sub(
+ .a({26'd0, bemf_sub_in_a_r}),
+ .b({26'd0, bemf_sub_in_b_r}),
.s(bemf_sub_out)
);
// adjust by the calibration amount
- reg [19:0] calib_sub_in_a_r = 20'd0;
- reg [19:0] calib_sub_in_b_r = 20'd0;
- wire [19:0] calib_sub_out;
- s20_sub calib_sub(
+ reg [35:0] calib_sub_in_a_r = 36'd0;
+ reg [35:0] calib_sub_in_b_r = 36'd0;
+ wire [35:0] calib_sub_out;
+ s36_sub calib_sub(
.a(calib_sub_in_a_r),
.b(calib_sub_in_b_r),
.s(calib_sub_out)
@@ -38,10 +38,10 @@ module bemf_update(
// integrate the calibrated back emf readings
- reg [19:0] bemf_integr_in_a_r = 20'd0;
- reg [19:0] bemf_integr_in_b_r = 20'd0;
- wire [19:0] bemf_integr_out;
- s20_add bemf_integr(
+ reg [35:0] bemf_integr_in_a_r = 36'd0;
+ reg [35:0] bemf_integr_in_b_r = 36'd0;
+ wire [35:0] bemf_integr_out;
+ s36_add bemf_integr(
.a(bemf_integr_in_a_r),
.b(bemf_integr_in_b_r),
.s(bemf_integr_out)
@@ -58,13 +58,13 @@ module bemf_update(
reg in_valid_2 = 1'd0;
reg in_valid_3 = 1'd0;
- reg [19:0] bemf_out_r = 20'd0;
+ reg [35:0] bemf_out_r = 36'd0;
- reg [19:0] bemf_in_0 = 20'd0;
- reg [19:0] bemf_in_1 = 20'd0;
+ reg [35:0] bemf_in_0 = 36'd0;
+ reg [35:0] bemf_in_1 = 36'd0;
- reg [19:0] vel_out_3 = 20'd0;
+ reg [35:0] vel_out_3 = 36'd0;
always @ (posedge clk) begin
@@ -88,10 +88,10 @@ module bemf_update(
// pipeline stage 2: subtracted the calibration info
// deadbanding
- if (calib_sub_out[19] == 1'b1)
- bemf_integr_in_a_r <= (~calib_sub_out > 16'd21) ? calib_sub_out : 20'd0; //negative
+ if (calib_sub_out[35] == 1'b1)
+ bemf_integr_in_a_r <= (~calib_sub_out > 36'd21) ? calib_sub_out : 36'd0; //negative
else
- bemf_integr_in_a_r <= (calib_sub_out > 15'd20) ? calib_sub_out : 20'd0; // positive
+ bemf_integr_in_a_r <= (calib_sub_out > 36'd20) ? calib_sub_out : 36'd0; // positive
//bemf_integr_in_a_r <= calib_sub_out;
bemf_integr_in_b_r <= bemf_in_1;
@@ -111,6 +111,6 @@ module bemf_update(
assign bemf_out = bemf_out_r;
assign out_valid = in_valid_3;
assign mot_sel_out = mot_sel_in_3;
- assign bemf_vel_out = vel_out_3;
+ //assign bemf_vel_out = vel_out_3;
endmodule
View
BIN  kovan.bit
Binary file not shown
View
78 kovan.v
@@ -282,32 +282,32 @@ module kovan (
reg [9:0] adc_15_new;
reg [9:0] adc_16_new;
- wire [19:0] bemf_0;
- wire [19:0] bemf_1;
- wire [19:0] bemf_2;
- wire [19:0] bemf_3;
+ wire [35:0] bemf_0;
+ wire [35:0] bemf_1;
+ wire [35:0] bemf_2;
+ wire [35:0] bemf_3;
- reg [19:0] bemf_0_r;
- reg [19:0] bemf_1_r;
- reg [19:0] bemf_2_r;
- reg [19:0] bemf_3_r;
+ reg [35:0] bemf_0_r;
+ reg [35:0] bemf_1_r;
+ reg [35:0] bemf_2_r;
+ reg [35:0] bemf_3_r;
- reg [19:0] bemf_0_r_208M = 20'd0;
- reg [19:0] bemf_1_r_208M = 20'd0;
- reg [19:0] bemf_2_r_208M = 20'd0;
- reg [19:0] bemf_3_r_208M = 20'd0;
+ reg [35:0] bemf_0_r_208M = 36'd0;
+ reg [35:0] bemf_1_r_208M = 36'd0;
+ reg [35:0] bemf_2_r_208M = 36'd0;
+ reg [35:0] bemf_3_r_208M = 36'd0;
- reg [19:0] bemf_0_calib = 20'd0;
- reg [19:0] bemf_1_calib = 20'd0;
- reg [19:0] bemf_2_calib = 20'd0;
- reg [19:0] bemf_3_calib = 20'd0;
+ reg [35:0] bemf_0_calib = 36'd0;
+ reg [35:0] bemf_1_calib = 36'd0;
+ reg [35:0] bemf_2_calib = 36'd0;
+ reg [35:0] bemf_3_calib = 36'd0;
- reg [15:0] mot_duty0_old = 16'd0;
- reg [15:0] mot_duty1_old = 16'd0;
- reg [15:0] mot_duty2_old = 16'd0;
- reg [15:0] mot_duty3_old = 16'd0;
+ reg [35:0] mot_duty0_old = 36'd0;
+ reg [35:0] mot_duty1_old = 36'd0;
+ reg [35:0] mot_duty2_old = 36'd0;
+ reg [35:0] mot_duty3_old = 36'd0;
reg [23:8] servo_pwm0_old = 16'd0;
reg [23:8] servo_pwm1_old = 16'd0;
@@ -452,23 +452,23 @@ module kovan (
assign servo_pwm_period[23:0] = 24'h03F7A0;
-
- wire [19:0] bemf_vel_out;
- reg [19:0] vel_mot_0 = 20'd0;
- reg [19:0] vel_mot_1 = 20'd0;
- reg [19:0] vel_mot_2 = 20'd0;
- reg [19:0] vel_mot_3 = 20'd0;
-
+/*
+ wire [35:0] bemf_vel_out;
+ reg [35:0] vel_mot_0 = 20'd0;
+ reg [35:0] vel_mot_1 = 20'd0;
+ reg [35:0] vel_mot_2 = 20'd0;
+ reg [35:0] vel_mot_3 = 20'd0;
+*/
reg [9:0] bemf_adc_h = 10'd0;
reg [9:0] bemf_adc_l = 10'd0;
reg [1:0] bemf_mot_sel_in = 2'd0;
reg bemf_in_valid = 1'd0;
- reg [19:0] bemf_in = 20'd0;
- reg [19:0] bemf_calib_in = 20'd0;
+ reg [35:0] bemf_in = 36'd0;
+ reg [35:0] bemf_calib_in = 36'd0;
wire [1:0] bemf_mot_sel_out;
wire bemf_out_valid;
- wire [19:0] bemf_out;
+ wire [35:0] bemf_out;
reg [15:0] bemf_counter = 16'd0; // can count for up to ~20mS
reg [2:0] bemf_state = 3'd0;
@@ -480,19 +480,19 @@ module kovan (
case(bemf_mot_sel_out)
2'd0: begin
bemf_0_r <= bemf_out;
- vel_mot_0 <= bemf_vel_out;
+ //vel_mot_0 <= bemf_vel_out;
end
2'd1: begin
bemf_1_r <= bemf_out;
- vel_mot_1 <= bemf_vel_out;
+ //vel_mot_1 <= bemf_vel_out;
end
2'd2: begin
bemf_2_r <= bemf_out;
- vel_mot_2 <= bemf_vel_out;
+ //vel_mot_2 <= bemf_vel_out;
end
2'd3: begin
bemf_3_r <= bemf_out;
- vel_mot_3 <= bemf_vel_out;
+ //vel_mot_3 <= bemf_vel_out;
end
endcase
end
@@ -608,7 +608,7 @@ module kovan (
.bemf_calib_in(bemf_calib_in),
.clk(clk3p2M),
.bemf_out(bemf_out),
- .bemf_vel_out(bemf_vel_out),
+ //.bemf_vel_out(bemf_vel_out),
.mot_sel_out(bemf_mot_sel_out),
.out_valid(bemf_out_valid)
);
@@ -644,10 +644,10 @@ module kovan (
.adc_15_in(adc_15_old),
.adc_16_in(adc_16_old),
.charge_acp_in(CHG_ACP),
- .bemf_0(bemf_0_r_208M[19:4]),
- .bemf_1(bemf_1_r_208M[19:4]),
- .bemf_2(bemf_2_r_208M[19:4]),
- .bemf_3(bemf_3_r_208M[19:4]),
+ .bemf_0(bemf_0_r_208M[35:4]),
+ .bemf_1(bemf_1_r_208M[35:4]),
+ .bemf_2(bemf_2_r_208M[35:4]),
+ .bemf_3(bemf_3_r_208M[35:4]),
.servo_pwm0_high(servo_pwm0_old),
.servo_pwm1_high(servo_pwm1_old),
.servo_pwm2_high(servo_pwm2_old),
View
331 s36_add.v
@@ -0,0 +1,331 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: P.28xd
+// \ \ Application: netgen
+// / / Filename: s36_add.v
+// /___/ /\ Timestamp: Mon Dec 31 12:01:02 2012
+// \ \ / \
+// \___\/\___\
+//
+// Command : -w -sim -ofmt verilog /home/josh/got/kovan-fpga/tmp/_cg/s36_add.ngc /home/josh/got/kovan-fpga/tmp/_cg/s36_add.v
+// Device : 6slx9csg324-2
+// Input file : /home/josh/got/kovan-fpga/tmp/_cg/s36_add.ngc
+// Output file : /home/josh/got/kovan-fpga/tmp/_cg/s36_add.v
+// # of Modules : 1
+// Design Name : s36_add
+// Xilinx : /opt/Xilinx/14.2/ISE_DS/ISE/
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module s36_add (
+a, b, s
+)/* synthesis syn_black_box syn_noprune=1 */;
+ input [35 : 0] a;
+ input [35 : 0] b;
+ output [35 : 0] s;
+
+ // synthesis translate_off
+
+ wire sig00000001;
+ wire sig00000002;
+ wire NLW_blk00000003_CARRYOUTF_UNCONNECTED;
+ wire NLW_blk00000003_CARRYOUT_UNCONNECTED;
+ wire \NLW_blk00000003_BCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<0>_UNCONNECTED ;
+ VCC blk00000001 (
+ .P(sig00000002)
+ );
+ GND blk00000002 (
+ .G(sig00000001)
+ );
+ DSP48A1 #(
+ .A0REG ( 0 ),
+ .A1REG ( 0 ),
+ .B0REG ( 0 ),
+ .B1REG ( 0 ),
+ .CARRYINREG ( 0 ),
+ .CARRYINSEL ( "OPMODE5" ),
+ .CREG ( 0 ),
+ .DREG ( 0 ),
+ .MREG ( 0 ),
+ .OPMODEREG ( 0 ),
+ .PREG ( 0 ),
+ .RSTTYPE ( "SYNC" ),
+ .CARRYOUTREG ( 0 ))
+ blk00000003 (
+ .CECARRYIN(sig00000001),
+ .RSTC(sig00000001),
+ .RSTCARRYIN(sig00000001),
+ .CED(sig00000001),
+ .RSTD(sig00000001),
+ .CEOPMODE(sig00000001),
+ .CEC(sig00000001),
+ .CARRYOUTF(NLW_blk00000003_CARRYOUTF_UNCONNECTED),
+ .RSTOPMODE(sig00000001),
+ .RSTM(sig00000001),
+ .CLK(sig00000001),
+ .RSTB(sig00000001),
+ .CEM(sig00000001),
+ .CEB(sig00000001),
+ .CARRYIN(sig00000001),
+ .CEP(sig00000001),
+ .CEA(sig00000001),
+ .CARRYOUT(NLW_blk00000003_CARRYOUT_UNCONNECTED),
+ .RSTA(sig00000001),
+ .RSTP(sig00000001),
+ .B({b[17], b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+ .BCOUT({\NLW_blk00000003_BCOUT<17>_UNCONNECTED , \NLW_blk00000003_BCOUT<16>_UNCONNECTED , \NLW_blk00000003_BCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<14>_UNCONNECTED , \NLW_blk00000003_BCOUT<13>_UNCONNECTED , \NLW_blk00000003_BCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<11>_UNCONNECTED , \NLW_blk00000003_BCOUT<10>_UNCONNECTED , \NLW_blk00000003_BCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<8>_UNCONNECTED , \NLW_blk00000003_BCOUT<7>_UNCONNECTED , \NLW_blk00000003_BCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<5>_UNCONNECTED , \NLW_blk00000003_BCOUT<4>_UNCONNECTED , \NLW_blk00000003_BCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<2>_UNCONNECTED , \NLW_blk00000003_BCOUT<1>_UNCONNECTED , \NLW_blk00000003_BCOUT<0>_UNCONNECTED }),
+ .PCIN({sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001}),
+ .C({a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[34], a[33], a[32], a[31], a[30], a[29], a[28],
+a[27], a[26], a[25], a[24], a[23], a[22], a[21], a[20], a[19], a[18], a[17], a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6],
+a[5], a[4], a[3], a[2], a[1], a[0]}),
+ .P({\NLW_blk00000003_P<47>_UNCONNECTED , \NLW_blk00000003_P<46>_UNCONNECTED , \NLW_blk00000003_P<45>_UNCONNECTED ,
+\NLW_blk00000003_P<44>_UNCONNECTED , \NLW_blk00000003_P<43>_UNCONNECTED , \NLW_blk00000003_P<42>_UNCONNECTED , \NLW_blk00000003_P<41>_UNCONNECTED ,
+\NLW_blk00000003_P<40>_UNCONNECTED , \NLW_blk00000003_P<39>_UNCONNECTED , \NLW_blk00000003_P<38>_UNCONNECTED , \NLW_blk00000003_P<37>_UNCONNECTED ,
+\NLW_blk00000003_P<36>_UNCONNECTED , s[35], s[34], s[33], s[32], s[31], s[30], s[29], s[28], s[27], s[26], s[25], s[24], s[23], s[22], s[21], s[20],
+s[19], s[18], s[17], s[16], s[15], s[14], s[13], s[12], s[11], s[10], s[9], s[8], s[7], s[6], s[5], s[4], s[3], s[2], s[1], s[0]}),
+ .OPMODE({sig00000001, sig00000001, sig00000001, sig00000001, sig00000002, sig00000002, sig00000002, sig00000002}),
+ .D({b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35]}),
+ .PCOUT({\NLW_blk00000003_PCOUT<47>_UNCONNECTED , \NLW_blk00000003_PCOUT<46>_UNCONNECTED , \NLW_blk00000003_PCOUT<45>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<44>_UNCONNECTED , \NLW_blk00000003_PCOUT<43>_UNCONNECTED , \NLW_blk00000003_PCOUT<42>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<41>_UNCONNECTED , \NLW_blk00000003_PCOUT<40>_UNCONNECTED , \NLW_blk00000003_PCOUT<39>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<38>_UNCONNECTED , \NLW_blk00000003_PCOUT<37>_UNCONNECTED , \NLW_blk00000003_PCOUT<36>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<35>_UNCONNECTED , \NLW_blk00000003_PCOUT<34>_UNCONNECTED , \NLW_blk00000003_PCOUT<33>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<32>_UNCONNECTED , \NLW_blk00000003_PCOUT<31>_UNCONNECTED , \NLW_blk00000003_PCOUT<30>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<29>_UNCONNECTED , \NLW_blk00000003_PCOUT<28>_UNCONNECTED , \NLW_blk00000003_PCOUT<27>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<26>_UNCONNECTED , \NLW_blk00000003_PCOUT<25>_UNCONNECTED , \NLW_blk00000003_PCOUT<24>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<23>_UNCONNECTED , \NLW_blk00000003_PCOUT<22>_UNCONNECTED , \NLW_blk00000003_PCOUT<21>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<20>_UNCONNECTED , \NLW_blk00000003_PCOUT<19>_UNCONNECTED , \NLW_blk00000003_PCOUT<18>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<17>_UNCONNECTED , \NLW_blk00000003_PCOUT<16>_UNCONNECTED , \NLW_blk00000003_PCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<14>_UNCONNECTED , \NLW_blk00000003_PCOUT<13>_UNCONNECTED , \NLW_blk00000003_PCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<11>_UNCONNECTED , \NLW_blk00000003_PCOUT<10>_UNCONNECTED , \NLW_blk00000003_PCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<8>_UNCONNECTED , \NLW_blk00000003_PCOUT<7>_UNCONNECTED , \NLW_blk00000003_PCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<5>_UNCONNECTED , \NLW_blk00000003_PCOUT<4>_UNCONNECTED , \NLW_blk00000003_PCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<2>_UNCONNECTED , \NLW_blk00000003_PCOUT<1>_UNCONNECTED , \NLW_blk00000003_PCOUT<0>_UNCONNECTED }),
+ .A({b[35], b[34], b[33], b[32], b[31], b[30], b[29], b[28], b[27], b[26], b[25], b[24], b[23], b[22], b[21], b[20], b[19], b[18]}),
+ .M({\NLW_blk00000003_M<35>_UNCONNECTED , \NLW_blk00000003_M<34>_UNCONNECTED , \NLW_blk00000003_M<33>_UNCONNECTED ,
+\NLW_blk00000003_M<32>_UNCONNECTED , \NLW_blk00000003_M<31>_UNCONNECTED , \NLW_blk00000003_M<30>_UNCONNECTED , \NLW_blk00000003_M<29>_UNCONNECTED ,
+\NLW_blk00000003_M<28>_UNCONNECTED , \NLW_blk00000003_M<27>_UNCONNECTED , \NLW_blk00000003_M<26>_UNCONNECTED , \NLW_blk00000003_M<25>_UNCONNECTED ,
+\NLW_blk00000003_M<24>_UNCONNECTED , \NLW_blk00000003_M<23>_UNCONNECTED , \NLW_blk00000003_M<22>_UNCONNECTED , \NLW_blk00000003_M<21>_UNCONNECTED ,
+\NLW_blk00000003_M<20>_UNCONNECTED , \NLW_blk00000003_M<19>_UNCONNECTED , \NLW_blk00000003_M<18>_UNCONNECTED , \NLW_blk00000003_M<17>_UNCONNECTED ,
+\NLW_blk00000003_M<16>_UNCONNECTED , \NLW_blk00000003_M<15>_UNCONNECTED , \NLW_blk00000003_M<14>_UNCONNECTED , \NLW_blk00000003_M<13>_UNCONNECTED ,
+\NLW_blk00000003_M<12>_UNCONNECTED , \NLW_blk00000003_M<11>_UNCONNECTED , \NLW_blk00000003_M<10>_UNCONNECTED , \NLW_blk00000003_M<9>_UNCONNECTED ,
+\NLW_blk00000003_M<8>_UNCONNECTED , \NLW_blk00000003_M<7>_UNCONNECTED , \NLW_blk00000003_M<6>_UNCONNECTED , \NLW_blk00000003_M<5>_UNCONNECTED ,
+\NLW_blk00000003_M<4>_UNCONNECTED , \NLW_blk00000003_M<3>_UNCONNECTED , \NLW_blk00000003_M<2>_UNCONNECTED , \NLW_blk00000003_M<1>_UNCONNECTED ,
+\NLW_blk00000003_M<0>_UNCONNECTED })
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
View
73 s36_add.xco
@@ -0,0 +1,73 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.2
+# Date: Mon Dec 31 18:00:27 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:c_addsub:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0
+# END Select
+# BEGIN Parameters
+CSET a_type=Signed
+CSET a_width=36
+CSET add_mode=Add
+CSET ainit_value=0
+CSET b_constant=false
+CSET b_type=Signed
+CSET b_value=000000000000000000000000000000000000
+CSET b_width=36
+CSET borrow_sense=Active_Low
+CSET bypass=false
+CSET bypass_ce_priority=CE_Overrides_Bypass
+CSET bypass_sense=Active_High
+CSET c_in=false
+CSET c_out=false
+CSET ce=false
+CSET component_name=s36_add
+CSET implementation=DSP48
+CSET latency=0
+CSET latency_configuration=Manual
+CSET out_width=36
+CSET sclr=false
+CSET sinit=false
+CSET sinit_value=0
+CSET sset=false
+CSET sync_ce_priority=Sync_Overrides_CE
+CSET sync_ctrl_priority=Reset_Overrides_Set
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-06-22T15:32:25Z
+# END Extra information
+GENERATE
+# CRC: 9a22ce39
View
331 s36_sub.v
@@ -0,0 +1,331 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: P.28xd
+// \ \ Application: netgen
+// / / Filename: s36_sub.v
+// /___/ /\ Timestamp: Mon Dec 31 12:02:10 2012
+// \ \ / \
+// \___\/\___\
+//
+// Command : -w -sim -ofmt verilog /home/josh/got/kovan-fpga/tmp/_cg/s36_sub.ngc /home/josh/got/kovan-fpga/tmp/_cg/s36_sub.v
+// Device : 6slx9csg324-2
+// Input file : /home/josh/got/kovan-fpga/tmp/_cg/s36_sub.ngc
+// Output file : /home/josh/got/kovan-fpga/tmp/_cg/s36_sub.v
+// # of Modules : 1
+// Design Name : s36_sub
+// Xilinx : /opt/Xilinx/14.2/ISE_DS/ISE/
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module s36_sub (
+a, b, s
+)/* synthesis syn_black_box syn_noprune=1 */;
+ input [35 : 0] a;
+ input [35 : 0] b;
+ output [35 : 0] s;
+
+ // synthesis translate_off
+
+ wire sig00000001;
+ wire sig00000002;
+ wire NLW_blk00000003_CARRYOUTF_UNCONNECTED;
+ wire NLW_blk00000003_CARRYOUT_UNCONNECTED;
+ wire \NLW_blk00000003_BCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<0>_UNCONNECTED ;
+ VCC blk00000001 (
+ .P(sig00000002)
+ );
+ GND blk00000002 (
+ .G(sig00000001)
+ );
+ DSP48A1 #(
+ .A0REG ( 0 ),
+ .A1REG ( 0 ),
+ .B0REG ( 0 ),
+ .B1REG ( 0 ),
+ .CARRYINREG ( 0 ),
+ .CARRYINSEL ( "OPMODE5" ),
+ .CREG ( 0 ),
+ .DREG ( 0 ),
+ .MREG ( 0 ),
+ .OPMODEREG ( 0 ),
+ .PREG ( 0 ),
+ .RSTTYPE ( "SYNC" ),
+ .CARRYOUTREG ( 0 ))
+ blk00000003 (
+ .CECARRYIN(sig00000001),
+ .RSTC(sig00000001),
+ .RSTCARRYIN(sig00000001),
+ .CED(sig00000001),
+ .RSTD(sig00000001),
+ .CEOPMODE(sig00000001),
+ .CEC(sig00000001),
+ .CARRYOUTF(NLW_blk00000003_CARRYOUTF_UNCONNECTED),
+ .RSTOPMODE(sig00000001),
+ .RSTM(sig00000001),
+ .CLK(sig00000001),
+ .RSTB(sig00000001),
+ .CEM(sig00000001),
+ .CEB(sig00000001),
+ .CARRYIN(sig00000001),
+ .CEP(sig00000001),
+ .CEA(sig00000001),
+ .CARRYOUT(NLW_blk00000003_CARRYOUT_UNCONNECTED),
+ .RSTA(sig00000001),
+ .RSTP(sig00000001),
+ .B({b[17], b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+ .BCOUT({\NLW_blk00000003_BCOUT<17>_UNCONNECTED , \NLW_blk00000003_BCOUT<16>_UNCONNECTED , \NLW_blk00000003_BCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<14>_UNCONNECTED , \NLW_blk00000003_BCOUT<13>_UNCONNECTED , \NLW_blk00000003_BCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<11>_UNCONNECTED , \NLW_blk00000003_BCOUT<10>_UNCONNECTED , \NLW_blk00000003_BCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<8>_UNCONNECTED , \NLW_blk00000003_BCOUT<7>_UNCONNECTED , \NLW_blk00000003_BCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<5>_UNCONNECTED , \NLW_blk00000003_BCOUT<4>_UNCONNECTED , \NLW_blk00000003_BCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<2>_UNCONNECTED , \NLW_blk00000003_BCOUT<1>_UNCONNECTED , \NLW_blk00000003_BCOUT<0>_UNCONNECTED }),
+ .PCIN({sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001}),
+ .C({a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[35], a[34], a[33], a[32], a[31], a[30], a[29], a[28],
+a[27], a[26], a[25], a[24], a[23], a[22], a[21], a[20], a[19], a[18], a[17], a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6],
+a[5], a[4], a[3], a[2], a[1], a[0]}),
+ .P({\NLW_blk00000003_P<47>_UNCONNECTED , \NLW_blk00000003_P<46>_UNCONNECTED , \NLW_blk00000003_P<45>_UNCONNECTED ,
+\NLW_blk00000003_P<44>_UNCONNECTED , \NLW_blk00000003_P<43>_UNCONNECTED , \NLW_blk00000003_P<42>_UNCONNECTED , \NLW_blk00000003_P<41>_UNCONNECTED ,
+\NLW_blk00000003_P<40>_UNCONNECTED , \NLW_blk00000003_P<39>_UNCONNECTED , \NLW_blk00000003_P<38>_UNCONNECTED , \NLW_blk00000003_P<37>_UNCONNECTED ,
+\NLW_blk00000003_P<36>_UNCONNECTED , s[35], s[34], s[33], s[32], s[31], s[30], s[29], s[28], s[27], s[26], s[25], s[24], s[23], s[22], s[21], s[20],
+s[19], s[18], s[17], s[16], s[15], s[14], s[13], s[12], s[11], s[10], s[9], s[8], s[7], s[6], s[5], s[4], s[3], s[2], s[1], s[0]}),
+ .OPMODE({sig00000002, sig00000001, sig00000001, sig00000001, sig00000002, sig00000002, sig00000002, sig00000002}),
+ .D({b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35], b[35]}),
+ .PCOUT({\NLW_blk00000003_PCOUT<47>_UNCONNECTED , \NLW_blk00000003_PCOUT<46>_UNCONNECTED , \NLW_blk00000003_PCOUT<45>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<44>_UNCONNECTED , \NLW_blk00000003_PCOUT<43>_UNCONNECTED , \NLW_blk00000003_PCOUT<42>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<41>_UNCONNECTED , \NLW_blk00000003_PCOUT<40>_UNCONNECTED , \NLW_blk00000003_PCOUT<39>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<38>_UNCONNECTED , \NLW_blk00000003_PCOUT<37>_UNCONNECTED , \NLW_blk00000003_PCOUT<36>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<35>_UNCONNECTED , \NLW_blk00000003_PCOUT<34>_UNCONNECTED , \NLW_blk00000003_PCOUT<33>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<32>_UNCONNECTED , \NLW_blk00000003_PCOUT<31>_UNCONNECTED , \NLW_blk00000003_PCOUT<30>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<29>_UNCONNECTED , \NLW_blk00000003_PCOUT<28>_UNCONNECTED , \NLW_blk00000003_PCOUT<27>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<26>_UNCONNECTED , \NLW_blk00000003_PCOUT<25>_UNCONNECTED , \NLW_blk00000003_PCOUT<24>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<23>_UNCONNECTED , \NLW_blk00000003_PCOUT<22>_UNCONNECTED , \NLW_blk00000003_PCOUT<21>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<20>_UNCONNECTED , \NLW_blk00000003_PCOUT<19>_UNCONNECTED , \NLW_blk00000003_PCOUT<18>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<17>_UNCONNECTED , \NLW_blk00000003_PCOUT<16>_UNCONNECTED , \NLW_blk00000003_PCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<14>_UNCONNECTED , \NLW_blk00000003_PCOUT<13>_UNCONNECTED , \NLW_blk00000003_PCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<11>_UNCONNECTED , \NLW_blk00000003_PCOUT<10>_UNCONNECTED , \NLW_blk00000003_PCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<8>_UNCONNECTED , \NLW_blk00000003_PCOUT<7>_UNCONNECTED , \NLW_blk00000003_PCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<5>_UNCONNECTED , \NLW_blk00000003_PCOUT<4>_UNCONNECTED , \NLW_blk00000003_PCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<2>_UNCONNECTED , \NLW_blk00000003_PCOUT<1>_UNCONNECTED , \NLW_blk00000003_PCOUT<0>_UNCONNECTED }),
+ .A({b[35], b[34], b[33], b[32], b[31], b[30], b[29], b[28], b[27], b[26], b[25], b[24], b[23], b[22], b[21], b[20], b[19], b[18]}),
+ .M({\NLW_blk00000003_M<35>_UNCONNECTED , \NLW_blk00000003_M<34>_UNCONNECTED , \NLW_blk00000003_M<33>_UNCONNECTED ,
+\NLW_blk00000003_M<32>_UNCONNECTED , \NLW_blk00000003_M<31>_UNCONNECTED , \NLW_blk00000003_M<30>_UNCONNECTED , \NLW_blk00000003_M<29>_UNCONNECTED ,
+\NLW_blk00000003_M<28>_UNCONNECTED , \NLW_blk00000003_M<27>_UNCONNECTED , \NLW_blk00000003_M<26>_UNCONNECTED , \NLW_blk00000003_M<25>_UNCONNECTED ,
+\NLW_blk00000003_M<24>_UNCONNECTED , \NLW_blk00000003_M<23>_UNCONNECTED , \NLW_blk00000003_M<22>_UNCONNECTED , \NLW_blk00000003_M<21>_UNCONNECTED ,
+\NLW_blk00000003_M<20>_UNCONNECTED , \NLW_blk00000003_M<19>_UNCONNECTED , \NLW_blk00000003_M<18>_UNCONNECTED , \NLW_blk00000003_M<17>_UNCONNECTED ,
+\NLW_blk00000003_M<16>_UNCONNECTED , \NLW_blk00000003_M<15>_UNCONNECTED , \NLW_blk00000003_M<14>_UNCONNECTED , \NLW_blk00000003_M<13>_UNCONNECTED ,
+\NLW_blk00000003_M<12>_UNCONNECTED , \NLW_blk00000003_M<11>_UNCONNECTED , \NLW_blk00000003_M<10>_UNCONNECTED , \NLW_blk00000003_M<9>_UNCONNECTED ,
+\NLW_blk00000003_M<8>_UNCONNECTED , \NLW_blk00000003_M<7>_UNCONNECTED , \NLW_blk00000003_M<6>_UNCONNECTED , \NLW_blk00000003_M<5>_UNCONNECTED ,
+\NLW_blk00000003_M<4>_UNCONNECTED , \NLW_blk00000003_M<3>_UNCONNECTED , \NLW_blk00000003_M<2>_UNCONNECTED , \NLW_blk00000003_M<1>_UNCONNECTED ,
+\NLW_blk00000003_M<0>_UNCONNECTED })
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
View
73 s36_sub.xco
@@ -0,0 +1,73 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.2
+# Date: Mon Dec 31 18:01:36 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:c_addsub:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0
+# END Select
+# BEGIN Parameters
+CSET a_type=Signed
+CSET a_width=36
+CSET add_mode=Subtract
+CSET ainit_value=0
+CSET b_constant=false
+CSET b_type=Signed
+CSET b_value=000000000000000000000000000000000000
+CSET b_width=36
+CSET borrow_sense=Active_Low
+CSET bypass=false
+CSET bypass_ce_priority=CE_Overrides_Bypass
+CSET bypass_sense=Active_High
+CSET c_in=false
+CSET c_out=false
+CSET ce=false
+CSET component_name=s36_sub
+CSET implementation=DSP48
+CSET latency=0
+CSET latency_configuration=Manual
+CSET out_width=36
+CSET sclr=false
+CSET sinit=false
+CSET sinit_value=0
+CSET sset=false
+CSET sync_ce_priority=Sync_Overrides_CE
+CSET sync_ctrl_priority=Reset_Overrides_Set
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-06-22T15:32:25Z
+# END Extra information
+GENERATE
+# CRC: 61947c73
View
20 spi.v
@@ -28,10 +28,10 @@ module spi(
input [9:0] adc_15_in,
input [9:0] adc_16_in,
input [0:0] charge_acp_in,
- input [15:0] bemf_0,
- input [15:0] bemf_1,
- input [15:0] bemf_2,
- input [15:0] bemf_3,
+ input [31:0] bemf_0,
+ input [31:0] bemf_1,
+ input [31:0] bemf_2,
+ input [31:0] bemf_3,
input [15:0] servo_pwm0_high,
input [15:0] servo_pwm1_high,
input [15:0] servo_pwm2_high,
@@ -153,10 +153,10 @@ module spi(
10'd17: SPI_OUT_tmp <= {6'd0, adc_15_in[9:0]};//SPI_REGr[287:272];
10'd18: SPI_OUT_tmp <= {6'd0, adc_16_in[9:0]};//SPI_REGr[303:288];
10'd19: SPI_OUT_tmp <= {15'd0, charge_acp_in};//10'd19: [319:304];
- 10'd20: SPI_OUT_tmp <= bemf_0;//10'd20: SPI_OUTr <= SPI_REGr[335:320];
- 10'd21: SPI_OUT_tmp <= bemf_1;//10'd21: SPI_OUTr <= SPI_REGr[351:336];
- 10'd22: SPI_OUT_tmp <= bemf_2;//10'd22: SPI_OUTr <= SPI_REGr[367:352];
- 10'd23: SPI_OUT_tmp <= bemf_3;//10'd23: SPI_OUTr <= SPI_REGr[383:368];
+ 10'd20: SPI_OUT_tmp <= bemf_0[15:0];//10'd20: SPI_OUTr <= SPI_REGr[335:320];
+ 10'd21: SPI_OUT_tmp <= bemf_1[15:0];//10'd21: SPI_OUTr <= SPI_REGr[351:336];
+ 10'd22: SPI_OUT_tmp <= bemf_2[15:0];//10'd22: SPI_OUTr <= SPI_REGr[367:352];
+ 10'd23: SPI_OUT_tmp <= bemf_3[15:0];//10'd23: SPI_OUTr <= SPI_REGr[383:368];
//10'd24: SPI_OUT_tmp <= SPI_REGr[399:384];
10'd25: SPI_OUT_tmp <= servo_pwm0_high;//SPI_REGr[415:400];
10'd26: SPI_OUT_tmp <= servo_pwm1_high;//SPI_REGr[431:416];
@@ -174,6 +174,10 @@ module spi(
10'd38: SPI_OUT_tmp <= {15'd0, dig_update};//SPI_REGr[623:608];
10'd39: SPI_OUT_tmp <= {8'd0, mot_drive_code};//SPI_REGr[639:624];
10'd40: SPI_OUT_tmp <= {11'd0, mot_allstop}; //SPI_REGr[655:640];
+ 10'd41: SPI_OUT_tmp <= bemf_0[31:16];
+ 10'd42: SPI_OUT_tmp <= bemf_1[31:16];
+ 10'd43: SPI_OUT_tmp <= bemf_2[31:16];
+ 10'd44: SPI_OUT_tmp <= bemf_3[31:16];
//10'd41: SPI_OUT_tmp <= pid_p_goal_0;
//10'd42: SPI_OUT_tmp <= pid_p_goal_1;
//10'd43: SPI_OUT_tmp <= pid_p_goal_2;
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