Skip to content
Browse files

backemf update was happening too fast. starting to hook up the pid co…

…ntroller
  • Loading branch information...
1 parent 0e141a6 commit 81d9a0d1327ef8f62948afd7caeb817f13d68da4 Josh S committed Dec 22, 2012
Showing with 1,429 additions and 623 deletions.
  1. +21 −21 bemf_update.v
  2. BIN kovan.bit
  3. +85 −87 kovan.v
  4. +233 −253 s13_add.v
  5. +3 −3 s13_add.xco
  6. +1 −1 s13_mult.v
  7. +1 −1 s13_mult.xco
  8. +234 −254 s13_sub.v
  9. +3 −3 s13_sub.xco
  10. +351 −0 s20_add.v
  11. +73 −0 s20_add.xco
  12. +351 −0 s20_sub.v
  13. +73 −0 s20_sub.xco
View
42 bemf_update.v
@@ -5,10 +5,10 @@ module bemf_update(
input [9:0] bemf_adc_l,
input [1:0] mot_sel_in,
input in_valid,
- input [21:0] bemf_in,
- input [21:0] bemf_calib_in,
+ input [19:0] bemf_in,
+ input [19:0] bemf_calib_in,
input clk,
- output [21:0] bemf_out,
+ output [19:0] bemf_out,
output [1:0] mot_sel_out,
output out_valid
);
@@ -17,30 +17,30 @@ module bemf_update(
// subtract the high and low side of the motor
reg [9:0] bemf_sub_in_a_r = 10'd0;
reg [9:0] bemf_sub_in_b_r = 10'd0;
- wire [21:0] bemf_sub_out;
- s22_sub bemf_sub(
- .a({16'd0, bemf_sub_in_a_r}),
- .b({16'd0, bemf_sub_in_b_r}),
+ wire [19:0] bemf_sub_out;
+ s20_sub bemf_sub(
+ .a({10'd0, bemf_sub_in_a_r}),
+ .b({10'd0, bemf_sub_in_b_r}),
.s(bemf_sub_out)
);
// adjust by the calibration amount
- reg [21:0] calib_sub_in_a_r = 22'd0;
- reg [21:0] calib_sub_in_b_r = 22'd0;
- wire [21:0] calib_sub_out;
- s22_sub calib_sub(
+ reg [19:0] calib_sub_in_a_r = 20'd0;
+ reg [19:0] calib_sub_in_b_r = 20'd0;
+ wire [19:0] calib_sub_out;
+ s20_sub calib_sub(
.a(calib_sub_in_a_r),
.b(calib_sub_in_b_r),
.s(calib_sub_out)
);
// integrate the calibrated back emf readings
- reg [21:0] bemf_integr_in_a_r = 22'd0;
- reg [21:0] bemf_integr_in_b_r = 22'd0;
- wire [21:0] bemf_integr_out;
- s22_add bemf_integr(
+ reg [19:0] bemf_integr_in_a_r = 20'd0;
+ reg [19:0] bemf_integr_in_b_r = 20'd0;
+ wire [19:0] bemf_integr_out;
+ s20_add bemf_integr(
.a(bemf_integr_in_a_r),
.b(bemf_integr_in_b_r),
.s(bemf_integr_out)
@@ -57,10 +57,10 @@ module bemf_update(
reg in_valid_2 = 1'd0;
reg in_valid_3 = 1'd0;
- reg [21:0] bemf_out_r = 22'd0;
+ reg [19:0] bemf_out_r = 20'd0;
- reg [21:0] bemf_in_0 = 22'd0;
- reg [21:0] bemf_in_1 = 22'd0;
+ reg [19:0] bemf_in_0 = 20'd0;
+ reg [19:0] bemf_in_1 = 20'd0;
always @ (posedge clk) begin
@@ -84,10 +84,10 @@ module bemf_update(
// pipeline stage 2: subtracted the calibration info
// deadbanding
- if (calib_sub_out[21] == 1'b1)
- bemf_integr_in_a_r <= (~calib_sub_out > 22'd21) ? calib_sub_out : 22'd0; //negative
+ if (calib_sub_out[19] == 1'b1)
+ bemf_integr_in_a_r <= (~calib_sub_out > 16'd21) ? calib_sub_out : 20'd0; //negative
else
- bemf_integr_in_a_r <= (calib_sub_out > 22'd20) ? calib_sub_out : 22'd0; // positive
+ bemf_integr_in_a_r <= (calib_sub_out > 15'd20) ? calib_sub_out : 20'd0; // positive
//bemf_integr_in_a_r <= calib_sub_out;
bemf_integr_in_b_r <= bemf_in_1;
View
BIN kovan.bit
Binary file not shown.
View
172 kovan.v
@@ -312,43 +312,43 @@ module kovan (
reg [9:0] adc_15_new;
reg [9:0] adc_16_new;
- wire [21:0] bemf_0;
- wire [21:0] bemf_1;
- wire [21:0] bemf_2;
- wire [21:0] bemf_3;
+ wire [19:0] bemf_0;
+ wire [19:0] bemf_1;
+ wire [19:0] bemf_2;
+ wire [19:0] bemf_3;
- reg [21:0] bemf_0_r;
- reg [21:0] bemf_1_r;
- reg [21:0] bemf_2_r;
- reg [21:0] bemf_3_r;
+ reg [19:0] bemf_0_r;
+ reg [19:0] bemf_1_r;
+ reg [19:0] bemf_2_r;
+ reg [19:0] bemf_3_r;
- reg [21:0] bemf_0_r_208M = 22'd0;
- reg [21:0] bemf_1_r_208M = 22'd0;
- reg [21:0] bemf_2_r_208M = 22'd0;
- reg [21:0] bemf_3_r_208M = 22'd0;
+ reg [19:0] bemf_0_r_208M = 20'd0;
+ reg [19:0] bemf_1_r_208M = 20'd0;
+ reg [19:0] bemf_2_r_208M = 20'd0;
+ reg [19:0] bemf_3_r_208M = 20'd0;
- reg [21:0] bemf_0_calib = 22'd0;
- reg [21:0] bemf_1_calib = 22'd0;
- reg [21:0] bemf_2_calib = 22'd0;
- reg [21:0] bemf_3_calib = 22'd0;
+ reg [19:0] bemf_0_calib = 20'd0;
+ reg [19:0] bemf_1_calib = 20'd0;
+ reg [19:0] bemf_2_calib = 20'd0;
+ reg [19:0] bemf_3_calib = 20'd0;
- reg [11:0] mot_duty0_old = 12'd0;
- reg [11:0] mot_duty1_old = 12'd0;
- reg [11:0] mot_duty2_old = 12'd0;
- reg [11:0] mot_duty3_old = 12'd0;
+ reg [15:0] mot_duty0_old = 16'd0;
+ reg [15:0] mot_duty1_old = 16'd0;
+ reg [15:0] mot_duty2_old = 16'd0;
+ reg [15:0] mot_duty3_old = 16'd0;
reg [23:8] servo_pwm0_old = 16'd0;
reg [23:8] servo_pwm1_old = 16'd0;
reg [23:8] servo_pwm2_old = 16'd0;
reg [23:8] servo_pwm3_old = 16'd0;
- wire [11:0] mot_duty0_new;
- wire [11:0] mot_duty1_new;
- wire [11:0] mot_duty2_new;
- wire [11:0] mot_duty3_new;
+ wire [15:0] mot_duty0_new;
+ wire [15:0] mot_duty1_new;
+ wire [15:0] mot_duty2_new;
+ wire [15:0] mot_duty3_new;
wire [23:8] servo_pwm0_new;
wire [23:8] servo_pwm1_new;
@@ -368,36 +368,30 @@ module kovan (
wire [7:0] dig_pu_new;
wire [7:0] dig_oe_new;
wire [7:0] ana_pu_new;
- wire [11:0] mot_duty_0_new;
- wire [11:0] mot_duty_1_new;
- wire [11:0] mot_duty_2_new;
- wire [11:0] mot_duty_3_new;
+ wire [15:0] mot_duty_0_new;
+ wire [15:0] mot_duty_1_new;
+ wire [15:0] mot_duty_2_new;
+ wire [15:0] mot_duty_3_new;
wire [0:0] dig_sample_new;
wire [0:0] dig_update_new;
wire [7:0] mot_drive_code_new;
wire [4:0] mot_allstop_new;
-/*
- reg bemf_calib_cmd_old = 1'd0;
- wire bemf_calib_cmd_new;
- */
-
- //reg [12:0] pid_pwm0;
- //reg [12:0] pid_pwm1;
- //reg [12:0] pid_pwm2;
- //reg [12:0] pid_pwm3;
-
- // 6 assign out = (enable) ? data : 1'bz;
- //reg using_pid0 = 1'b0;
- //reg using_pid1 = 1'b0;
- //reg using_pid2 = 1'b0;
- //reg using_pid3 = 1'b0;
+ reg [11:0] pid_pwm0 = 12'd0;
+ reg [11:0] pid_pwm1 = 12'd0;
+ reg [11:0] pid_pwm2 = 12'd0;
+ reg [11:0] pid_pwm3 = 12'd0;
+
+ reg pid_dir0 = 1'd0;
+ reg pid_dir1 = 1'd0;
+ reg pid_dir2 = 1'd0;
+ reg pid_dir3 = 1'd0;
// TODO: direction, convert to unsigned
- assign mot_duty0 = mot_duty0_new; //(using_pid0) ? pid_pwm0[11:0] : mot_duty0_r;
- assign mot_duty1 = mot_duty1_new; //(using_pid1) ? pid_pwm1[11:0] : mot_duty1_r;
- assign mot_duty2 = mot_duty2_new; //(using_pid2) ? pid_pwm2[11:0] : mot_duty2_r;
- assign mot_duty3 = mot_duty3_new; //(using_pid3) ? pid_pwm3[11:0] : mot_duty3_r;
+ assign mot_duty0 = (mot_duty0_old[15]) ? pid_pwm0[11:0] : mot_duty0_new;
+ assign mot_duty1 = (mot_duty1_old[15]) ? pid_pwm1[11:0] : mot_duty1_new;
+ assign mot_duty2 = (mot_duty2_old[15]) ? pid_pwm2[11:0] : mot_duty2_new;
+ assign mot_duty3 = (mot_duty3_old[15]) ? pid_pwm3[11:0] : mot_duty3_new;
assign servo0_pwm_pulse = {servo_pwm0_old, 8'd0};
assign servo1_pwm_pulse = {servo_pwm1_old, 8'd0};
@@ -409,13 +403,14 @@ module kovan (
assign dig_out_val = dig_out_val_old;
assign dig_oe = dig_oe_old;
assign dig_pu = dig_pu_old;
- assign ana_pu = ana_pu_old;
- //assign dig_in_val = dig_in_val_old;
- //assign dig_val_good = dig_val_good_old;
- //assign dig_busy = dig_busy_old;
+ assign ana_pu = ana_pu_old;
+
assign dig_sample = dig_sample_old;
assign dig_update = dig_update_old;
+
+ //TODO: motor drive code assignment should consider pid mode
assign mot_drive_code = mot_drive_code_old;
+
assign mot_allstop = mot_allstop_old;
@@ -506,27 +501,16 @@ module kovan (
reg [9:0] bemf_adc_l = 10'd0;
reg [1:0] bemf_mot_sel_in = 2'd0;
reg bemf_in_valid = 1'd0;
- reg [21:0] bemf_in = 22'd0;
- reg [21:0] bemf_calib_in = 22'd0;
+ reg [19:0] bemf_in = 20'd0;
+ reg [19:0] bemf_calib_in = 20'd0;
wire [1:0] bemf_mot_sel_out;
wire bemf_out_valid;
- wire [21:0] bemf_out;
+ wire [19:0] bemf_out;
reg [15:0] bemf_counter = 16'd0; // can count for up to ~20mS
reg [2:0] bemf_state = 3'd0;
- /*
- always @(posedge clk3p2M) begin
-
- bemf_0_r <= bemf_out + 3'd1;
- bemf_1_r <= bemf_out + 3'd2;
- bemf_2_r <= bemf_out + 3'd3;
- bemf_3_r <= bemf_out + 3'd4;
-
- end
- */
-
always @(posedge clk3p2M) begin
@@ -632,8 +616,8 @@ module kovan (
3'd6: begin
bemf_in_valid <= 1'd0;
- if (bemf_counter > 64000) begin// 20mS total
- bemf_state <= bemf_state + 1'd1;
+ if (bemf_counter < 64000) begin
+ //bemf_state <= bemf_state + 1'd1;
bemf_counter <= bemf_counter + 1'd1;
end else begin
bemf_state <= 3'd0;
@@ -693,10 +677,10 @@ module kovan (
.adc_15_in(adc_15_old),
.adc_16_in(adc_16_old),
.charge_acp_in(CHG_ACP),
- .bemf_0(bemf_0_r_208M[21:6]),
- .bemf_1(bemf_1_r_208M[21:6]),
- .bemf_2(bemf_2_r_208M[21:6]),
- .bemf_3(bemf_3_r_208M[21:6]),
+ .bemf_0(bemf_0_r_208M[19:4]),
+ .bemf_1(bemf_1_r_208M[19:4]),
+ .bemf_2(bemf_2_r_208M[19:4]),
+ .bemf_3(bemf_3_r_208M[19:4]),
.servo_pwm0_high(servo_pwm0_old),
.servo_pwm1_high(servo_pwm1_old),
.servo_pwm2_high(servo_pwm2_old),
@@ -736,18 +720,19 @@ module kovan (
);
-/*
+
+
// Inputs
- reg [12:0] pos_d;
- reg [12:0] pos;
- reg [12:0] err_prev;
- reg [12:0] int_err_prev;
- reg [12:0] Kp_n;
- reg [7:0] Kp_d;
- reg [12:0] Ki_n;
- reg [7:0] Ki_d;
- reg [12:0] Kd_n;
- reg [7:0] Kd_d;
+ reg [12:0] pos_d = 13'd0;
+ reg [12:0] pos = 13'd0;
+ reg [12:0] err_prev = 13'd0;
+ reg [12:0] int_err_prev = 13'd0;
+ reg [12:0] Kp_n = 13'd0;
+ reg [7:0] Kp_d = 13'd0;
+ reg [12:0] Ki_n = 13'd0;
+ reg [7:0] Ki_d = 13'd0;
+ reg [12:0] Kd_n = 13'd0;
+ reg [7:0] Kd_d = 13'd0;
// Outputs
wire [12:0] pid_pwm;
@@ -773,15 +758,28 @@ module kovan (
.int_err(pid_int_err),
.dir(pid_dir)
);
-*/
+
+
+
+ always @(posedge clk3p2M) begin
+ pid_pwm0 <= pid_pwm;
+ pid_pwm1 <= pid_pwm;
+ pid_pwm2 <= pid_pwm;
+ pid_pwm3 <= pid_pwm;
+ pid_dir0 <= pid_dir;
+ pid_dir1 <= pid_dir;
+ pid_dir2 <= pid_dir;
+ pid_dir3 <= pid_dir;
+ end
+
quad_motor motor_controller (
.clk(clk26buf),
.MOT_EN(!mot_allstop[0]),
- .duty0(mot_duty0),
- .duty1(mot_duty1),
- .duty2(mot_duty2),
- .duty3(mot_duty3),
+ .duty0(mot_duty0[11:0]),
+ .duty1(mot_duty1[11:0]),
+ .duty2(mot_duty2[11:0]),
+ .duty3(mot_duty3[11:0]),
.drive_code(mot_drive_code),
.bemf_sensing(bemf_sensing),
.pwm(MOT_PWM),
View
486 s13_add.v
@@ -7,7 +7,7 @@
// \ \ \/ Version: P.28xd
// \ \ Application: netgen
// / / Filename: s13_add.v
-// /___/ /\ Timestamp: Sat Dec 15 16:37:50 2012
+// /___/ /\ Timestamp: Sat Dec 22 14:54:09 2012
// \ \ / \
// \___\/\___\
//
@@ -44,260 +44,240 @@ a, b, s
wire sig00000001;
wire sig00000002;
- wire sig00000003;
- wire sig00000004;
- wire sig00000005;
- wire sig00000006;
- wire sig00000007;
- wire sig00000008;
- wire sig00000009;
- wire sig0000000a;
- wire sig0000000b;
- wire sig0000000c;
- wire sig0000000d;
- wire sig0000000e;
- wire sig0000000f;
- wire sig00000010;
- wire sig00000011;
- wire sig00000012;
- wire sig00000013;
- wire sig00000014;
- wire sig00000015;
- wire sig00000016;
- wire sig00000017;
- wire sig00000018;
- wire sig00000019;
- wire sig0000001a;
- GND blk00000001 (
+ wire NLW_blk00000003_CARRYOUTF_UNCONNECTED;
+ wire NLW_blk00000003_CARRYOUT_UNCONNECTED;
+ wire \NLW_blk00000003_BCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<0>_UNCONNECTED ;
+ VCC blk00000001 (
+ .P(sig00000002)
+ );
+ GND blk00000002 (
.G(sig00000001)
);
- XORCY blk00000002 (
- .CI(sig00000001),
- .LI(sig0000000e),
- .O(s[0])
- );
- XORCY blk00000003 (
- .CI(sig0000000f),
- .LI(sig0000000d),
- .O(s[12])
- );
- XORCY blk00000004 (
- .CI(sig00000010),
- .LI(sig00000002),
- .O(s[11])
- );
- XORCY blk00000005 (
- .CI(sig00000011),
- .LI(sig00000003),
- .O(s[10])
- );
- XORCY blk00000006 (
- .CI(sig00000012),
- .LI(sig00000004),
- .O(s[9])
- );
- XORCY blk00000007 (
- .CI(sig00000013),
- .LI(sig00000005),
- .O(s[8])
- );
- XORCY blk00000008 (
- .CI(sig00000014),
- .LI(sig00000006),
- .O(s[7])
- );
- XORCY blk00000009 (
- .CI(sig00000015),
- .LI(sig00000007),
- .O(s[6])
- );
- XORCY blk0000000a (
- .CI(sig00000016),
- .LI(sig00000008),
- .O(s[5])
- );
- XORCY blk0000000b (
- .CI(sig00000017),
- .LI(sig00000009),
- .O(s[4])
- );
- XORCY blk0000000c (
- .CI(sig00000018),
- .LI(sig0000000a),
- .O(s[3])
- );
- XORCY blk0000000d (
- .CI(sig00000019),
- .LI(sig0000000b),
- .O(s[2])
- );
- XORCY blk0000000e (
- .CI(sig0000001a),
- .LI(sig0000000c),
- .O(s[1])
- );
- MUXCY blk0000000f (
- .CI(sig00000010),
- .DI(a[11]),
- .S(sig00000002),
- .O(sig0000000f)
- );
- MUXCY blk00000010 (
- .CI(sig00000011),
- .DI(a[10]),
- .S(sig00000003),
- .O(sig00000010)
- );
- MUXCY blk00000011 (
- .CI(sig00000012),
- .DI(a[9]),
- .S(sig00000004),
- .O(sig00000011)
- );
- MUXCY blk00000012 (
- .CI(sig00000013),
- .DI(a[8]),
- .S(sig00000005),
- .O(sig00000012)
- );
- MUXCY blk00000013 (
- .CI(sig00000014),
- .DI(a[7]),
- .S(sig00000006),
- .O(sig00000013)
- );
- MUXCY blk00000014 (
- .CI(sig00000015),
- .DI(a[6]),
- .S(sig00000007),
- .O(sig00000014)
- );
- MUXCY blk00000015 (
- .CI(sig00000016),
- .DI(a[5]),
- .S(sig00000008),
- .O(sig00000015)
- );
- MUXCY blk00000016 (
- .CI(sig00000017),
- .DI(a[4]),
- .S(sig00000009),
- .O(sig00000016)
- );
- MUXCY blk00000017 (
- .CI(sig00000018),
- .DI(a[3]),
- .S(sig0000000a),
- .O(sig00000017)
- );
- MUXCY blk00000018 (
- .CI(sig00000019),
- .DI(a[2]),
- .S(sig0000000b),
- .O(sig00000018)
- );
- MUXCY blk00000019 (
- .CI(sig0000001a),
- .DI(a[1]),
- .S(sig0000000c),
- .O(sig00000019)
- );
- MUXCY blk0000001a (
- .CI(sig00000001),
- .DI(a[0]),
- .S(sig0000000e),
- .O(sig0000001a)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk0000001b (
- .I0(a[0]),
- .I1(b[0]),
- .O(sig0000000e)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk0000001c (
- .I0(a[1]),
- .I1(b[1]),
- .O(sig0000000c)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk0000001d (
- .I0(a[2]),
- .I1(b[2]),
- .O(sig0000000b)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk0000001e (
- .I0(a[3]),
- .I1(b[3]),
- .O(sig0000000a)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk0000001f (
- .I0(a[4]),
- .I1(b[4]),
- .O(sig00000009)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk00000020 (
- .I0(a[5]),
- .I1(b[5]),
- .O(sig00000008)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk00000021 (
- .I0(a[6]),
- .I1(b[6]),
- .O(sig00000007)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk00000022 (
- .I0(a[7]),
- .I1(b[7]),
- .O(sig00000006)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk00000023 (
- .I0(a[8]),
- .I1(b[8]),
- .O(sig00000005)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk00000024 (
- .I0(a[9]),
- .I1(b[9]),
- .O(sig00000004)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk00000025 (
- .I0(a[10]),
- .I1(b[10]),
- .O(sig00000003)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk00000026 (
- .I0(a[11]),
- .I1(b[11]),
- .O(sig00000002)
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- blk00000027 (
- .I0(a[12]),
- .I1(b[12]),
- .O(sig0000000d)
+ DSP48A1 #(
+ .A0REG ( 0 ),
+ .A1REG ( 0 ),
+ .B0REG ( 0 ),
+ .B1REG ( 0 ),
+ .CARRYINREG ( 0 ),
+ .CARRYINSEL ( "OPMODE5" ),
+ .CREG ( 0 ),
+ .DREG ( 0 ),
+ .MREG ( 0 ),
+ .OPMODEREG ( 0 ),
+ .PREG ( 0 ),
+ .RSTTYPE ( "SYNC" ),
+ .CARRYOUTREG ( 0 ))
+ blk00000003 (
+ .CECARRYIN(sig00000001),
+ .RSTC(sig00000001),
+ .RSTCARRYIN(sig00000001),
+ .CED(sig00000001),
+ .RSTD(sig00000001),
+ .CEOPMODE(sig00000001),
+ .CEC(sig00000001),
+ .CARRYOUTF(NLW_blk00000003_CARRYOUTF_UNCONNECTED),
+ .RSTOPMODE(sig00000001),
+ .RSTM(sig00000001),
+ .CLK(sig00000001),
+ .RSTB(sig00000001),
+ .CEM(sig00000001),
+ .CEB(sig00000001),
+ .CARRYIN(sig00000001),
+ .CEP(sig00000001),
+ .CEA(sig00000001),
+ .CARRYOUT(NLW_blk00000003_CARRYOUT_UNCONNECTED),
+ .RSTA(sig00000001),
+ .RSTP(sig00000001),
+ .B({b[12], b[12], b[12], b[12], b[12], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+ .BCOUT({\NLW_blk00000003_BCOUT<17>_UNCONNECTED , \NLW_blk00000003_BCOUT<16>_UNCONNECTED , \NLW_blk00000003_BCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<14>_UNCONNECTED , \NLW_blk00000003_BCOUT<13>_UNCONNECTED , \NLW_blk00000003_BCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<11>_UNCONNECTED , \NLW_blk00000003_BCOUT<10>_UNCONNECTED , \NLW_blk00000003_BCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<8>_UNCONNECTED , \NLW_blk00000003_BCOUT<7>_UNCONNECTED , \NLW_blk00000003_BCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<5>_UNCONNECTED , \NLW_blk00000003_BCOUT<4>_UNCONNECTED , \NLW_blk00000003_BCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<2>_UNCONNECTED , \NLW_blk00000003_BCOUT<1>_UNCONNECTED , \NLW_blk00000003_BCOUT<0>_UNCONNECTED }),
+ .PCIN({sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001}),
+ .C({a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12],
+a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[11], a[10], a[9], a[8], a[7], a[6],
+a[5], a[4], a[3], a[2], a[1], a[0]}),
+ .P({\NLW_blk00000003_P<47>_UNCONNECTED , \NLW_blk00000003_P<46>_UNCONNECTED , \NLW_blk00000003_P<45>_UNCONNECTED ,
+\NLW_blk00000003_P<44>_UNCONNECTED , \NLW_blk00000003_P<43>_UNCONNECTED , \NLW_blk00000003_P<42>_UNCONNECTED , \NLW_blk00000003_P<41>_UNCONNECTED ,
+\NLW_blk00000003_P<40>_UNCONNECTED , \NLW_blk00000003_P<39>_UNCONNECTED , \NLW_blk00000003_P<38>_UNCONNECTED , \NLW_blk00000003_P<37>_UNCONNECTED ,
+\NLW_blk00000003_P<36>_UNCONNECTED , \NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED ,
+\NLW_blk00000003_P<32>_UNCONNECTED , \NLW_blk00000003_P<31>_UNCONNECTED , \NLW_blk00000003_P<30>_UNCONNECTED , \NLW_blk00000003_P<29>_UNCONNECTED ,
+\NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED ,
+\NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , \NLW_blk00000003_P<21>_UNCONNECTED ,
+\NLW_blk00000003_P<20>_UNCONNECTED , \NLW_blk00000003_P<19>_UNCONNECTED , \NLW_blk00000003_P<18>_UNCONNECTED , \NLW_blk00000003_P<17>_UNCONNECTED ,
+\NLW_blk00000003_P<16>_UNCONNECTED , \NLW_blk00000003_P<15>_UNCONNECTED , \NLW_blk00000003_P<14>_UNCONNECTED , \NLW_blk00000003_P<13>_UNCONNECTED ,
+s[12], s[11], s[10], s[9], s[8], s[7], s[6], s[5], s[4], s[3], s[2], s[1], s[0]}),
+ .OPMODE({sig00000001, sig00000001, sig00000001, sig00000001, sig00000002, sig00000002, sig00000002, sig00000002}),
+ .D({b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12]}),
+ .PCOUT({\NLW_blk00000003_PCOUT<47>_UNCONNECTED , \NLW_blk00000003_PCOUT<46>_UNCONNECTED , \NLW_blk00000003_PCOUT<45>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<44>_UNCONNECTED , \NLW_blk00000003_PCOUT<43>_UNCONNECTED , \NLW_blk00000003_PCOUT<42>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<41>_UNCONNECTED , \NLW_blk00000003_PCOUT<40>_UNCONNECTED , \NLW_blk00000003_PCOUT<39>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<38>_UNCONNECTED , \NLW_blk00000003_PCOUT<37>_UNCONNECTED , \NLW_blk00000003_PCOUT<36>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<35>_UNCONNECTED , \NLW_blk00000003_PCOUT<34>_UNCONNECTED , \NLW_blk00000003_PCOUT<33>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<32>_UNCONNECTED , \NLW_blk00000003_PCOUT<31>_UNCONNECTED , \NLW_blk00000003_PCOUT<30>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<29>_UNCONNECTED , \NLW_blk00000003_PCOUT<28>_UNCONNECTED , \NLW_blk00000003_PCOUT<27>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<26>_UNCONNECTED , \NLW_blk00000003_PCOUT<25>_UNCONNECTED , \NLW_blk00000003_PCOUT<24>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<23>_UNCONNECTED , \NLW_blk00000003_PCOUT<22>_UNCONNECTED , \NLW_blk00000003_PCOUT<21>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<20>_UNCONNECTED , \NLW_blk00000003_PCOUT<19>_UNCONNECTED , \NLW_blk00000003_PCOUT<18>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<17>_UNCONNECTED , \NLW_blk00000003_PCOUT<16>_UNCONNECTED , \NLW_blk00000003_PCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<14>_UNCONNECTED , \NLW_blk00000003_PCOUT<13>_UNCONNECTED , \NLW_blk00000003_PCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<11>_UNCONNECTED , \NLW_blk00000003_PCOUT<10>_UNCONNECTED , \NLW_blk00000003_PCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<8>_UNCONNECTED , \NLW_blk00000003_PCOUT<7>_UNCONNECTED , \NLW_blk00000003_PCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<5>_UNCONNECTED , \NLW_blk00000003_PCOUT<4>_UNCONNECTED , \NLW_blk00000003_PCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<2>_UNCONNECTED , \NLW_blk00000003_PCOUT<1>_UNCONNECTED , \NLW_blk00000003_PCOUT<0>_UNCONNECTED }),
+ .A({b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12]}),
+ .M({\NLW_blk00000003_M<35>_UNCONNECTED , \NLW_blk00000003_M<34>_UNCONNECTED , \NLW_blk00000003_M<33>_UNCONNECTED ,
+\NLW_blk00000003_M<32>_UNCONNECTED , \NLW_blk00000003_M<31>_UNCONNECTED , \NLW_blk00000003_M<30>_UNCONNECTED , \NLW_blk00000003_M<29>_UNCONNECTED ,
+\NLW_blk00000003_M<28>_UNCONNECTED , \NLW_blk00000003_M<27>_UNCONNECTED , \NLW_blk00000003_M<26>_UNCONNECTED , \NLW_blk00000003_M<25>_UNCONNECTED ,
+\NLW_blk00000003_M<24>_UNCONNECTED , \NLW_blk00000003_M<23>_UNCONNECTED , \NLW_blk00000003_M<22>_UNCONNECTED , \NLW_blk00000003_M<21>_UNCONNECTED ,
+\NLW_blk00000003_M<20>_UNCONNECTED , \NLW_blk00000003_M<19>_UNCONNECTED , \NLW_blk00000003_M<18>_UNCONNECTED , \NLW_blk00000003_M<17>_UNCONNECTED ,
+\NLW_blk00000003_M<16>_UNCONNECTED , \NLW_blk00000003_M<15>_UNCONNECTED , \NLW_blk00000003_M<14>_UNCONNECTED , \NLW_blk00000003_M<13>_UNCONNECTED ,
+\NLW_blk00000003_M<12>_UNCONNECTED , \NLW_blk00000003_M<11>_UNCONNECTED , \NLW_blk00000003_M<10>_UNCONNECTED , \NLW_blk00000003_M<9>_UNCONNECTED ,
+\NLW_blk00000003_M<8>_UNCONNECTED , \NLW_blk00000003_M<7>_UNCONNECTED , \NLW_blk00000003_M<6>_UNCONNECTED , \NLW_blk00000003_M<5>_UNCONNECTED ,
+\NLW_blk00000003_M<4>_UNCONNECTED , \NLW_blk00000003_M<3>_UNCONNECTED , \NLW_blk00000003_M<2>_UNCONNECTED , \NLW_blk00000003_M<1>_UNCONNECTED ,
+\NLW_blk00000003_M<0>_UNCONNECTED })
);
// synthesis translate_on
View
6 s13_add.xco
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.2
-# Date: Sat Dec 15 22:37:17 2012
+# Date: Sat Dec 22 20:53:37 2012
#
##############################################################
#
@@ -55,7 +55,7 @@ CSET c_in=false
CSET c_out=false
CSET ce=false
CSET component_name=s13_add
-CSET implementation=Fabric
+CSET implementation=DSP48
CSET latency=0
CSET latency_configuration=Manual
CSET out_width=13
@@ -70,4 +70,4 @@ CSET sync_ctrl_priority=Reset_Overrides_Set
MISC pkg_timestamp=2012-06-22T15:32:25Z
# END Extra information
GENERATE
-# CRC: ac751624
+# CRC: ffbc4aa2
View
2 s13_mult.v
@@ -7,7 +7,7 @@
// \ \ \/ Version: P.28xd
// \ \ Application: netgen
// / / Filename: s13_mult.v
-// /___/ /\ Timestamp: Sat Dec 15 16:41:05 2012
+// /___/ /\ Timestamp: Sat Dec 22 14:55:30 2012
// \ \ / \
// \___\/\___\
//
View
2 s13_mult.xco
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.2
-# Date: Sat Dec 15 22:40:30 2012
+# Date: Sat Dec 22 20:54:55 2012
#
##############################################################
#
View
488 s13_sub.v
@@ -7,7 +7,7 @@
// \ \ \/ Version: P.28xd
// \ \ Application: netgen
// / / Filename: s13_sub.v
-// /___/ /\ Timestamp: Sat Dec 15 16:36:23 2012
+// /___/ /\ Timestamp: Sat Dec 22 14:52:15 2012
// \ \ / \
// \___\/\___\
//
@@ -44,260 +44,240 @@ a, b, s
wire sig00000001;
wire sig00000002;
- wire sig00000003;
- wire sig00000004;
- wire sig00000005;
- wire sig00000006;
- wire sig00000007;
- wire sig00000008;
- wire sig00000009;
- wire sig0000000a;
- wire sig0000000b;
- wire sig0000000c;
- wire sig0000000d;
- wire sig0000000e;
- wire sig0000000f;
- wire sig00000010;
- wire sig00000011;
- wire sig00000012;
- wire sig00000013;
- wire sig00000014;
- wire sig00000015;
- wire sig00000016;
- wire sig00000017;
- wire sig00000018;
- wire sig00000019;
- wire sig0000001a;
+ wire NLW_blk00000003_CARRYOUTF_UNCONNECTED;
+ wire NLW_blk00000003_CARRYOUT_UNCONNECTED;
+ wire \NLW_blk00000003_BCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<0>_UNCONNECTED ;
VCC blk00000001 (
- .P(sig00000001)
- );
- XORCY blk00000002 (
- .CI(sig00000001),
- .LI(sig0000000e),
- .O(s[0])
- );
- XORCY blk00000003 (
- .CI(sig0000000f),
- .LI(sig0000000d),
- .O(s[12])
- );
- XORCY blk00000004 (
- .CI(sig00000010),
- .LI(sig00000002),
- .O(s[11])
- );
- XORCY blk00000005 (
- .CI(sig00000011),
- .LI(sig00000003),
- .O(s[10])
- );
- XORCY blk00000006 (
- .CI(sig00000012),
- .LI(sig00000004),
- .O(s[9])
- );
- XORCY blk00000007 (
- .CI(sig00000013),
- .LI(sig00000005),
- .O(s[8])
- );
- XORCY blk00000008 (
- .CI(sig00000014),
- .LI(sig00000006),
- .O(s[7])
- );
- XORCY blk00000009 (
- .CI(sig00000015),
- .LI(sig00000007),
- .O(s[6])
- );
- XORCY blk0000000a (
- .CI(sig00000016),
- .LI(sig00000008),
- .O(s[5])
- );
- XORCY blk0000000b (
- .CI(sig00000017),
- .LI(sig00000009),
- .O(s[4])
- );
- XORCY blk0000000c (
- .CI(sig00000018),
- .LI(sig0000000a),
- .O(s[3])
- );
- XORCY blk0000000d (
- .CI(sig00000019),
- .LI(sig0000000b),
- .O(s[2])
- );
- XORCY blk0000000e (
- .CI(sig0000001a),
- .LI(sig0000000c),
- .O(s[1])
- );
- MUXCY blk0000000f (
- .CI(sig00000010),
- .DI(a[11]),
- .S(sig00000002),
- .O(sig0000000f)
- );
- MUXCY blk00000010 (
- .CI(sig00000011),
- .DI(a[10]),
- .S(sig00000003),
- .O(sig00000010)
- );
- MUXCY blk00000011 (
- .CI(sig00000012),
- .DI(a[9]),
- .S(sig00000004),
- .O(sig00000011)
- );
- MUXCY blk00000012 (
- .CI(sig00000013),
- .DI(a[8]),
- .S(sig00000005),
- .O(sig00000012)
- );
- MUXCY blk00000013 (
- .CI(sig00000014),
- .DI(a[7]),
- .S(sig00000006),
- .O(sig00000013)
- );
- MUXCY blk00000014 (
- .CI(sig00000015),
- .DI(a[6]),
- .S(sig00000007),
- .O(sig00000014)
- );
- MUXCY blk00000015 (
- .CI(sig00000016),
- .DI(a[5]),
- .S(sig00000008),
- .O(sig00000015)
- );
- MUXCY blk00000016 (
- .CI(sig00000017),
- .DI(a[4]),
- .S(sig00000009),
- .O(sig00000016)
- );
- MUXCY blk00000017 (
- .CI(sig00000018),
- .DI(a[3]),
- .S(sig0000000a),
- .O(sig00000017)
- );
- MUXCY blk00000018 (
- .CI(sig00000019),
- .DI(a[2]),
- .S(sig0000000b),
- .O(sig00000018)
- );
- MUXCY blk00000019 (
- .CI(sig0000001a),
- .DI(a[1]),
- .S(sig0000000c),
- .O(sig00000019)
- );
- MUXCY blk0000001a (
- .CI(sig00000001),
- .DI(a[0]),
- .S(sig0000000e),
- .O(sig0000001a)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk0000001b (
- .I0(a[0]),
- .I1(b[0]),
- .O(sig0000000e)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk0000001c (
- .I0(a[1]),
- .I1(b[1]),
- .O(sig0000000c)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk0000001d (
- .I0(a[2]),
- .I1(b[2]),
- .O(sig0000000b)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk0000001e (
- .I0(a[3]),
- .I1(b[3]),
- .O(sig0000000a)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk0000001f (
- .I0(a[4]),
- .I1(b[4]),
- .O(sig00000009)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk00000020 (
- .I0(a[5]),
- .I1(b[5]),
- .O(sig00000008)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk00000021 (
- .I0(a[6]),
- .I1(b[6]),
- .O(sig00000007)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk00000022 (
- .I0(a[7]),
- .I1(b[7]),
- .O(sig00000006)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk00000023 (
- .I0(a[8]),
- .I1(b[8]),
- .O(sig00000005)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk00000024 (
- .I0(a[9]),
- .I1(b[9]),
- .O(sig00000004)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk00000025 (
- .I0(a[10]),
- .I1(b[10]),
- .O(sig00000003)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk00000026 (
- .I0(a[11]),
- .I1(b[11]),
- .O(sig00000002)
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- blk00000027 (
- .I0(a[12]),
- .I1(b[12]),
- .O(sig0000000d)
+ .P(sig00000002)
+ );
+ GND blk00000002 (
+ .G(sig00000001)
+ );
+ DSP48A1 #(
+ .A0REG ( 0 ),
+ .A1REG ( 0 ),
+ .B0REG ( 0 ),
+ .B1REG ( 0 ),
+ .CARRYINREG ( 0 ),
+ .CARRYINSEL ( "OPMODE5" ),
+ .CREG ( 0 ),
+ .DREG ( 0 ),
+ .MREG ( 0 ),
+ .OPMODEREG ( 0 ),
+ .PREG ( 0 ),
+ .RSTTYPE ( "SYNC" ),
+ .CARRYOUTREG ( 0 ))
+ blk00000003 (
+ .CECARRYIN(sig00000001),
+ .RSTC(sig00000001),
+ .RSTCARRYIN(sig00000001),
+ .CED(sig00000001),
+ .RSTD(sig00000001),
+ .CEOPMODE(sig00000001),
+ .CEC(sig00000001),
+ .CARRYOUTF(NLW_blk00000003_CARRYOUTF_UNCONNECTED),
+ .RSTOPMODE(sig00000001),
+ .RSTM(sig00000001),
+ .CLK(sig00000001),
+ .RSTB(sig00000001),
+ .CEM(sig00000001),
+ .CEB(sig00000001),
+ .CARRYIN(sig00000001),
+ .CEP(sig00000001),
+ .CEA(sig00000001),
+ .CARRYOUT(NLW_blk00000003_CARRYOUT_UNCONNECTED),
+ .RSTA(sig00000001),
+ .RSTP(sig00000001),
+ .B({b[12], b[12], b[12], b[12], b[12], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+ .BCOUT({\NLW_blk00000003_BCOUT<17>_UNCONNECTED , \NLW_blk00000003_BCOUT<16>_UNCONNECTED , \NLW_blk00000003_BCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<14>_UNCONNECTED , \NLW_blk00000003_BCOUT<13>_UNCONNECTED , \NLW_blk00000003_BCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<11>_UNCONNECTED , \NLW_blk00000003_BCOUT<10>_UNCONNECTED , \NLW_blk00000003_BCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<8>_UNCONNECTED , \NLW_blk00000003_BCOUT<7>_UNCONNECTED , \NLW_blk00000003_BCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<5>_UNCONNECTED , \NLW_blk00000003_BCOUT<4>_UNCONNECTED , \NLW_blk00000003_BCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<2>_UNCONNECTED , \NLW_blk00000003_BCOUT<1>_UNCONNECTED , \NLW_blk00000003_BCOUT<0>_UNCONNECTED }),
+ .PCIN({sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001}),
+ .C({a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12],
+a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[12], a[11], a[10], a[9], a[8], a[7], a[6],
+a[5], a[4], a[3], a[2], a[1], a[0]}),
+ .P({\NLW_blk00000003_P<47>_UNCONNECTED , \NLW_blk00000003_P<46>_UNCONNECTED , \NLW_blk00000003_P<45>_UNCONNECTED ,
+\NLW_blk00000003_P<44>_UNCONNECTED , \NLW_blk00000003_P<43>_UNCONNECTED , \NLW_blk00000003_P<42>_UNCONNECTED , \NLW_blk00000003_P<41>_UNCONNECTED ,
+\NLW_blk00000003_P<40>_UNCONNECTED , \NLW_blk00000003_P<39>_UNCONNECTED , \NLW_blk00000003_P<38>_UNCONNECTED , \NLW_blk00000003_P<37>_UNCONNECTED ,
+\NLW_blk00000003_P<36>_UNCONNECTED , \NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED ,
+\NLW_blk00000003_P<32>_UNCONNECTED , \NLW_blk00000003_P<31>_UNCONNECTED , \NLW_blk00000003_P<30>_UNCONNECTED , \NLW_blk00000003_P<29>_UNCONNECTED ,
+\NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED ,
+\NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , \NLW_blk00000003_P<21>_UNCONNECTED ,
+\NLW_blk00000003_P<20>_UNCONNECTED , \NLW_blk00000003_P<19>_UNCONNECTED , \NLW_blk00000003_P<18>_UNCONNECTED , \NLW_blk00000003_P<17>_UNCONNECTED ,
+\NLW_blk00000003_P<16>_UNCONNECTED , \NLW_blk00000003_P<15>_UNCONNECTED , \NLW_blk00000003_P<14>_UNCONNECTED , \NLW_blk00000003_P<13>_UNCONNECTED ,
+s[12], s[11], s[10], s[9], s[8], s[7], s[6], s[5], s[4], s[3], s[2], s[1], s[0]}),
+ .OPMODE({sig00000002, sig00000001, sig00000001, sig00000001, sig00000002, sig00000002, sig00000002, sig00000002}),
+ .D({b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12]}),
+ .PCOUT({\NLW_blk00000003_PCOUT<47>_UNCONNECTED , \NLW_blk00000003_PCOUT<46>_UNCONNECTED , \NLW_blk00000003_PCOUT<45>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<44>_UNCONNECTED , \NLW_blk00000003_PCOUT<43>_UNCONNECTED , \NLW_blk00000003_PCOUT<42>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<41>_UNCONNECTED , \NLW_blk00000003_PCOUT<40>_UNCONNECTED , \NLW_blk00000003_PCOUT<39>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<38>_UNCONNECTED , \NLW_blk00000003_PCOUT<37>_UNCONNECTED , \NLW_blk00000003_PCOUT<36>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<35>_UNCONNECTED , \NLW_blk00000003_PCOUT<34>_UNCONNECTED , \NLW_blk00000003_PCOUT<33>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<32>_UNCONNECTED , \NLW_blk00000003_PCOUT<31>_UNCONNECTED , \NLW_blk00000003_PCOUT<30>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<29>_UNCONNECTED , \NLW_blk00000003_PCOUT<28>_UNCONNECTED , \NLW_blk00000003_PCOUT<27>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<26>_UNCONNECTED , \NLW_blk00000003_PCOUT<25>_UNCONNECTED , \NLW_blk00000003_PCOUT<24>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<23>_UNCONNECTED , \NLW_blk00000003_PCOUT<22>_UNCONNECTED , \NLW_blk00000003_PCOUT<21>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<20>_UNCONNECTED , \NLW_blk00000003_PCOUT<19>_UNCONNECTED , \NLW_blk00000003_PCOUT<18>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<17>_UNCONNECTED , \NLW_blk00000003_PCOUT<16>_UNCONNECTED , \NLW_blk00000003_PCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<14>_UNCONNECTED , \NLW_blk00000003_PCOUT<13>_UNCONNECTED , \NLW_blk00000003_PCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<11>_UNCONNECTED , \NLW_blk00000003_PCOUT<10>_UNCONNECTED , \NLW_blk00000003_PCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<8>_UNCONNECTED , \NLW_blk00000003_PCOUT<7>_UNCONNECTED , \NLW_blk00000003_PCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<5>_UNCONNECTED , \NLW_blk00000003_PCOUT<4>_UNCONNECTED , \NLW_blk00000003_PCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<2>_UNCONNECTED , \NLW_blk00000003_PCOUT<1>_UNCONNECTED , \NLW_blk00000003_PCOUT<0>_UNCONNECTED }),
+ .A({b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12], b[12]}),
+ .M({\NLW_blk00000003_M<35>_UNCONNECTED , \NLW_blk00000003_M<34>_UNCONNECTED , \NLW_blk00000003_M<33>_UNCONNECTED ,
+\NLW_blk00000003_M<32>_UNCONNECTED , \NLW_blk00000003_M<31>_UNCONNECTED , \NLW_blk00000003_M<30>_UNCONNECTED , \NLW_blk00000003_M<29>_UNCONNECTED ,
+\NLW_blk00000003_M<28>_UNCONNECTED , \NLW_blk00000003_M<27>_UNCONNECTED , \NLW_blk00000003_M<26>_UNCONNECTED , \NLW_blk00000003_M<25>_UNCONNECTED ,
+\NLW_blk00000003_M<24>_UNCONNECTED , \NLW_blk00000003_M<23>_UNCONNECTED , \NLW_blk00000003_M<22>_UNCONNECTED , \NLW_blk00000003_M<21>_UNCONNECTED ,
+\NLW_blk00000003_M<20>_UNCONNECTED , \NLW_blk00000003_M<19>_UNCONNECTED , \NLW_blk00000003_M<18>_UNCONNECTED , \NLW_blk00000003_M<17>_UNCONNECTED ,
+\NLW_blk00000003_M<16>_UNCONNECTED , \NLW_blk00000003_M<15>_UNCONNECTED , \NLW_blk00000003_M<14>_UNCONNECTED , \NLW_blk00000003_M<13>_UNCONNECTED ,
+\NLW_blk00000003_M<12>_UNCONNECTED , \NLW_blk00000003_M<11>_UNCONNECTED , \NLW_blk00000003_M<10>_UNCONNECTED , \NLW_blk00000003_M<9>_UNCONNECTED ,
+\NLW_blk00000003_M<8>_UNCONNECTED , \NLW_blk00000003_M<7>_UNCONNECTED , \NLW_blk00000003_M<6>_UNCONNECTED , \NLW_blk00000003_M<5>_UNCONNECTED ,
+\NLW_blk00000003_M<4>_UNCONNECTED , \NLW_blk00000003_M<3>_UNCONNECTED , \NLW_blk00000003_M<2>_UNCONNECTED , \NLW_blk00000003_M<1>_UNCONNECTED ,
+\NLW_blk00000003_M<0>_UNCONNECTED })
);
// synthesis translate_on
View
6 s13_sub.xco
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.2
-# Date: Sat Dec 15 22:35:50 2012
+# Date: Sat Dec 22 20:51:42 2012
#
##############################################################
#
@@ -55,7 +55,7 @@ CSET c_in=false
CSET c_out=false
CSET ce=false
CSET component_name=s13_sub
-CSET implementation=Fabric
+CSET implementation=DSP48
CSET latency=0
CSET latency_configuration=Manual
CSET out_width=13
@@ -70,4 +70,4 @@ CSET sync_ctrl_priority=Reset_Overrides_Set
MISC pkg_timestamp=2012-06-22T15:32:25Z
# END Extra information
GENERATE
-# CRC: f7287b80
+# CRC: 7c7ff31d
View
351 s20_add.v
@@ -0,0 +1,351 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: P.28xd
+// \ \ Application: netgen
+// / / Filename: s20_add.v
+// /___/ /\ Timestamp: Sat Dec 22 15:12:35 2012
+// \ \ / \
+// \___\/\___\
+//
+// Command : -w -sim -ofmt verilog /home/josh/got/kovan-fpga/tmp/_cg/s20_add.ngc /home/josh/got/kovan-fpga/tmp/_cg/s20_add.v
+// Device : 6slx9csg324-2
+// Input file : /home/josh/got/kovan-fpga/tmp/_cg/s20_add.ngc
+// Output file : /home/josh/got/kovan-fpga/tmp/_cg/s20_add.v
+// # of Modules : 1
+// Design Name : s20_add
+// Xilinx : /opt/Xilinx/14.2/ISE_DS/ISE/
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module s20_add (
+a, b, s
+)/* synthesis syn_black_box syn_noprune=1 */;
+ input [19 : 0] a;
+ input [19 : 0] b;
+ output [19 : 0] s;
+
+ // synthesis translate_off
+
+ wire sig00000001;
+ wire sig00000002;
+ wire NLW_blk00000003_CARRYOUTF_UNCONNECTED;
+ wire NLW_blk00000003_CARRYOUT_UNCONNECTED;
+ wire \NLW_blk00000003_BCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<0>_UNCONNECTED ;
+ VCC blk00000001 (
+ .P(sig00000002)
+ );
+ GND blk00000002 (
+ .G(sig00000001)
+ );
+ DSP48A1 #(
+ .A0REG ( 0 ),
+ .A1REG ( 0 ),
+ .B0REG ( 0 ),
+ .B1REG ( 0 ),
+ .CARRYINREG ( 0 ),
+ .CARRYINSEL ( "OPMODE5" ),
+ .CREG ( 0 ),
+ .DREG ( 0 ),
+ .MREG ( 0 ),
+ .OPMODEREG ( 0 ),
+ .PREG ( 0 ),
+ .RSTTYPE ( "SYNC" ),
+ .CARRYOUTREG ( 0 ))
+ blk00000003 (
+ .CECARRYIN(sig00000001),
+ .RSTC(sig00000001),
+ .RSTCARRYIN(sig00000001),
+ .CED(sig00000001),
+ .RSTD(sig00000001),
+ .CEOPMODE(sig00000001),
+ .CEC(sig00000001),
+ .CARRYOUTF(NLW_blk00000003_CARRYOUTF_UNCONNECTED),
+ .RSTOPMODE(sig00000001),
+ .RSTM(sig00000001),
+ .CLK(sig00000001),
+ .RSTB(sig00000001),
+ .CEM(sig00000001),
+ .CEB(sig00000001),
+ .CARRYIN(sig00000001),
+ .CEP(sig00000001),
+ .CEA(sig00000001),
+ .CARRYOUT(NLW_blk00000003_CARRYOUT_UNCONNECTED),
+ .RSTA(sig00000001),
+ .RSTP(sig00000001),
+ .B({b[17], b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+ .BCOUT({\NLW_blk00000003_BCOUT<17>_UNCONNECTED , \NLW_blk00000003_BCOUT<16>_UNCONNECTED , \NLW_blk00000003_BCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<14>_UNCONNECTED , \NLW_blk00000003_BCOUT<13>_UNCONNECTED , \NLW_blk00000003_BCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<11>_UNCONNECTED , \NLW_blk00000003_BCOUT<10>_UNCONNECTED , \NLW_blk00000003_BCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<8>_UNCONNECTED , \NLW_blk00000003_BCOUT<7>_UNCONNECTED , \NLW_blk00000003_BCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<5>_UNCONNECTED , \NLW_blk00000003_BCOUT<4>_UNCONNECTED , \NLW_blk00000003_BCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<2>_UNCONNECTED , \NLW_blk00000003_BCOUT<1>_UNCONNECTED , \NLW_blk00000003_BCOUT<0>_UNCONNECTED }),
+ .PCIN({sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001}),
+ .C({a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19],
+a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[18], a[17], a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6],
+a[5], a[4], a[3], a[2], a[1], a[0]}),
+ .P({\NLW_blk00000003_P<47>_UNCONNECTED , \NLW_blk00000003_P<46>_UNCONNECTED , \NLW_blk00000003_P<45>_UNCONNECTED ,
+\NLW_blk00000003_P<44>_UNCONNECTED , \NLW_blk00000003_P<43>_UNCONNECTED , \NLW_blk00000003_P<42>_UNCONNECTED , \NLW_blk00000003_P<41>_UNCONNECTED ,
+\NLW_blk00000003_P<40>_UNCONNECTED , \NLW_blk00000003_P<39>_UNCONNECTED , \NLW_blk00000003_P<38>_UNCONNECTED , \NLW_blk00000003_P<37>_UNCONNECTED ,
+\NLW_blk00000003_P<36>_UNCONNECTED , \NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED ,
+\NLW_blk00000003_P<32>_UNCONNECTED , \NLW_blk00000003_P<31>_UNCONNECTED , \NLW_blk00000003_P<30>_UNCONNECTED , \NLW_blk00000003_P<29>_UNCONNECTED ,
+\NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED ,
+\NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , \NLW_blk00000003_P<21>_UNCONNECTED ,
+\NLW_blk00000003_P<20>_UNCONNECTED , s[19], s[18], s[17], s[16], s[15], s[14], s[13], s[12], s[11], s[10], s[9], s[8], s[7], s[6], s[5], s[4], s[3],
+s[2], s[1], s[0]}),
+ .OPMODE({sig00000001, sig00000001, sig00000001, sig00000001, sig00000002, sig00000002, sig00000002, sig00000002}),
+ .D({b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19]}),
+ .PCOUT({\NLW_blk00000003_PCOUT<47>_UNCONNECTED , \NLW_blk00000003_PCOUT<46>_UNCONNECTED , \NLW_blk00000003_PCOUT<45>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<44>_UNCONNECTED , \NLW_blk00000003_PCOUT<43>_UNCONNECTED , \NLW_blk00000003_PCOUT<42>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<41>_UNCONNECTED , \NLW_blk00000003_PCOUT<40>_UNCONNECTED , \NLW_blk00000003_PCOUT<39>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<38>_UNCONNECTED , \NLW_blk00000003_PCOUT<37>_UNCONNECTED , \NLW_blk00000003_PCOUT<36>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<35>_UNCONNECTED , \NLW_blk00000003_PCOUT<34>_UNCONNECTED , \NLW_blk00000003_PCOUT<33>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<32>_UNCONNECTED , \NLW_blk00000003_PCOUT<31>_UNCONNECTED , \NLW_blk00000003_PCOUT<30>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<29>_UNCONNECTED , \NLW_blk00000003_PCOUT<28>_UNCONNECTED , \NLW_blk00000003_PCOUT<27>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<26>_UNCONNECTED , \NLW_blk00000003_PCOUT<25>_UNCONNECTED , \NLW_blk00000003_PCOUT<24>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<23>_UNCONNECTED , \NLW_blk00000003_PCOUT<22>_UNCONNECTED , \NLW_blk00000003_PCOUT<21>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<20>_UNCONNECTED , \NLW_blk00000003_PCOUT<19>_UNCONNECTED , \NLW_blk00000003_PCOUT<18>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<17>_UNCONNECTED , \NLW_blk00000003_PCOUT<16>_UNCONNECTED , \NLW_blk00000003_PCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<14>_UNCONNECTED , \NLW_blk00000003_PCOUT<13>_UNCONNECTED , \NLW_blk00000003_PCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<11>_UNCONNECTED , \NLW_blk00000003_PCOUT<10>_UNCONNECTED , \NLW_blk00000003_PCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<8>_UNCONNECTED , \NLW_blk00000003_PCOUT<7>_UNCONNECTED , \NLW_blk00000003_PCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<5>_UNCONNECTED , \NLW_blk00000003_PCOUT<4>_UNCONNECTED , \NLW_blk00000003_PCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<2>_UNCONNECTED , \NLW_blk00000003_PCOUT<1>_UNCONNECTED , \NLW_blk00000003_PCOUT<0>_UNCONNECTED }),
+ .A({b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[18]}),
+ .M({\NLW_blk00000003_M<35>_UNCONNECTED , \NLW_blk00000003_M<34>_UNCONNECTED , \NLW_blk00000003_M<33>_UNCONNECTED ,
+\NLW_blk00000003_M<32>_UNCONNECTED , \NLW_blk00000003_M<31>_UNCONNECTED , \NLW_blk00000003_M<30>_UNCONNECTED , \NLW_blk00000003_M<29>_UNCONNECTED ,
+\NLW_blk00000003_M<28>_UNCONNECTED , \NLW_blk00000003_M<27>_UNCONNECTED , \NLW_blk00000003_M<26>_UNCONNECTED , \NLW_blk00000003_M<25>_UNCONNECTED ,
+\NLW_blk00000003_M<24>_UNCONNECTED , \NLW_blk00000003_M<23>_UNCONNECTED , \NLW_blk00000003_M<22>_UNCONNECTED , \NLW_blk00000003_M<21>_UNCONNECTED ,
+\NLW_blk00000003_M<20>_UNCONNECTED , \NLW_blk00000003_M<19>_UNCONNECTED , \NLW_blk00000003_M<18>_UNCONNECTED , \NLW_blk00000003_M<17>_UNCONNECTED ,
+\NLW_blk00000003_M<16>_UNCONNECTED , \NLW_blk00000003_M<15>_UNCONNECTED , \NLW_blk00000003_M<14>_UNCONNECTED , \NLW_blk00000003_M<13>_UNCONNECTED ,
+\NLW_blk00000003_M<12>_UNCONNECTED , \NLW_blk00000003_M<11>_UNCONNECTED , \NLW_blk00000003_M<10>_UNCONNECTED , \NLW_blk00000003_M<9>_UNCONNECTED ,
+\NLW_blk00000003_M<8>_UNCONNECTED , \NLW_blk00000003_M<7>_UNCONNECTED , \NLW_blk00000003_M<6>_UNCONNECTED , \NLW_blk00000003_M<5>_UNCONNECTED ,
+\NLW_blk00000003_M<4>_UNCONNECTED , \NLW_blk00000003_M<3>_UNCONNECTED , \NLW_blk00000003_M<2>_UNCONNECTED , \NLW_blk00000003_M<1>_UNCONNECTED ,
+\NLW_blk00000003_M<0>_UNCONNECTED })
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
View
73 s20_add.xco
@@ -0,0 +1,73 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.2
+# Date: Sat Dec 22 21:12:03 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:c_addsub:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0
+# END Select
+# BEGIN Parameters
+CSET a_type=Signed
+CSET a_width=20
+CSET add_mode=Add
+CSET ainit_value=0
+CSET b_constant=false
+CSET b_type=Signed
+CSET b_value=00000000000000000000
+CSET b_width=20
+CSET borrow_sense=Active_Low
+CSET bypass=false
+CSET bypass_ce_priority=CE_Overrides_Bypass
+CSET bypass_sense=Active_High
+CSET c_in=false
+CSET c_out=false
+CSET ce=false
+CSET component_name=s20_add
+CSET implementation=DSP48
+CSET latency=0
+CSET latency_configuration=Manual
+CSET out_width=20
+CSET sclr=false
+CSET sinit=false
+CSET sinit_value=0
+CSET sset=false
+CSET sync_ce_priority=Sync_Overrides_CE
+CSET sync_ctrl_priority=Reset_Overrides_Set
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-06-22T15:32:25Z
+# END Extra information
+GENERATE
+# CRC: a5c14bd6
View
351 s20_sub.v
@@ -0,0 +1,351 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: P.28xd
+// \ \ Application: netgen
+// / / Filename: s20_sub.v
+// /___/ /\ Timestamp: Sat Dec 22 15:14:04 2012
+// \ \ / \
+// \___\/\___\
+//
+// Command : -w -sim -ofmt verilog /home/josh/got/kovan-fpga/tmp/_cg/s20_sub.ngc /home/josh/got/kovan-fpga/tmp/_cg/s20_sub.v
+// Device : 6slx9csg324-2
+// Input file : /home/josh/got/kovan-fpga/tmp/_cg/s20_sub.ngc
+// Output file : /home/josh/got/kovan-fpga/tmp/_cg/s20_sub.v
+// # of Modules : 1
+// Design Name : s20_sub
+// Xilinx : /opt/Xilinx/14.2/ISE_DS/ISE/
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module s20_sub (
+a, b, s
+)/* synthesis syn_black_box syn_noprune=1 */;
+ input [19 : 0] a;
+ input [19 : 0] b;
+ output [19 : 0] s;
+
+ // synthesis translate_off
+
+ wire sig00000001;
+ wire sig00000002;
+ wire NLW_blk00000003_CARRYOUTF_UNCONNECTED;
+ wire NLW_blk00000003_CARRYOUT_UNCONNECTED;
+ wire \NLW_blk00000003_BCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_BCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_P<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<47>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<46>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<45>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<44>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<43>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<42>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<41>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<40>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<39>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<38>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<37>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<36>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_PCOUT<0>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<35>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<34>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<33>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<32>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<31>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<30>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<29>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<28>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<27>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<26>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<25>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<24>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<23>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<22>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<21>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<20>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<19>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<18>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<17>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<16>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<15>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<14>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<13>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<12>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<11>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<10>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<9>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<8>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<7>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<6>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<5>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<4>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<3>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<2>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<1>_UNCONNECTED ;
+ wire \NLW_blk00000003_M<0>_UNCONNECTED ;
+ VCC blk00000001 (
+ .P(sig00000002)
+ );
+ GND blk00000002 (
+ .G(sig00000001)
+ );
+ DSP48A1 #(
+ .A0REG ( 0 ),
+ .A1REG ( 0 ),
+ .B0REG ( 0 ),
+ .B1REG ( 0 ),
+ .CARRYINREG ( 0 ),
+ .CARRYINSEL ( "OPMODE5" ),
+ .CREG ( 0 ),
+ .DREG ( 0 ),
+ .MREG ( 0 ),
+ .OPMODEREG ( 0 ),
+ .PREG ( 0 ),
+ .RSTTYPE ( "SYNC" ),
+ .CARRYOUTREG ( 0 ))
+ blk00000003 (
+ .CECARRYIN(sig00000001),
+ .RSTC(sig00000001),
+ .RSTCARRYIN(sig00000001),
+ .CED(sig00000001),
+ .RSTD(sig00000001),
+ .CEOPMODE(sig00000001),
+ .CEC(sig00000001),
+ .CARRYOUTF(NLW_blk00000003_CARRYOUTF_UNCONNECTED),
+ .RSTOPMODE(sig00000001),
+ .RSTM(sig00000001),
+ .CLK(sig00000001),
+ .RSTB(sig00000001),
+ .CEM(sig00000001),
+ .CEB(sig00000001),
+ .CARRYIN(sig00000001),
+ .CEP(sig00000001),
+ .CEA(sig00000001),
+ .CARRYOUT(NLW_blk00000003_CARRYOUT_UNCONNECTED),
+ .RSTA(sig00000001),
+ .RSTP(sig00000001),
+ .B({b[17], b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
+ .BCOUT({\NLW_blk00000003_BCOUT<17>_UNCONNECTED , \NLW_blk00000003_BCOUT<16>_UNCONNECTED , \NLW_blk00000003_BCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<14>_UNCONNECTED , \NLW_blk00000003_BCOUT<13>_UNCONNECTED , \NLW_blk00000003_BCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<11>_UNCONNECTED , \NLW_blk00000003_BCOUT<10>_UNCONNECTED , \NLW_blk00000003_BCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<8>_UNCONNECTED , \NLW_blk00000003_BCOUT<7>_UNCONNECTED , \NLW_blk00000003_BCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<5>_UNCONNECTED , \NLW_blk00000003_BCOUT<4>_UNCONNECTED , \NLW_blk00000003_BCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_BCOUT<2>_UNCONNECTED , \NLW_blk00000003_BCOUT<1>_UNCONNECTED , \NLW_blk00000003_BCOUT<0>_UNCONNECTED }),
+ .PCIN({sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001, sig00000001,
+sig00000001, sig00000001, sig00000001, sig00000001, sig00000001}),
+ .C({a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19],
+a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[19], a[18], a[17], a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6],
+a[5], a[4], a[3], a[2], a[1], a[0]}),
+ .P({\NLW_blk00000003_P<47>_UNCONNECTED , \NLW_blk00000003_P<46>_UNCONNECTED , \NLW_blk00000003_P<45>_UNCONNECTED ,
+\NLW_blk00000003_P<44>_UNCONNECTED , \NLW_blk00000003_P<43>_UNCONNECTED , \NLW_blk00000003_P<42>_UNCONNECTED , \NLW_blk00000003_P<41>_UNCONNECTED ,
+\NLW_blk00000003_P<40>_UNCONNECTED , \NLW_blk00000003_P<39>_UNCONNECTED , \NLW_blk00000003_P<38>_UNCONNECTED , \NLW_blk00000003_P<37>_UNCONNECTED ,
+\NLW_blk00000003_P<36>_UNCONNECTED , \NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED ,
+\NLW_blk00000003_P<32>_UNCONNECTED , \NLW_blk00000003_P<31>_UNCONNECTED , \NLW_blk00000003_P<30>_UNCONNECTED , \NLW_blk00000003_P<29>_UNCONNECTED ,
+\NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED ,
+\NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , \NLW_blk00000003_P<21>_UNCONNECTED ,
+\NLW_blk00000003_P<20>_UNCONNECTED , s[19], s[18], s[17], s[16], s[15], s[14], s[13], s[12], s[11], s[10], s[9], s[8], s[7], s[6], s[5], s[4], s[3],
+s[2], s[1], s[0]}),
+ .OPMODE({sig00000002, sig00000001, sig00000001, sig00000001, sig00000002, sig00000002, sig00000002, sig00000002}),
+ .D({b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19]}),
+ .PCOUT({\NLW_blk00000003_PCOUT<47>_UNCONNECTED , \NLW_blk00000003_PCOUT<46>_UNCONNECTED , \NLW_blk00000003_PCOUT<45>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<44>_UNCONNECTED , \NLW_blk00000003_PCOUT<43>_UNCONNECTED , \NLW_blk00000003_PCOUT<42>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<41>_UNCONNECTED , \NLW_blk00000003_PCOUT<40>_UNCONNECTED , \NLW_blk00000003_PCOUT<39>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<38>_UNCONNECTED , \NLW_blk00000003_PCOUT<37>_UNCONNECTED , \NLW_blk00000003_PCOUT<36>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<35>_UNCONNECTED , \NLW_blk00000003_PCOUT<34>_UNCONNECTED , \NLW_blk00000003_PCOUT<33>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<32>_UNCONNECTED , \NLW_blk00000003_PCOUT<31>_UNCONNECTED , \NLW_blk00000003_PCOUT<30>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<29>_UNCONNECTED , \NLW_blk00000003_PCOUT<28>_UNCONNECTED , \NLW_blk00000003_PCOUT<27>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<26>_UNCONNECTED , \NLW_blk00000003_PCOUT<25>_UNCONNECTED , \NLW_blk00000003_PCOUT<24>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<23>_UNCONNECTED , \NLW_blk00000003_PCOUT<22>_UNCONNECTED , \NLW_blk00000003_PCOUT<21>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<20>_UNCONNECTED , \NLW_blk00000003_PCOUT<19>_UNCONNECTED , \NLW_blk00000003_PCOUT<18>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<17>_UNCONNECTED , \NLW_blk00000003_PCOUT<16>_UNCONNECTED , \NLW_blk00000003_PCOUT<15>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<14>_UNCONNECTED , \NLW_blk00000003_PCOUT<13>_UNCONNECTED , \NLW_blk00000003_PCOUT<12>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<11>_UNCONNECTED , \NLW_blk00000003_PCOUT<10>_UNCONNECTED , \NLW_blk00000003_PCOUT<9>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<8>_UNCONNECTED , \NLW_blk00000003_PCOUT<7>_UNCONNECTED , \NLW_blk00000003_PCOUT<6>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<5>_UNCONNECTED , \NLW_blk00000003_PCOUT<4>_UNCONNECTED , \NLW_blk00000003_PCOUT<3>_UNCONNECTED ,
+\NLW_blk00000003_PCOUT<2>_UNCONNECTED , \NLW_blk00000003_PCOUT<1>_UNCONNECTED , \NLW_blk00000003_PCOUT<0>_UNCONNECTED }),
+ .A({b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[19], b[18]}),
+ .M({\NLW_blk00000003_M<35>_UNCONNECTED , \NLW_blk00000003_M<34>_UNCONNECTED , \NLW_blk00000003_M<33>_UNCONNECTED ,
+\NLW_blk00000003_M<32>_UNCONNECTED , \NLW_blk00000003_M<31>_UNCONNECTED , \NLW_blk00000003_M<30>_UNCONNECTED , \NLW_blk00000003_M<29>_UNCONNECTED ,
+\NLW_blk00000003_M<28>_UNCONNECTED , \NLW_blk00000003_M<27>_UNCONNECTED , \NLW_blk00000003_M<26>_UNCONNECTED , \NLW_blk00000003_M<25>_UNCONNECTED ,
+\NLW_blk00000003_M<24>_UNCONNECTED , \NLW_blk00000003_M<23>_UNCONNECTED , \NLW_blk00000003_M<22>_UNCONNECTED , \NLW_blk00000003_M<21>_UNCONNECTED ,
+\NLW_blk00000003_M<20>_UNCONNECTED , \NLW_blk00000003_M<19>_UNCONNECTED , \NLW_blk00000003_M<18>_UNCONNECTED , \NLW_blk00000003_M<17>_UNCONNECTED ,
+\NLW_blk00000003_M<16>_UNCONNECTED , \NLW_blk00000003_M<15>_UNCONNECTED , \NLW_blk00000003_M<14>_UNCONNECTED , \NLW_blk00000003_M<13>_UNCONNECTED ,
+\NLW_blk00000003_M<12>_UNCONNECTED , \NLW_blk00000003_M<11>_UNCONNECTED , \NLW_blk00000003_M<10>_UNCONNECTED , \NLW_blk00000003_M<9>_UNCONNECTED ,
+\NLW_blk00000003_M<8>_UNCONNECTED , \NLW_blk00000003_M<7>_UNCONNECTED , \NLW_blk00000003_M<6>_UNCONNECTED , \NLW_blk00000003_M<5>_UNCONNECTED ,
+\NLW_blk00000003_M<4>_UNCONNECTED , \NLW_blk00000003_M<3>_UNCONNECTED , \NLW_blk00000003_M<2>_UNCONNECTED , \NLW_blk00000003_M<1>_UNCONNECTED ,
+\NLW_blk00000003_M<0>_UNCONNECTED })
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
View
73 s20_sub.xco
@@ -0,0 +1,73 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.2
+# Date: Sat Dec 22 21:13:32 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:c_addsub:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0
+# END Select
+# BEGIN Parameters
+CSET a_type=Signed
+CSET a_width=20
+CSET add_mode=Subtract
+CSET ainit_value=0
+CSET b_constant=false
+CSET b_type=Signed
+CSET b_value=00000000000000000000
+CSET b_width=20
+CSET borrow_sense=Active_Low
+CSET bypass=false
+CSET bypass_ce_priority=CE_Overrides_Bypass
+CSET bypass_sense=Active_High
+CSET c_in=false