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simple uart receiver

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kmod committed Jul 20, 2013
1 parent 4880b06 commit 5858907b3d553f65e05e75cacb765335e8998bc1
Showing with 59 additions and 9 deletions.
  1. +21 −7 fpga.v
  2. +5 −1 src/uart.py
  3. +33 −1 src/util.v
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28 fpga.v
@@ -51,17 +51,11 @@ module fpga(
reg [15:0] ctr;
reg [4:0] btn_prev;
always @(posedge clk) begin
if (btn_debounced[0] && !btn_prev[0]) ctr <= ctr + 1'b1;
if (btn_debounced[2] && !btn_prev[2]) ctr <= 0;
btn_prev <= btn_debounced;
end
sseg #(.N(16)) sseg(.clk(clk), .in(ctr), .c(seg), .an(an));
wire [7:0] uart_tx_data;
reg [7:0] uart_tx_data = 8'd65;
assign uart_tx_data = 8'd65;
wire uart_tx_req, uart_tx_ready;
assign uart_tx_req = (btn_debounced[3] && !btn_prev[3]);
@@ -71,4 +65,24 @@ module fpga(
115,200: 87 cycles
*/
uart_tranceiver #(.CLK_CYCLES(87)) uart_tx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .ready(uart_tx_ready), .uart_tx(RsTx));
// Input synchronizer:
reg RsRx1=1, RsRx2=1;
always @(posedge clk) begin
{RsRx1, RsRx2} <= {RsRx, RsRx1};
end
wire [7:0] uart_rx_data;
wire uart_received;
uart_receiver #(.CLK_CYCLES(87)) uart_rx(.clk(clk), .data(uart_rx_data), .received(uart_received), .uart_rx(RsRx2));
always @(posedge clk) begin
if (btn_debounced[0] && !btn_prev[0]) ctr <= ctr + 1'b1;
if (btn_debounced[2] && !btn_prev[2]) ctr <= 0;
if (uart_received) begin
ctr <= {ctr[7:0], uart_rx_data};
end
btn_prev <= btn_debounced;
end
endmodule
View
@@ -2,7 +2,7 @@
# Baud rates linux seems to support:
# 0 50 75 110 134 150 200 300 600 1200 1800 2400 4800 9600 19200 38400 57600 115200 230400 460800 576000 921600 1152000 1500000 3000000
# 0 50 75 110 134 150 200 300 600 1200 1800 2400 4800 9600 19200 38400 57600 115200 230400 460800 576000 921600 1152000 1500000 3000000...
def test(br):
ser = serial.Serial("/dev/ttyUSB0", br, timeout=.1)
try:
@@ -20,7 +20,11 @@ def test(br):
ser = serial.Serial("/dev/ttyUSB0", 115200, timeout=1)
print ser.portstr
ser.write("hello")
i = 0
while True:
c = ser.read(1)
ser.write(chr(i&0xff))
i += 1
print repr(c)
ser.write(c)
View
@@ -143,7 +143,7 @@ module uart_tranceiver #(parameter CLK_CYCLES=4167, CTR_WIDTH=16)
assign ready = (bits_left == 0);
always @(posedge clk) begin
ctr <= ctr + 1;
ctr <= ctr + 1'b1;
if (ctr == (CLK_CYCLES-1)) begin
ctr <= 0;
@@ -162,3 +162,35 @@ module uart_tranceiver #(parameter CLK_CYCLES=4167, CTR_WIDTH=16)
end
end
endmodule
module uart_receiver #(parameter CLK_CYCLES=4178, CTR_WIDTH=16)
(input wire clk, output reg [7:0] data, output reg received, input wire uart_rx);
reg [CTR_WIDTH-1:0] ctr = CLK_CYCLES;
reg [4:0] bits_left = 0;
reg receiving = 0;
always @(posedge clk) begin
ctr <= ctr - 1'b1;
received <= 0;
if (ctr == 0) begin
ctr <= (CLK_CYCLES-1);
data <= {uart_rx, data[7:1]};
bits_left <= bits_left - 1'b1;
if (receiving && (bits_left == 1)) begin
received <= 1;
end
if (bits_left == 0) begin
receiving <= 0;
end
end
if (uart_rx == 0 && !receiving) begin
ctr <= (CLK_CYCLES-1 + CLK_CYCLES / 2); // try to sample in the middle of the bit, to maximize clk rate flexibility. wait an additional CLK_CYCLES to skip the rest of the start bit
bits_left <= 4'd8;
receiving <= 1;
end
end
endmodule

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