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simple multibyte transmitter

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kmod committed Jul 21, 2013
1 parent 5858907 commit 90334f2b3d4826f3e692340b9dadb04fbb2a6c14
Showing with 48 additions and 5 deletions.
  1. +3 −3 fpga.v
  2. +6 −0 processor.xise
  3. +39 −2 src/util.v
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6 fpga.v
@@ -55,16 +55,16 @@ module fpga(
sseg #(.N(16)) sseg(.clk(clk), .in(ctr), .c(seg), .an(an));
reg [7:0] uart_tx_data = 8'd65;
assign uart_tx_data = 8'd65;
reg [127:0] uart_tx_data = 128'h2d2d2d2d2d646c726f77206f6c6c6568; // "hello world-----" with 'h' as the LSB
wire uart_tx_req, uart_tx_ready;
assign uart_tx_req = (btn_debounced[3] && !btn_prev[3]);
/*
Baud rates:
@10MHz:
115,200: 87 cycles
*/
uart_tranceiver #(.CLK_CYCLES(87)) uart_tx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .ready(uart_tx_ready), .uart_tx(RsTx));
//uart_transmitter #(.CLK_CYCLES(87)) uart_tx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .ready(uart_tx_ready), .uart_tx(RsTx));
uart_multibyte_transmitter #(.CLK_CYCLES(87), .MSG_LOG_WIDTH(4)) uart_mbtx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .uart_tx(RsTx));
// Input synchronizer:
reg RsRx1=1, RsRx2=1;
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@@ -30,6 +30,12 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="test/uart_multibyte_tx.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="ipcore_dir/dcm.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
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@@ -126,7 +126,7 @@ module debounce_unopt #(parameter N=100000) (
endmodule
module uart_tranceiver #(parameter CLK_CYCLES=4167, CTR_WIDTH=16)
module uart_transmitter #(parameter CLK_CYCLES=4167, CTR_WIDTH=16)
(input wire clk, input wire [7:0] data, input wire req, output wire ready, output wire uart_tx);
reg [CTR_WIDTH-1:0] ctr;
@@ -155,14 +155,51 @@ module uart_tranceiver #(parameter CLK_CYCLES=4167, CTR_WIDTH=16)
bits_left <= bits_left - 1'b1;
end
if (req) begin
if (req && ready) begin
line_data <= {1'b1, data, 1'b0};
ctr <= 0;
bits_left <= 4'd10;
end
end
endmodule
module uart_multibyte_transmitter #(parameter CLK_CYCLES=4167, CTR_WIDTH=16, MSG_LOG_WIDTH=3)
(input wire clk, input wire [8*(2**MSG_LOG_WIDTH)-1:0] data, input wire req, output wire uart_tx);
reg [8*(2**MSG_LOG_WIDTH)-1:0] cur_data;
reg [MSG_LOG_WIDTH-1:0] byte_idx;
reg busy = 1'b0;
wire [7:0] cur_byte;
genvar idx;
generate
for (idx=0; idx<8; idx=idx+1) begin: byte_sel
assign cur_byte[idx] = cur_data[8*byte_idx+idx];
end
endgenerate
//assign cur_byte = cur_data[8*byte_idx+7:8*byte_idx];
wire tx_ready;
uart_transmitter #(.CLK_CYCLES(CLK_CYCLES), .CTR_WIDTH(CTR_WIDTH)) uart_txr(.clk(clk), .data(cur_byte), .req(busy), .ready(tx_ready), .uart_tx(uart_tx));
wire [MSG_LOG_WIDTH-1:0] next_byte_idx;
assign next_byte_idx = byte_idx + 1;
always @(posedge clk) begin
if (!busy && req) begin
busy <= 1;
cur_data <= data;
byte_idx <= 0;
end
else if (busy && tx_ready) begin
byte_idx <= next_byte_idx;
if (next_byte_idx == 0) begin
busy <= 0;
end
end
end
endmodule
module uart_receiver #(parameter CLK_CYCLES=4178, CTR_WIDTH=16)
(input wire clk, output reg [7:0] data, output reg received, input wire uart_rx);
reg [CTR_WIDTH-1:0] ctr = CLK_CYCLES;

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