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initial uart serial communication (just board->pc right now)

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kmod committed Jul 20, 2013
1 parent 2ad9a1a commit b8881f16542740b3a8967a0d552478da4872ff81
Showing with 92 additions and 341 deletions.
  1. +1 −0 .gitignore
  2. +2 −2 Nexys3_Master.ucf
  3. +15 −1 fpga.v
  4. +4 −333 ipcore_dir/dcm.xise
  5. +5 −5 processor.xise
  6. +26 −0 src/uart.py
  7. +39 −0 src/util.v
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@@ -1,5 +1,6 @@
*
!*.v
!*.py
!*.ucf
!.gitignore
!*.xise
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@@ -247,8 +247,8 @@ NET "btn<4>" LOC = "D9" | IOSTANDARD = "LVCMOS33"; #Bank = 0, Pin nam
## Usb-RS232 interface
#NET "RsRx" LOC = "N17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L48P_HDC_M1DQ8, Sch name = MCU-RX
#NET "RsTx" LOC = "N18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L48N_M1DQ9, Sch name = MCU-TX
NET "RsRx" LOC = "N17" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L48P_HDC_M1DQ8, Sch name = MCU-RX
NET "RsTx" LOC = "N18" | IOSTANDARD = "LVCMOS33"; #Bank = 1, Pin name = IO_L48N_M1DQ9, Sch name = MCU-TX
## VHDCI Connector
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16 fpga.v
@@ -25,7 +25,9 @@ module fpga(
input wire [4:0] btn,
output wire [7:0] led,
output wire [7:0] seg,
output wire [3:0] an
output wire [3:0] an,
output wire RsTx,
input wire RsRx
);
wire clk; // 10MHz clock
@@ -57,4 +59,16 @@ module fpga(
end
sseg #(.N(16)) sseg(.clk(clk), .in(ctr), .c(seg), .an(an));
wire [7:0] uart_tx_data;
assign uart_tx_data = 8'd65;
wire uart_tx_req, uart_tx_ready;
assign uart_tx_req = (btn_debounced[3] && !btn_prev[3]);
/*
Baud rates:
@10MHz:
115,200: 87 cycles
*/
uart_tranceiver #(.CLK_CYCLES(87)) uart_tx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .ready(uart_tx_ready), .uart_tx(RsTx));
endmodule
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@@ -339,7 +339,7 @@
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
@@ -353,10 +353,10 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="YYYY-MM-DDTHH:MM:SS" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnableToCalculate" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Unknown" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-07-20T12:38:25" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6B251AF0B2014E6596D24722C18DB83E" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
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@@ -0,0 +1,26 @@
import serial # easy_install pyserial
# Baud rates linux seems to support:
# 0 50 75 110 134 150 200 300 600 1200 1800 2400 4800 9600 19200 38400 57600 115200 230400 460800 576000 921600 1152000 1500000 3000000
def test(br):
ser = serial.Serial("/dev/ttyUSB0", br, timeout=.1)
try:
ser.read(1)
except serial.serialutil.SerialException:
return False
finally:
ser.close()
return True
# for i in xrange(0, 10000000, 1200):
# if test(i):
# print i
ser = serial.Serial("/dev/ttyUSB0", 115200, timeout=1)
print ser.portstr
ser.write("hello")
while True:
c = ser.read(1)
print repr(c)
ser.write(c)
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@@ -124,3 +124,42 @@ module debounce_unopt #(parameter N=100000) (
out <= _o;
end
endmodule
module uart_tranceiver #(parameter CLK_CYCLES=4167, CTR_WIDTH=16)
(input wire clk, input wire [7:0] data, input wire req, output wire ready, output wire uart_tx);
reg [CTR_WIDTH-1:0] ctr;
reg [4:0] bit_idx;
reg [9:0] line_data;
reg sending;
initial begin
sending = 0;
ctr = 0;
end;
assign uart_tx = sending ? line_data[bit_idx] : 1'b1;
always @(posedge clk) begin
ctr <= ctr + 1;
if (ctr == (CLK_CYCLES-1)) begin
ctr <= 0;
if (bit_idx == 9) begin
sending <= 0;
end
bit_idx <= bit_idx + 1;
end
if (req && !sending) begin
line_data <= {1'b1, data, 1'b0};
bit_idx <= 0;
sending <= 1;
ctr <= 0;
end
end
endmodule

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