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simple multibyte receiver

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kmod committed Jul 21, 2013
1 parent 90334f2 commit f8c2d43ced41cef3ca1345ab69cf82cfbcbcc616
Showing with 60 additions and 16 deletions.
  1. +15 −11 fpga.v
  2. +16 −4 src/uart.py
  3. +29 −1 src/util.v
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26 fpga.v
@@ -33,7 +33,7 @@ module fpga(
wire clk; // 10MHz clock
dcm dcm(.CLK_IN(input_clk), .CLK_OUT(clk)); // 100MHz -> 10MHz DCM
assign led = sw;
//assign led = sw;
// button synchronizer:
reg [4:0] btn_sync, btn_sync2;
@@ -55,32 +55,36 @@ module fpga(
sseg #(.N(16)) sseg(.clk(clk), .in(ctr), .c(seg), .an(an));
reg [127:0] uart_tx_data = 128'h2d2d2d2d2d646c726f77206f6c6c6568; // "hello world-----" with 'h' as the LSB
wire uart_tx_req, uart_tx_ready;
assign uart_tx_req = (btn_debounced[3] && !btn_prev[3]);
/*
Baud rates:
@10MHz:
115,200: 87 cycles
*/
//uart_transmitter #(.CLK_CYCLES(87)) uart_tx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .ready(uart_tx_ready), .uart_tx(RsTx));
uart_multibyte_transmitter #(.CLK_CYCLES(87), .MSG_LOG_WIDTH(4)) uart_mbtx(.clk(clk), .data(uart_tx_data), .req(uart_tx_req), .uart_tx(RsTx));
wire uart_tx_req, uart_tx_ready;
wire [31:0] uart_rx_data;
wire uart_rx_valid;
assign uart_tx_req = uart_rx_valid;
uart_multibyte_transmitter #(.CLK_CYCLES(87), .MSG_LOG_WIDTH(2)) uart_mbtx(.clk(clk), .data(uart_rx_data), .req(uart_tx_req), .uart_tx(RsTx));
// Input synchronizer:
reg RsRx1=1, RsRx2=1;
always @(posedge clk) begin
{RsRx1, RsRx2} <= {RsRx, RsRx1};
end
wire [7:0] uart_rx_data;
wire uart_received;
uart_receiver #(.CLK_CYCLES(87)) uart_rx(.clk(clk), .data(uart_rx_data), .received(uart_received), .uart_rx(RsRx2));
uart_multibyte_receiver #(.CLK_CYCLES(87), .MSG_LOG_WIDTH(2)) uart_mbrx(.clk(clk), .data(uart_rx_data), .valid(uart_rx_valid), .ack(1'b1), .uart_rx(RsRx2));
always @(posedge clk) begin
if (btn_debounced[0] && !btn_prev[0]) ctr <= ctr + 1'b1;
if (btn_debounced[2] && !btn_prev[2]) ctr <= 0;
if (uart_received) begin
ctr <= {ctr[7:0], uart_rx_data};
if (uart_rx_valid) begin
ctr <= uart_rx_data[15:0];
end
btn_prev <= btn_debounced;
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@@ -1,3 +1,6 @@
import threading
import time
import serial # easy_install pyserial
@@ -17,14 +20,23 @@ def test(br):
# if test(i):
# print i
ser = serial.Serial("/dev/ttyUSB0", 115200, timeout=1)
ser = serial.Serial("/dev/ttyUSB0", 115200, timeout=4)
print ser.portstr
ser.write("hello")
def read_thread():
while True:
c = ser.read(1)
print "R", repr(c)
t = threading.Thread(target=read_thread)
t.setDaemon(True)
t.start()
i = 0
while True:
c = ser.read(1)
time.sleep(1)
print "W", repr(chr(i&0xff))
ser.write(chr(i&0xff))
i += 1
print repr(c)
ser.write(c)
# ser.write(c)
View
@@ -183,7 +183,7 @@ module uart_multibyte_transmitter #(parameter CLK_CYCLES=4167, CTR_WIDTH=16, MSG
uart_transmitter #(.CLK_CYCLES(CLK_CYCLES), .CTR_WIDTH(CTR_WIDTH)) uart_txr(.clk(clk), .data(cur_byte), .req(busy), .ready(tx_ready), .uart_tx(uart_tx));
wire [MSG_LOG_WIDTH-1:0] next_byte_idx;
assign next_byte_idx = byte_idx + 1;
assign next_byte_idx = byte_idx + 1'b1;
always @(posedge clk) begin
if (!busy && req) begin
@@ -231,3 +231,31 @@ module uart_receiver #(parameter CLK_CYCLES=4178, CTR_WIDTH=16)
end
end
endmodule
module uart_multibyte_receiver #(parameter CLK_CYCLES=4178, CTR_WIDTH=16, MSG_LOG_WIDTH=3)
(input wire clk, output reg [8*(2**MSG_LOG_WIDTH)-1:0] data, output reg valid, input wire ack, input wire uart_rx, output wire [7:0] led);
reg [MSG_LOG_WIDTH-1:0] byte_idx;
wire [MSG_LOG_WIDTH-1:0] next_byte_idx;
assign next_byte_idx = byte_idx + 1'b1;
reg [8*(2**MSG_LOG_WIDTH)-1:0] buffer;
wire [8*(2**MSG_LOG_WIDTH)-1:0] next_buffer;
assign next_buffer = {recvd_byte, buffer[8*(2**MSG_LOG_WIDTH)-1:8]};
wire [7:0] recvd_byte;
wire recvd_valid;
uart_receiver #(.CLK_CYCLES(CLK_CYCLES)) uart_rvr(.clk(clk), .data(recvd_byte), .received(recvd_valid), .uart_rx(uart_rx));
always @(posedge clk) begin
if (ack) valid <= 1'b0;
if (recvd_valid) begin
buffer <= next_buffer;
byte_idx <= next_byte_idx;
if (next_byte_idx == 0) begin
data <= next_buffer;
valid <= 1'b1;
end
end
end
endmodule

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