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Update with initial support and drivers for the Microblaze MCS

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commit 3db7967c54b667d2f623ff42b33d5483e69bb5c7 1 parent 2e8f47e
@kpansky authored
View
108 ports/microblaze/Makefile
@@ -0,0 +1,108 @@
+############
+# Settings #
+############
+
+# Build all test applications:
+# make
+#
+
+# Location of build tools and atomthreads sources
+KERNEL_DIR=../../kernel
+TESTS_DIR=../../tests
+BSP_DIR = ./mcs_bsp
+CC=mb-gcc
+OBJCOPY=mb-objcopy
+SIZE=mb-size
+LITTLE_ENDIAN=true
+
+# Enable stack-checking.
+STACK_CHECK=true
+
+# Directory for built objects
+BUILD_DIR=build
+
+# Port/application object files
+APP_OBJECTS = atomport.o tests-main.o
+APP_ASM_OBJECTS = atomport-asm.o
+BSP_OBJECTS = xiomodule.o
+BSP_LDSCRIPT = linker_bram_64k.ld
+
+# Kernel object files
+KERNEL_OBJECTS = atomkernel.o atomsem.o atommutex.o atomtimer.o atomqueue.o
+
+# Collection of built objects (excluding test applications)
+ALL_OBJECTS = $(APP_OBJECTS) $(APP_ASM_OBJECTS) $(KERNEL_OBJECTS) $(BSP_OBJECTS)
+BUILT_OBJECTS = $(patsubst %,$(BUILD_DIR)/%,$(ALL_OBJECTS))
+
+# Test object files (dealt with separately as only one per application build)
+TEST_OBJECTS = $(notdir $(patsubst %.c,%.o,$(wildcard $(TESTS_DIR)/*.c)))
+
+# Target application filenames (.elf and .hex) for each test object
+TEST_ELFS = $(patsubst %.o,%.elf,$(TEST_OBJECTS))
+TEST_HEXS = $(patsubst %.o,%.hex,$(TEST_OBJECTS))
+
+# Search build/output directory for dependencies
+vpath %.o ./$(BUILD_DIR)
+vpath %.elf ./$(BUILD_DIR)
+vpath %.hex ./$(BUILD_DIR)
+
+# GCC flags
+CFLAGS=-g -Os -Wall -Werror -mlittle-endian
+
+# Enable stack-checking (disable if not required)
+ifeq ($(STACK_CHECK),true)
+CFLAGS += -DATOM_STACK_CHECKING
+endif
+
+#################
+# Build targets #
+#################
+
+# All tests
+all: $(BUILD_DIR) $(TEST_HEXS) Makefile
+
+# Make build/output directory
+$(BUILD_DIR):
+ mkdir $(BUILD_DIR)
+
+# Test HEX files (one application build for each test)
+$(TEST_HEXS): %.hex: %.elf
+ @echo Building $@
+ $(OBJCOPY) -j .text -j .data -O ihex $(BUILD_DIR)/$< $(BUILD_DIR)/$@
+
+# Test ELF files (one application build for each test)
+$(TEST_ELFS): %.elf: %.o $(KERNEL_OBJECTS) $(BSP_OBJECTS) $(APP_OBJECTS) $(APP_ASM_OBJECTS)
+ $(CC) $(CFLAGS) $(BUILD_DIR)/$(notdir $<) $(BUILT_OBJECTS) --output $(BUILD_DIR)/$@ -Wl,-Map,$(BUILD_DIR)/$(basename $@).map -T$(BSP_DIR)/$(BSP_LDSCRIPT)
+
+# Kernel objects builder
+$(KERNEL_OBJECTS): %.o: $(KERNEL_DIR)/%.c
+ $(CC) -c $(CFLAGS) -I. -I$(BSP_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Test objects builder
+$(TEST_OBJECTS): %.o: $(TESTS_DIR)/%.c
+ $(CC) -c $(CFLAGS) -I. -I$(KERNEL_DIR) -I$(BSP_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Application C objects builder
+$(APP_OBJECTS): %.o: ./%.c
+ $(CC) -c $(CFLAGS) -I. -I$(KERNEL_DIR) -I$(TESTS_DIR) -I$(BSP_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# Application asm objects builder
+$(APP_ASM_OBJECTS): %.o: ./%.s
+ $(CC) -c $(CFLAGS) -x assembler-with-cpp -I. -I$(KERNEL_DIR) -I$(BSP_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+$(BSP_OBJECTS): %.o: $(BSP_DIR)/%.c
+ $(CC) -c $(CFLAGS) -I. -I$(KERNEL_DIR) -I$(TESTS_DIR) -I$(BSP_DIR) $< -o $(BUILD_DIR)/$(notdir $@)
+
+# .lst file builder
+%.lst: %.c
+ $(CC) $(CFLAGS) -I. -I$(KERNEL_DIR) -I$(TESTS_DIR) -I$(BSP_DIR) -Wa,-al $< > $@
+
+# Clean
+clean:
+ rm -fr build
+ rm -fr doxygen-kernel
+ rm -fr doxygen-microblaze
+
+doxygen:
+ doxygen $(KERNEL_DIR)/Doxyfile
+ doxygen ./Doxyfile
View
8 ports/microblaze/README
@@ -47,16 +47,16 @@ minimum.
PREREQUISITES
-TBD:
+TBD MCS:
---------------------------------------------------------------------------
BUILDING THE SOURCE
-TBD:
-Code was tested by adding required files to a SDK project exported from the
-EDK. Makefile for building on the commandline is TBD.
+TBD MCS:
+Code was tested by adding required files to a Xilinx SDK project exported from the
+Xilinx EDK. Makefile for building on the commandline is TBD.
---------------------------------------------------------------------------
View
3  ports/microblaze/atomport-tests.h
@@ -42,7 +42,8 @@
* it around a critical section for safety.
*/
//#define ATOMLOG printf
-#define ATOMLOG(format, ...) {CRITICAL_STORE; CRITICAL_START(); printf(format, ##__VA_ARGS__); CRITICAL_END();}
+//#define ATOMLOG(format, ...) {CRITICAL_STORE; CRITICAL_START(); printf(format, ##__VA_ARGS__); CRITICAL_END();}
+#define ATOMLOG(format, ...) {CRITICAL_STORE; CRITICAL_START(); print(format); CRITICAL_END();}
/*
* String location macro: for platforms which need to place strings in
View
64 ports/microblaze/atomport.c
@@ -31,11 +31,42 @@
#include "atom.h"
#include "xparameters.h"
#include "mb_interface.h"
-#include "xtmrctr.h"
-#include "xintc.h"
+#if defined(XPAR_XIOMODULE_NUM_INSTANCES)
+
+/* We are using the Microblaze MCS */
+
+#include "xiomodule.h"
+static XIOModule myIOModule;
+
+#define myIntc myIOModule
+#define myTmrCtr myIOModule
+#define XPAR_XPS_INTC_0_DEVICE_ID XPAR_IOMODULE_0_DEVICE_ID
+#define XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR 3
+#define XPAR_XPS_TIMER_0_DEVICE_ID 0
+#define XIntc_Initialize XIOModule_Initialize
+#define XIntc_SetOptions XIOModule_SetOptions
+#define XIntc_Connect XIOModule_Connect
+#define XIntc_Start(a,b) XIOModule_Start(a)
+#define XIntc_Enable XIOModule_Enable
+#define XIntc_DeviceInterruptHandler XIOModule_DeviceInterruptHandler
+#define XTmrCtr_Initialize XIOModule_Timer_Initialize
+#define XTmrCtr_InterruptHandler XIOModule_Timer_InterruptHandler
+#define XTmrCtr_SetOptions XIOModule_Timer_SetOptions
+#define XTmrCtr_SetResetValue XIOModule_SetResetValue
+#define XTmrCtr_Start XIOModule_Timer_Start
+
+#else
+
+/* We are using a Microblaze from EDK */
+#include "xintc.h"
+#include "xtmrctr.h"
static XIntc myIntc;
static XTmrCtr myTmrCtr;
+
+#endif
+
+
volatile uint32_t myTmrCtrIntOccurred;
/**
@@ -54,14 +85,14 @@ volatile uint32_t myTmrCtrIntOccurred;
*/
void microblazeInterruptWrapper(void *DataPtr)
{
- atomIntEnter();
- myTmrCtrIntOccurred = FALSE;
- XIntc_DeviceInterruptHandler(DataPtr);
- if (myTmrCtrIntOccurred == TRUE)
- {
- atomTimerTick();
- }
- atomIntExit(TRUE);
+ atomIntEnter();
+ myTmrCtrIntOccurred = FALSE;
+ XIntc_DeviceInterruptHandler(DataPtr);
+ if (myTmrCtrIntOccurred == TRUE)
+ {
+ atomTimerTick();
+ }
+ atomIntExit(TRUE);
}
/**
@@ -74,12 +105,9 @@ void microblazeInterruptWrapper(void *DataPtr)
*
* @return None
*/
-void microblazeTimerHandler(void *CallBackRef, uint8_t TmrCtrNumber)
+void microblazeTimerHandler(void *CallBackRef)
{
- if (TmrCtrNumber == 0)
- {
- myTmrCtrIntOccurred = TRUE;
- }
+ myTmrCtrIntOccurred = TRUE;
}
/**
@@ -96,15 +124,15 @@ void microblazeInitSystemTickTimer ( void )
/* Setup the interrupt controller with the timer enabled */
XIntc_Initialize(&myIntc, XPAR_XPS_INTC_0_DEVICE_ID);
+ XIntc_SetOptions(&myIntc, XIN_SVC_ALL_ISRS_OPTION);
XIntc_Connect(&myIntc, XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR,
- (XInterruptHandler)XTmrCtr_InterruptHandler, &myTmrCtr);
+ (XInterruptHandler)microblazeTimerHandler, &myTmrCtr);
XIntc_Start(&myIntc, XIN_REAL_MODE);
XIntc_Enable(&myIntc, XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR);
/* Set our timer to generate automatic interrupts at a SYSTEM_TICKS_PER_SEC rate */
XTmrCtr_Initialize(&myTmrCtr, XPAR_XPS_TIMER_0_DEVICE_ID);
- XTmrCtr_SetOptions(&myTmrCtr, 0, XTC_DOWN_COUNT_OPTION | XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION);
- XTmrCtr_SetHandler(&myTmrCtr, (XTmrCtr_Handler)microblazeTimerHandler, NULL);
+ XTmrCtr_SetOptions(&myTmrCtr, 0, XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION);
XTmrCtr_SetResetValue(&myTmrCtr, 0, XPAR_CPU_CORE_CLOCK_FREQ_HZ / SYSTEM_TICKS_PER_SEC);
XTmrCtr_Start(&myTmrCtr, 0);
}
View
12 ports/microblaze/atomport.h
@@ -31,12 +31,16 @@
#ifndef __ATOM_PORT_H
#define __ATOM_PORT_H
+#include "xparameters.h"
#include "mb_interface.h"
+/* For NULL */
+#include <string.h>
+
/* Required number of system ticks per second (normally 100 for 10ms tick) */
#define SYSTEM_TICKS_PER_SEC 100
-/* Size of each stack entry / stack alignment size (8 bits on AVR) */
+/* Size of each stack entry / stack alignment size */
#define STACK_ALIGN_SIZE sizeof(uint32_t)
/**
@@ -44,11 +48,11 @@
*/
#define uint8_t unsigned char
#define uint16_t unsigned short
-#define uint32_t unsigned long
+#define uint32_t unsigned int
#define uint64_t unsigned long long
#define int8_t char
#define int16_t short
-#define int32_t long
+#define int32_t int
#define int64_t long long
#define POINTER void *
@@ -59,7 +63,7 @@
/* Uncomment to enable stack-checking */
-#define ATOM_STACK_CHECKING
+/* #define ATOM_STACK_CHECKING */
#endif /* __ATOM_PORT_H */
View
194 ports/microblaze/mcs_bsp/linker_bram_64k.ld
@@ -0,0 +1,194 @@
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x0500;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x0100;
+
+MEMORY
+{
+ bram : ORIGIN = 0x00000050, LENGTH = 0x0000FFB0
+}
+
+ENTRY(_start)
+
+SECTIONS
+{
+.vectors.reset 0x00000000 : {
+ *(.vectors.reset)
+}
+
+.vectors.sw_exception 0x00000008 : {
+ *(.vectors.sw_exception)
+}
+
+.vectors.interrupt 0x00000010 : {
+ *(.vectors.interrupt)
+}
+
+.vectors.hw_exception 0x00000020 : {
+ *(.vectors.hw_exception)
+}
+
+.text : {
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+} > bram
+
+.init : {
+ KEEP (*(.init))
+} > bram
+
+.fini : {
+ KEEP (*(.fini))
+} > bram
+
+.ctors : {
+ __CTOR_LIST__ = .;
+ ___CTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ ___CTORS_END___ = .;
+} > bram
+
+.dtors : {
+ __DTOR_LIST__ = .;
+ ___DTORS_LIST___ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ ___DTORS_END___ = .;
+} > bram
+
+.rodata : {
+ __rodata_start = .;
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+ __rodata_end = .;
+} > bram
+
+.sdata2 : {
+ . = ALIGN(8);
+ __sdata2_start = .;
+ *(.sdata2)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s2.*)
+ . = ALIGN(8);
+ __sdata2_end = .;
+} > bram
+
+.sbss2 : {
+ __sbss2_start = .;
+ *(.sbss2)
+ *(.sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ __sbss2_end = .;
+} > bram
+
+.data : {
+ . = ALIGN(4);
+ __data_start = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ __data_end = .;
+} > bram
+
+.got : {
+ *(.got)
+} > bram
+
+.got1 : {
+ *(.got1)
+} > bram
+
+.got2 : {
+ *(.got2)
+} > bram
+
+.eh_frame : {
+ *(.eh_frame)
+} > bram
+
+.jcr : {
+ *(.jcr)
+} > bram
+
+.gcc_except_table : {
+ *(.gcc_except_table)
+} > bram
+
+.sdata : {
+ . = ALIGN(8);
+ __sdata_start = .;
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ __sdata_end = .;
+} > bram
+
+.sbss : {
+ . = ALIGN(4);
+ __sbss_start = .;
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ . = ALIGN(8);
+ __sbss_end = .;
+} > bram
+
+.tdata : {
+ __tdata_start = .;
+ *(.tdata)
+ *(.tdata.*)
+ *(.gnu.linkonce.td.*)
+ __tdata_end = .;
+} > bram
+
+.tbss : {
+ __tbss_start = .;
+ *(.tbss)
+ *(.tbss.*)
+ *(.gnu.linkonce.tb.*)
+ __tbss_end = .;
+} > bram
+
+.bss : {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end = .;
+} > bram
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap : {
+ . = ALIGN(8);
+ _heap = .;
+ _heap_start = .;
+ . += _HEAP_SIZE;
+ _heap_end = .;
+} > bram
+
+.stack : {
+ _stack_end = .;
+ . += _STACK_SIZE;
+ . = ALIGN(8);
+ _stack = .;
+ __stack = _stack;
+} > bram
+
+_end = .;
+}
+
View
20 ports/microblaze/mcs_bsp/mb_interface.h
@@ -0,0 +1,20 @@
+#ifndef __MB_INTERFACE_H__
+#define __MB_INTERFACE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+void microblaze_enable_interrupts(void);
+void microblaze_disable_interrupts(void);
+void microblaze_register_handler(XInterruptHandler, void *);
+
+#define mfmsr() ({ unsigned int _msr; __asm__ __volatile__ ("mfs %0,rmsr\n\t" : "=d"(_msr)); _msr; })
+#define mtmsr(_msr) ({ __asm__ __volatile__ ("mts rmsr,%0\n\t nop\n\t" : : "d"(_msr)); })
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __MB_INTERFACE_H__ */
View
608 ports/microblaze/mcs_bsp/xiomodule.c
@@ -0,0 +1,608 @@
+#include "xparameters.h"
+#include "xiomodule.h"
+#include "mb_interface.h"
+
+#define ASSERT(x) if(!(x)) while(1)
+
+/*****************************************************************************
+* Basic STDIO support for newlib
+*****************************************************************************/
+char inbyte(void)
+{
+ u8 XIOModule_Uart_RecvByte(u32 BaseAddress);
+ return XIOModule_Uart_RecvByte(XPAR_IOMODULE_0_BASEADDR);
+}
+
+void outbyte(char c)
+{
+ void XIOModule_Uart_SendByte(u32 BaseAddress, u8 Data);
+ XIOModule_Uart_SendByte(XPAR_IOMODULE_0_BASEADDR, c);
+}
+
+
+
+/*****************************************************************************
+* Minimal Microblaze support library
+*****************************************************************************/
+void XNullHandler(void *NullParameter);
+void XNullHandler(void *NullParameter)
+{
+}
+
+static XInterruptHandler Microblaze_InterruptHandler = XNullHandler;
+static void *Microblaze_InterruptCallBackRef;
+
+void __interrupt_handler(void) __attribute__ ((interrupt_handler));
+void __interrupt_handler(void)
+{
+ Microblaze_InterruptHandler(Microblaze_InterruptCallBackRef);
+}
+
+void microblaze_enable_interrupts(void)
+{
+ unsigned int msr = mfmsr();
+ msr |= 0x2;
+ mtmsr(msr);
+}
+
+void microblaze_disable_interrupts(void)
+{
+ unsigned int msr = mfmsr();
+ msr &= ~0x2;
+ mtmsr(msr);
+}
+
+void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr)
+{
+ Microblaze_InterruptHandler = Handler;
+ Microblaze_InterruptCallBackRef = DataPtr;
+}
+
+/*****************************************************************************
+* IOModule support library
+*****************************************************************************/
+
+static XIOModule_Config theXIOModule_Config =
+{
+ .DeviceId = XPAR_IOMODULE_0_DEVICE_ID,
+ .BaseAddress = XPAR_IOMODULE_0_BASEADDR,
+ .IoBaseAddress = XPAR_IOMODULE_0_IO_BASEADDR,
+ .IntcAckBeforeService = XPAR_IOMODULE_0_INTC_LEVEL_EDGE,
+ .IntcOptions = XIN_SVC_SGL_ISR_OPTION,
+ .PitUsed =
+ {
+ XPAR_IOMODULE_0_USE_PIT1,
+ XPAR_IOMODULE_0_USE_PIT2,
+ XPAR_IOMODULE_0_USE_PIT3,
+ XPAR_IOMODULE_0_USE_PIT4
+ },
+ .PitSize =
+ {
+ XPAR_IOMODULE_0_PIT1_SIZE,
+ XPAR_IOMODULE_0_PIT2_SIZE,
+ XPAR_IOMODULE_0_PIT3_SIZE,
+ XPAR_IOMODULE_0_PIT4_SIZE
+ },
+ .PitPrescaler =
+ {
+ XPAR_IOMODULE_0_PIT1_PRESCALER,
+ XPAR_IOMODULE_0_PIT2_PRESCALER,
+ XPAR_IOMODULE_0_PIT3_PRESCALER,
+ XPAR_IOMODULE_0_PIT4_PRESCALER
+ },
+ .PitReadable =
+ {
+ XPAR_IOMODULE_0_PIT1_READABLE,
+ XPAR_IOMODULE_0_PIT2_READABLE,
+ XPAR_IOMODULE_0_PIT3_READABLE,
+ XPAR_IOMODULE_0_PIT4_READABLE
+ },
+ .GpoInit =
+ {
+ XPAR_IOMODULE_0_GPO1_INIT,
+ XPAR_IOMODULE_0_GPO2_INIT,
+ XPAR_IOMODULE_0_GPO3_INIT,
+ XPAR_IOMODULE_0_GPO4_INIT
+ },
+ .HandlerTable =
+ {
+ {XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},
+ {XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},
+ {XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},
+ {XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},
+ {XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},
+ {XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},
+ {XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},
+ {XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL},{XNullHandler, (void *)NULL}
+ }
+};
+
+
+/*****************************************************************************
+* IOModule General
+*****************************************************************************/
+
+s32 XIOModule_Initialize(XIOModule * InstancePtr, u16 DeviceId)
+{
+ unsigned int ii = 0;
+
+ if (DeviceId != XPAR_IOMODULE_0_DEVICE_ID)
+ return XST_FAILURE;
+
+ ASSERT(InstancePtr != NULL);
+
+ if (InstancePtr->IsReady == XIL_COMPONENT_IS_READY)
+ return XST_SUCCESS;
+
+ ASSERT(InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED);
+
+ InstancePtr->CfgPtr = &theXIOModule_Config;
+
+ InstancePtr->IsReady = 0;
+ InstancePtr->IsStarted = 0;
+
+ /* Initialize GPO */
+ for (ii=0; ii<XGPO_DEVICE_COUNT; ii++)
+ {
+ InstancePtr->GpoValue[ii] = InstancePtr->CfgPtr->GpoInit[ii];
+ }
+
+ /* Initialize GPI -- nothing */
+
+ /* Initialize UART -- nothing */
+
+ /* Initialize PIT */
+ for (ii=0; ii<XTC_DEVICE_TIMER_COUNT; ii++)
+ {
+ InstancePtr->TimerTCSR[ii] = 0;
+ InstancePtr->TimerTLR[ii] = 0;
+ }
+
+ /* Initialize Interrupt Controller */
+ InstancePtr->IntEnabledMask = 0;
+
+ InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+ return XST_SUCCESS;
+}
+
+s32 XIOModule_Start(XIOModule * InstancePtr)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+
+ return XST_SUCCESS;
+}
+
+void XIOModule_Stop(XIOModule * InstancePtr)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->IsStarted = 0;
+}
+
+u32 XIOModule_IoReadWord(XIOModule *InstancePtr, u32 ByteOffset)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XIo_In32(InstancePtr->CfgPtr->IoBaseAddress + ByteOffset);
+}
+
+u16 XIOModule_IoReadHalfword(XIOModule *InstancePtr, u32 ByteOffset)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XIo_In16(InstancePtr->CfgPtr->IoBaseAddress + ByteOffset);
+}
+
+u8 XIOModule_IoReadByte(XIOModule *InstancePtr, u32 ByteOffset)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XIo_In8(InstancePtr->CfgPtr->IoBaseAddress + ByteOffset);
+}
+
+void XIOModule_IoWriteWord(XIOModule *InstancePtr, u32 ByteOffset, u32 Data)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XIo_Out32(InstancePtr->CfgPtr->IoBaseAddress + ByteOffset, Data);
+}
+
+void XIOModule_IoWriteHalfword(XIOModule *InstancePtr, u32 ByteOffset, u16 Data)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XIo_Out16(InstancePtr->CfgPtr->IoBaseAddress + ByteOffset, Data);
+}
+
+void XIOModule_IoWriteByte(XIOModule *InstancePtr, u32 ByteOffset, u8 Data)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XIo_Out8(InstancePtr->CfgPtr->IoBaseAddress + ByteOffset, Data);
+}
+
+
+/*****************************************************************************
+* IOModule UART
+*****************************************************************************/
+
+/* Private Functions and Function-like Macros */
+#define XIOModule_Uart_IsReceiveEmpty(BaseAddress) ((XIo_In32(BaseAddress + XUL_STATUS_REG_OFFSET) & XUL_SR_RX_FIFO_VALID_DATA) != XUL_SR_RX_FIFO_VALID_DATA)
+#define XIOModule_Uart_IsTransmitFull(BaseAddress) ((XIo_In32(BaseAddress + XUL_STATUS_REG_OFFSET) & XUL_SR_TX_FIFO_FULL) == XUL_SR_TX_FIFO_FULL)
+
+void XIOModule_Uart_SendByte(u32 BaseAddress, u8 Data)
+{
+ ASSERT(BaseAddress != 0);
+ while (XIOModule_Uart_IsTransmitFull(BaseAddress));
+ XIo_Out32((BaseAddress) + XUL_TX_OFFSET, Data);
+}
+
+u8 XIOModule_Uart_RecvByte(u32 BaseAddress)
+{
+ ASSERT(BaseAddress != 0);
+ while (XIOModule_Uart_IsReceiveEmpty(BaseAddress));
+ return (u8)XIo_In32((BaseAddress) + XUL_RX_OFFSET);
+}
+
+/* Functions and Function-like Macros */
+u32 XIOModule_Uart_Send(XIOModule *InstancePtr, u8 *DataBufferPtr, u32 NumBytes)
+{
+ u32 ii = 0;
+
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for(ii=0; ii<NumBytes; ii++)
+ {
+ XIOModule_Uart_SendByte(InstancePtr->CfgPtr->BaseAddress, DataBufferPtr[ii]);
+ }
+
+ return ii;
+}
+
+u32 XIOModule_Uart_Recv(XIOModule *InstancePtr, u8 *DataBufferPtr, u32 NumBytes)
+{
+ u32 ii = 0;
+
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for(ii=0; ii<NumBytes; ii++)
+ {
+ DataBufferPtr[ii] = XIOModule_Uart_RecvByte(InstancePtr->CfgPtr->BaseAddress);
+ }
+
+ return ii;
+}
+
+s32 XIOModule_Uart_IsSending(XIOModule *InstancePtr)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return XIOModule_Uart_IsTransmitFull(InstancePtr->CfgPtr->BaseAddress);
+}
+
+
+/*****************************************************************************
+* IOModule Interrupt Controller
+*****************************************************************************/
+
+/* Functions and Function-like Macros */
+void XIOModule_Intc_DeviceInterruptHandler(void *DeviceId)
+{
+ XIOModule_Config* CfgPtr = NULL;
+ u32 Pending = 0;
+ u32 IntMask = 0;
+ u32 IntNum = 0;
+
+ ASSERT((u32)DeviceId == theXIOModule_Config.DeviceId);
+ CfgPtr = &theXIOModule_Config;
+ ASSERT(CfgPtr != NULL);
+
+ Pending = XIo_In32(CfgPtr->BaseAddress + XIN_IPR_OFFSET);
+
+ for (IntMask = 0x1, IntNum = 0; Pending != 0; IntMask <<= 1, IntNum++)
+ {
+ if (IntMask & Pending)
+ {
+ if (CfgPtr->IntcAckBeforeService & IntMask)
+ XIo_Out32(CfgPtr->BaseAddress + XIN_IAR_OFFSET, IntMask);
+
+ if (CfgPtr->HandlerTable[IntNum].Handler != NULL)
+ CfgPtr->HandlerTable[IntNum].Handler(CfgPtr->HandlerTable[IntNum].CallBackRef);
+
+ if (~CfgPtr->IntcAckBeforeService & IntMask)
+ XIo_Out32(CfgPtr->BaseAddress + XIN_IAR_OFFSET, IntMask);
+
+ Pending &= ~IntMask;
+
+ if (CfgPtr->IntcOptions & XIN_SVC_SGL_ISR_OPTION)
+ Pending = 0;
+ }
+ }
+ return;
+}
+
+s32 XIOModule_Intc_Connect(XIOModule * InstancePtr, u8 Id, XInterruptHandler Handler, void *CallBackRef)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(Id < XPAR_IOMODULE_INTC_MAX_INTR_SIZE);
+
+ if(InstancePtr->CfgPtr->HandlerTable[Id].Handler != XNullHandler)
+ return XST_FAILURE;
+
+
+ InstancePtr->CfgPtr->HandlerTable[Id].Handler = Handler;
+ InstancePtr->CfgPtr->HandlerTable[Id].CallBackRef = CallBackRef;
+
+ return XST_SUCCESS;
+}
+
+void XIOModule_Intc_Disconnect(XIOModule * InstancePtr, u8 Id)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(Id < XPAR_IOMODULE_INTC_MAX_INTR_SIZE);
+
+ InstancePtr->CfgPtr->HandlerTable[Id].Handler = XNullHandler;
+ InstancePtr->CfgPtr->HandlerTable[Id].CallBackRef = NULL;
+}
+
+void XIOModule_Intc_Enable(XIOModule * InstancePtr, u8 Id)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(Id < XPAR_IOMODULE_INTC_MAX_INTR_SIZE);
+
+ InstancePtr->IntEnabledMask |= (1 << Id);
+
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + XIN_IER_OFFSET, InstancePtr->IntEnabledMask);
+}
+
+void XIOModule_Intc_Disable(XIOModule * InstancePtr, u8 Id)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(Id < XPAR_IOMODULE_INTC_MAX_INTR_SIZE);
+
+ InstancePtr->IntEnabledMask &= ~(1 << Id);
+
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + XIN_IER_OFFSET, InstancePtr->IntEnabledMask);
+}
+
+void XIOModule_Intc_Acknowledge(XIOModule * InstancePtr, u8 Id)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(Id < XPAR_IOMODULE_INTC_MAX_INTR_SIZE);
+
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + XIN_IAR_OFFSET, (1 << Id));
+}
+
+void XIOModule_Intc_InterruptHandler(XIOModule * InstancePtr)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ XIOModule_Intc_DeviceInterruptHandler((void *)(u32)InstancePtr->CfgPtr->DeviceId);
+}
+
+s32 XIOModule_Intc_SetOptions(XIOModule * InstancePtr, u32 Options)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ InstancePtr->CfgPtr->IntcOptions = Options;
+
+ return XST_SUCCESS;
+}
+
+u32 XIOModule_Intc_GetOptions(XIOModule * InstancePtr)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ return InstancePtr->CfgPtr->IntcOptions;
+}
+
+
+
+
+/*****************************************************************************
+* IOModule PIT
+*****************************************************************************/
+
+/* Functions and Function-like Macros */
+s32 XIOModule_Timer_Initialize(XIOModule * InstancePtr, u16 DeviceId)
+{
+ u32 ii = 0;
+
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+ for (ii=0; ii < XTC_DEVICE_TIMER_COUNT; ii++)
+ {
+ InstancePtr->TimerTCSR[ii] = 0;
+ InstancePtr->TimerTLR[ii] = 0;
+
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + (ii*0x10) + XTC_TCSR_OFFSET, InstancePtr->TimerTCSR[ii]);
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + (ii*0x10) + XTC_TLR_OFFSET, InstancePtr->TimerTLR[ii]);
+ }
+
+ return XST_SUCCESS;
+}
+
+void XIOModule_Timer_Start(XIOModule * InstancePtr, u8 TimerNumber)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(TimerNumber < XTC_DEVICE_TIMER_COUNT);
+ ASSERT(InstancePtr->CfgPtr->PitUsed[TimerNumber]);
+
+ InstancePtr->TimerTCSR[TimerNumber] |= XTC_CSR_ENABLE_TMR_MASK;
+
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + (TimerNumber*0x10) + XTC_TCSR_OFFSET, InstancePtr->TimerTCSR[TimerNumber]);
+}
+
+void XIOModule_Timer_Stop(XIOModule * InstancePtr, u8 TimerNumber)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(TimerNumber < XTC_DEVICE_TIMER_COUNT);
+ ASSERT(InstancePtr->CfgPtr->PitUsed[TimerNumber]);
+
+ InstancePtr->TimerTCSR[TimerNumber] &= ~XTC_CSR_ENABLE_TMR_MASK;
+
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + (TimerNumber*0x10) + XTC_TCSR_OFFSET, InstancePtr->TimerTCSR[TimerNumber]);
+}
+
+u32 XIOModule_Timer_GetValue(XIOModule * InstancePtr, u8 TimerNumber)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(TimerNumber < XTC_DEVICE_TIMER_COUNT);
+ ASSERT(InstancePtr->CfgPtr->PitUsed[TimerNumber]);
+ ASSERT(InstancePtr->CfgPtr->PitReadable[TimerNumber]);
+
+ return XIo_In32(InstancePtr->CfgPtr->BaseAddress + (TimerNumber*0x10) + XTC_TCR_OFFSET);
+}
+
+void XIOModule_Timer_SetResetValue(XIOModule * InstancePtr, u8 TimerNumber, u32 ResetValue)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(TimerNumber < XTC_DEVICE_TIMER_COUNT);
+ ASSERT(InstancePtr->CfgPtr->PitUsed[TimerNumber]);
+ ASSERT(ResetValue < (1 << (InstancePtr->CfgPtr->PitSize[TimerNumber]-1)));
+
+ InstancePtr->TimerTLR[TimerNumber] = ResetValue;
+
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + (TimerNumber*0x10) + XTC_TLR_OFFSET, InstancePtr->TimerTLR[TimerNumber]);
+}
+
+s32 XIOModule_Timer_IsExpired(XIOModule * InstancePtr, u8 TimerNumber)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(TimerNumber < XTC_DEVICE_TIMER_COUNT);
+ ASSERT(InstancePtr->CfgPtr->PitUsed[TimerNumber]);
+ ASSERT(InstancePtr->CfgPtr->PitReadable[TimerNumber]);
+
+ return (XIo_In32(InstancePtr->CfgPtr->BaseAddress + (TimerNumber*0x10) + XTC_TCR_OFFSET) == 0);
+}
+
+void XIOModule_Timer_Reset(XIOModule * InstancePtr, u8 TimerNumber)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(TimerNumber < XTC_DEVICE_TIMER_COUNT);
+ ASSERT(InstancePtr->CfgPtr->PitUsed[TimerNumber]);
+
+ if (InstancePtr->TimerTCSR[TimerNumber] & XTC_CSR_ENABLE_TMR_MASK)
+ {
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + (TimerNumber*0x10) + XTC_TCSR_OFFSET, InstancePtr->TimerTCSR[TimerNumber] & ~XTC_CSR_ENABLE_TMR_MASK);
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + (TimerNumber*0x10) + XTC_TCSR_OFFSET, InstancePtr->TimerTCSR[TimerNumber]);
+ }
+}
+
+void XIOModule_Timer_SetOptions(XIOModule * InstancePtr, u8 TimerNumber, u32 Options)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(TimerNumber < XTC_DEVICE_TIMER_COUNT);
+ ASSERT(InstancePtr->CfgPtr->PitUsed[TimerNumber]);
+
+ InstancePtr->TimerTCSR[TimerNumber] = Options;
+
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + (TimerNumber*0x10) + XTC_TCSR_OFFSET, InstancePtr->TimerTCSR[TimerNumber]);
+}
+
+u32 XIOModule_Timer_GetOptions(XIOModule * InstancePtr, u8 TimerNumber)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(TimerNumber < XTC_DEVICE_TIMER_COUNT);
+ ASSERT(InstancePtr->CfgPtr->PitUsed[TimerNumber]);
+
+ return InstancePtr->TimerTCSR[TimerNumber];
+}
+
+/*****************************************************************************
+* IOModule GPIO
+*****************************************************************************/
+
+/* Functions and Function-like Macros */
+u32 XIOModule_GPI_DiscreteRead(XIOModule *InstancePtr, u8 Channel)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(Channel < XGPI_DEVICE_COUNT);
+
+ if (Channel == 0) ASSERT(XPAR_IOMODULE_0_USE_GPI1);
+ if (Channel == 1) ASSERT(XPAR_IOMODULE_0_USE_GPI2);
+ if (Channel == 2) ASSERT(XPAR_IOMODULE_0_USE_GPI3);
+ if (Channel == 3) ASSERT(XPAR_IOMODULE_0_USE_GPI4);
+
+ return XIo_In32(InstancePtr->CfgPtr->BaseAddress + XGI_IN_OFFSET + (Channel*XGPI_CHAN_OFFSET));
+}
+
+void XIOModule_GPO_DiscreteWrite(XIOModule *InstancePtr, u8 Channel, u32 Mask)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(Channel < XGPO_DEVICE_COUNT);
+
+ if (Channel == 0) ASSERT(XPAR_IOMODULE_0_USE_GPO1);
+ if (Channel == 1) ASSERT(XPAR_IOMODULE_0_USE_GPO2);
+ if (Channel == 2) ASSERT(XPAR_IOMODULE_0_USE_GPO3);
+ if (Channel == 3) ASSERT(XPAR_IOMODULE_0_USE_GPO4);
+
+ InstancePtr->GpoValue[Channel] = Mask;
+
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + XGO_OUT_OFFSET + (Channel*XGPO_CHAN_OFFSET), InstancePtr->GpoValue[Channel]);
+}
+
+void XIOModule_GPO_DiscreteSet(XIOModule *InstancePtr, u8 Channel, u32 Mask)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(Channel < XGPO_DEVICE_COUNT);
+
+ if (Channel == 0) ASSERT(XPAR_IOMODULE_0_USE_GPO1);
+ if (Channel == 1) ASSERT(XPAR_IOMODULE_0_USE_GPO2);
+ if (Channel == 2) ASSERT(XPAR_IOMODULE_0_USE_GPO3);
+ if (Channel == 3) ASSERT(XPAR_IOMODULE_0_USE_GPO4);
+
+ InstancePtr->GpoValue[Channel] |= Mask;
+
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + XGO_OUT_OFFSET + (Channel*XGPO_CHAN_OFFSET), InstancePtr->GpoValue[Channel]);
+}
+
+void XIOModule_GPO_DiscreteClear(XIOModule *InstancePtr, u8 Channel, u32 Mask)
+{
+ ASSERT(InstancePtr != NULL);
+ ASSERT(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+ ASSERT(Channel < XGPO_DEVICE_COUNT);
+
+ if (Channel == 0) ASSERT(XPAR_IOMODULE_0_USE_GPO1);
+ if (Channel == 1) ASSERT(XPAR_IOMODULE_0_USE_GPO2);
+ if (Channel == 2) ASSERT(XPAR_IOMODULE_0_USE_GPO3);
+ if (Channel == 3) ASSERT(XPAR_IOMODULE_0_USE_GPO4);
+
+ InstancePtr->GpoValue[Channel] &= ~Mask;
+
+ XIo_Out32(InstancePtr->CfgPtr->BaseAddress + XGO_OUT_OFFSET + (Channel*XGPO_CHAN_OFFSET), InstancePtr->GpoValue[Channel]);
+}
View
325 ports/microblaze/mcs_bsp/xiomodule.h
@@ -0,0 +1,325 @@
+#ifndef __IOMODULE_H__
+#define __IOMODULE_H__
+
+#include "xparameters.h"
+#include "mb_interface.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************
+* Basic
+*****************************************************************************/
+
+/* Basic types */
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+#ifndef NULL
+#define NULL (void *)0
+#endif
+#ifndef u8
+#define u8 unsigned char
+#endif
+#ifndef u16
+#define u16 unsigned short
+#endif
+#ifndef u32
+#define u32 unsigned int
+#endif
+#ifndef u64
+#define u64 unsigned long long
+#endif
+#ifndef s8
+#define s8 signed char
+#endif
+#ifndef s16
+#define s16 signed short
+#endif
+#ifndef s32
+#define s32 signed int
+#endif
+#ifndef s64
+#define s64 signed long long
+#endif
+
+#define XIL_COMPONENT_IS_READY 0x11111111
+#define XIL_COMPONENT_IS_STARTED 0x22222222
+#define XST_SUCCESS 0x00
+#define XST_FAILURE 0x01
+
+
+/* Basic access macros */
+#define XIo_In8(Addr) (*(volatile u8 *)(Addr))
+#define XIo_In16(Addr) (*(volatile u16 *)(Addr))
+#define XIo_In32(Addr) (*(volatile u32 *)(Addr))
+#define XIo_Out8(Addr, Val) (*(volatile u8 *)((Addr)) = (Val))
+#define XIo_Out16(Addr, Val) (*(volatile u16 *)((Addr)) = (Val))
+#define XIo_Out32(Addr, Val) (*(volatile u32 *)((Addr)) = (Val))
+
+char inbyte(void);
+void outbyte(char);
+
+/*****************************************************************************
+* IOModule Interrupt Controller - Defines and Data Structures
+*****************************************************************************/
+
+/* Register field bitmasks */
+#define XIN_SVC_SGL_ISR_OPTION 0x1
+#define XIN_SVC_ALL_ISRS_OPTION 0x2
+
+/* Register address offsets */
+#define XIN_ISR_OFFSET 0x00000030
+#define XIN_IPR_OFFSET 0x00000034
+#define XIN_IER_OFFSET 0x00000038
+#define XIN_IAR_OFFSET 0x0000003C
+
+/* Interrupt enumerations */
+#define XIN_IOMODULE_FIT_4_INTERRUPT_INTR 10
+#define XIN_IOMODULE_FIT_3_INTERRUPT_INTR 9
+#define XIN_IOMODULE_FIT_2_INTERRUPT_INTR 8
+#define XIN_IOMODULE_FIT_1_INTERRUPT_INTR 7
+#define XIN_IOMODULE_PIT_4_INTERRUPT_INTR 6
+#define XIN_IOMODULE_PIT_3_INTERRUPT_INTR 5
+#define XIN_IOMODULE_PIT_2_INTERRUPT_INTR 4
+#define XIN_IOMODULE_PIT_1_INTERRUPT_INTR 3
+#define XIN_IOMODULE_UART_RX_INTERRUPT_INTR 2
+#define XIN_IOMODULE_UART_TX_INTERRUPT_INTR 1
+#define XIN_IOMODULE_UART_ERROR_INTERRUPT_INTR 0
+#define XIN_IOMODULE_EXTERNAL_INTERRUPT_INTR 16
+
+/* Data types */
+typedef struct {
+ XInterruptHandler Handler;
+ void *CallBackRef;
+} XIOModule_Intc_VectorTableEntry;
+
+
+/*****************************************************************************
+* IOModule GPIO - Defines and Data Structures
+*****************************************************************************/
+
+/* General */
+#define XGPO_DEVICE_COUNT 4
+#define XGPI_DEVICE_COUNT 4
+
+/* Register address offsets */
+#define XGO_OUT_OFFSET 0x00000010
+#define XGI_IN_OFFSET 0x00000020
+#define XGPO_DATA_OFFSET XGO_OUT_OFFSET
+#define XGPO_CHAN_OFFSET 4
+#define XGPI_DATA_OFFSET XGI_IN_OFFSET
+#define XGPI_CHAN_OFFSET 4
+
+
+/*****************************************************************************
+* IOModule UART - Defines and Data Structures
+*****************************************************************************/
+
+/* Register field bitmasks */
+#define XUL_SR_PARITY_ERROR 0x80
+#define XUL_SR_FRAMING_ERROR 0x40
+#define XUL_SR_OVERRUN_ERROR 0x20
+#define XUL_SR_INTR_ENABLED 0x10
+#define XUL_SR_TX_FIFO_FULL 0x08
+#define XUL_SR_RX_FIFO_VALID_DATA 0x01
+#define XUL_STOP_BITS 1
+#define XUL_PARITY_NONE 0
+#define XUL_PARITY_ODD 1
+#define XUL_PARITY_EVEN 2
+
+/* Register address offsets */
+#define XUL_RX_OFFSET 0x00000000
+#define XUL_TX_OFFSET 0x00000004
+#define XUL_STATUS_REG_OFFSET 0x00000008
+
+/* Interrupt Callback profile */
+typedef void (*XIOModule_Uart_Handler)(void *CallBackRef, u32 ByteCount);
+
+
+/*****************************************************************************
+* IOModule PIT - Defines and Data Structures
+*****************************************************************************/
+
+/* Register field bitmasks */
+#define XTC_INT_MODE_OPTION 0x00
+#define XTC_AUTO_RELOAD_OPTION 0x02
+#define XTC_CSR_ENABLE_TMR_MASK 0x01
+#define XTC_CSR_AUTO_RELOAD_MASK 0x02
+
+/* Register address offsets */
+#define XTC_TLR_OFFSET 0x00000040
+#define XTC_TCR_OFFSET 0x00000044
+#define XTC_TCSR_OFFSET 0x00000048
+
+/* General */
+#define XTC_DEVICE_TIMER_COUNT 4
+
+/*****************************************************************************
+* IOModule General - Defines and Data Structures
+*****************************************************************************/
+
+/* Data types */
+typedef struct {
+ u16 DeviceId;
+ u32 BaseAddress;
+ u32 IoBaseAddress;
+ u32 IntcAckBeforeService;
+ u32 IntcOptions;
+ u8 PitUsed[XTC_DEVICE_TIMER_COUNT];
+ u8 PitSize[XTC_DEVICE_TIMER_COUNT];
+ u8 PitPrescaler[XTC_DEVICE_TIMER_COUNT];
+ u8 PitReadable[XTC_DEVICE_TIMER_COUNT];
+ u32 GpoInit[XGPO_DEVICE_COUNT];
+ XIOModule_Intc_VectorTableEntry HandlerTable[XPAR_IOMODULE_INTC_MAX_INTR_SIZE];
+} XIOModule_Config;
+
+typedef struct {
+ u32 IsReady;
+ u32 IsStarted;
+ XIOModule_Config *CfgPtr;
+ u32 GpoValue[XGPO_DEVICE_COUNT];
+ u32 IntEnabledMask;
+ u32 TimerTCSR[XTC_DEVICE_TIMER_COUNT];
+ u32 TimerTLR[XTC_DEVICE_TIMER_COUNT];
+} XIOModule;
+
+
+/*****************************************************************************
+* IOModule General - Functions
+*****************************************************************************/
+
+/* Functions and Function-like Macros */
+s32 XIOModule_Initialize(XIOModule * InstancePtr, u16 DeviceId);
+s32 XIOModule_Start(XIOModule * InstancePtr);
+void XIOModule_Stop(XIOModule * InstancePtr);
+u32 XIOModule_IoReadWord(XIOModule *InstancePtr, u32 ByteOffset);
+u16 XIOModule_IoReadHalfword(XIOModule *InstancePtr, u32 ByteOffset);
+u8 XIOModule_IoReadByte(XIOModule *InstancePtr, u32 ByteOffset);
+void XIOModule_IoWriteWord(XIOModule *InstancePtr, u32 ByteOffset, u32 Data);
+void XIOModule_IoWriteHalfword(XIOModule *InstancePtr, u32 ByteOffset, u16 Data);
+void XIOModule_IoWriteByte(XIOModule *InstancePtr, u32 ByteOffset, u8 Data);
+
+/*****************************************************************************
+* IOModule Interrupt Controller - Functions
+*****************************************************************************/
+
+/* Provide compatability for the haphazard IOModule namespace */
+#define XIOModule_VectorTableEntry XIOModule_Intc_VectorTableEntry
+#define XIOModule_LowLevelInterruptHandler XIOModule_Intc_LowLevelInterruptHandler
+#define XIOModule_DeviceInterruptHandler XIOModule_Intc_DeviceInterruptHandler
+#define XIOModule_RegisterHandler XIOModule_Intc_RegisterHandler
+#define XIOModule_Connect XIOModule_Intc_Connect
+#define XIOModule_Disconnect XIOModule_Intc_Disconnect
+#define XIOModule_Enable XIOModule_Intc_Enable
+#define XIOModule_Disable XIOModule_Intc_Disable
+#define XIOModule_Acknowledge XIOModule_Intc_Acknowledge
+#define XIOModule_InterruptHandler XIOModule_Intc_InterruptHandler
+#define XIOModule_SetOptions XIOModule_Intc_SetOptions
+#define XIOModule_GetOptions XIOModule_Intc_GetOptions
+/* Private -
+#define XIOModule_EnableIntr XIOModule_Intc_EnableIntr
+#define XIOModule_DisableIntr XIOModule_Intc_DisableIntr
+#define XIOModule_AckIntr XIOModule_Intc_AckIntr
+#define XIOModule_GetIntrStatus XIOModule_Intc_GetIntrStatus
+#define XIOModule_VoidInterruptHandler XIOModule_Intc_VoidInterruptHandler
+#define XIOModule_SetIntrSvcOption XIOModule_Intc_SetIntrSvcOption
+*/
+
+
+/* Functions and Function-like Macros */
+void XIOModule_Intc_LowLevelInterruptHandler(void);
+void XIOModule_Intc_DeviceInterruptHandler(void *DeviceId);
+s32 XIOModule_Intc_Connect(XIOModule * InstancePtr, u8 Id, XInterruptHandler Handler, void *CallBackRef);
+void XIOModule_Intc_Disconnect(XIOModule * InstancePtr, u8 Id);
+void XIOModule_Intc_Enable(XIOModule * InstancePtr, u8 Id);
+void XIOModule_Intc_Disable(XIOModule * InstancePtr, u8 Id);
+void XIOModule_Intc_Acknowledge(XIOModule * InstancePtr, u8 Id);
+void XIOModule_Intc_InterruptHandler(XIOModule * InstancePtr);
+s32 XIOModule_Intc_SetOptions(XIOModule * InstancePtr, u32 Options);
+u32 XIOModule_Intc_GetOptions(XIOModule * InstancePtr);
+
+/* Private -
+void XIOModule_Intc_SetIntrSvcOption(u32 BaseAddress, u32 Option);
+void XIOModule_Intc_RegisterHandler(u32 BaseAddress, u32 InterruptId, XInterruptHandler Handler, void *CallBackRef);
+#define XIOModule_Intc_EnableIntr(BaseAddress, EnableMask) XIo_Out32((BaseAddress) + XIN_IER_OFFSET, (EnableMask))
+#define XIOModule_Intc_DisableIntr(BaseAddress, DisableMask) XIo_Out32((BaseAddress) + XIN_IER_OFFSET, ~(DisableMask))
+#define XIOModule_Intc_AckIntr(BaseAddress, AckMask) XIo_Out32((BaseAddress) + XIN_IAR_OFFSET, (AckMask))
+#define XIOModule_Intc_GetIntrStatus(BaseAddress) (XIo_In32((BaseAddress) + XIN_IPR_OFFSET))
+*/
+
+
+/*****************************************************************************
+* IOModule GPIO - Functions
+*****************************************************************************/
+
+/* Provide compatability for the haphazard IOModule namespace */
+#define XIOModule_DiscreteRead XIOModule_GPI_DiscreteRead
+#define XIOModule_DiscreteWrite XIOModule_GPO_DiscreteWrite
+#define XIOModule_DiscreteSet XIOModule_GPO_DiscreteSet
+#define XIOModule_DiscreteClear XIOModule_GPO_DiscreteClear
+
+/* Functions and Function-like Macros */
+u32 XIOModule_GPI_DiscreteRead(XIOModule *InstancePtr, u8 Channel);
+void XIOModule_GPO_DiscreteWrite(XIOModule *InstancePtr, u8 Channel, u32 Mask);
+void XIOModule_GPO_DiscreteSet(XIOModule *InstancePtr, u8 Channel, u32 Mask);
+void XIOModule_GPO_DiscreteClear(XIOModule *InstancePtr, u8 Channel, u32 Mask);
+
+
+
+
+/*****************************************************************************
+* IOModule UART - Functions
+*****************************************************************************/
+
+/* Provide compatability for the haphazard IOModule namespace */
+#define XIOModule_ResetFifos(a) ({;})
+#define XIOModule_Send XIOModule_Uart_Send
+#define XIOModule_Recv XIOModule_Uart_Recv
+#define XIOModule_IsSending XIOModule_Uart_IsSending
+#define XIOModule_Handler XIOModule_Uart_Handler
+/* Private -- do not want to call these
+#define XIOModule_GetStatusReg XIOModule_Uart_GetStatusReg
+#define XIOModule_IsReceiveEmpty XIOModule_Uart_IsReceiveEmpty
+#define XIOModule_IsTransmitFull XIOModule_Uart_IsTransmitFull
+#define XIOModule_SendByte XIOModule_Uart_SendByte
+#define XIOModule_RecvByte XIOModule_Uart_RecvByte
+*/
+
+/* Functions and Function-like Macros */
+u32 XIOModule_Uart_Send(XIOModule *InstancePtr, u8 *DataBufferPtr, u32 NumBytes);
+u32 XIOModule_Uart_Recv(XIOModule *InstancePtr, u8 *DataBufferPtr, u32 NumBytes);
+s32 XIOModule_Uart_IsSending(XIOModule *InstancePtr);
+
+/*****************************************************************************
+* IOModule PIT - Functions
+*****************************************************************************/
+
+/* Provide compatability for the haphazard IOModule namespace */
+#define XIOModule_GetValue XIOModule_Timer_GetValue
+#define XIOModule_SetResetValue XIOModule_Timer_SetResetValue
+#define XIOModule_GetCaptureValue XIOModule_Timer_GetValue
+#define XIOModule_IsExpired XIOModule_Timer_IsExpired
+#define XIOModule_Reset XIOModule_Timer_Reset
+#define XIOModule_SetHandler XIOModule_Timer_SetHandler
+
+/* Functions and Function-like Macros */
+s32 XIOModule_Timer_Initialize(XIOModule * InstancePtr, u16 DeviceId);
+void XIOModule_Timer_Start(XIOModule * InstancePtr, u8 TimerNumber);
+void XIOModule_Timer_Stop(XIOModule * InstancePtr, u8 TimerNumber);
+u32 XIOModule_Timer_GetValue(XIOModule * InstancePtr, u8 TimerNumber);
+void XIOModule_Timer_SetResetValue(XIOModule * InstancePtr, u8 TimerNumber, u32 ResetValue);
+u32 XIOModule_Timer_GetCaptureValue(XIOModule * InstancePtr, u8 TimerNumber);
+s32 XIOModule_Timer_IsExpired(XIOModule * InstancePtr, u8 TimerNumber);
+void XIOModule_Timer_Reset(XIOModule * InstancePtr, u8 TimerNumber);
+void XIOModule_Timer_SetOptions(XIOModule * InstancePtr, u8 TimerNumber, u32 Options);
+u32 XIOModule_Timer_GetOptions(XIOModule * InstancePtr, u8 TimerNumber);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __IOMODULE_H__ */
View
148 ports/microblaze/mcs_bsp/xparameters.h
@@ -0,0 +1,148 @@
+#ifndef __XPARAMETERS_H__
+#define __XPARAMETERS_H__
+
+/*****************************************************************************
+* Global configuration (modify for your generated Microblaze MCS)
+*****************************************************************************/
+#define XPAR_CPU_ID 0
+#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 100000000
+
+/*****************************************************************************
+* XIOModule configuration (modify for your generated Microblaze MCS)
+*****************************************************************************/
+#define XPAR_IOMODULE_0_USE_UART_RX 1
+#define XPAR_IOMODULE_0_USE_UART_TX 1
+#define XPAR_IOMODULE_0_UART_BAUDRATE 115200
+#define XPAR_IOMODULE_0_UART_DATA_BITS 8
+#define XPAR_IOMODULE_0_UART_USE_PARITY 0
+#define XPAR_IOMODULE_0_UART_ODD_PARITY 0
+#define XPAR_IOMODULE_0_UART_RX_INTERRUPT 1
+#define XPAR_IOMODULE_0_UART_TX_INTERRUPT 1
+#define XPAR_IOMODULE_0_UART_ERROR_INTERRUPT 1
+#define XPAR_IOMODULE_0_USE_FIT1 0
+#define XPAR_IOMODULE_0_FIT1_NO_CLOCKS 6216
+#define XPAR_IOMODULE_0_FIT1_INTERRUPT 0
+#define XPAR_IOMODULE_0_USE_FIT2 0
+#define XPAR_IOMODULE_0_FIT2_NO_CLOCKS 6216
+#define XPAR_IOMODULE_0_FIT2_INTERRUPT 0
+#define XPAR_IOMODULE_0_USE_FIT3 0
+#define XPAR_IOMODULE_0_FIT3_NO_CLOCKS 6216
+#define XPAR_IOMODULE_0_FIT3_INTERRUPT 0
+#define XPAR_IOMODULE_0_USE_FIT4 0
+#define XPAR_IOMODULE_0_FIT4_NO_CLOCKS 6216
+#define XPAR_IOMODULE_0_FIT4_INTERRUPT 0
+#define XPAR_IOMODULE_0_USE_PIT1 1
+#define XPAR_IOMODULE_0_PIT1_SIZE 32
+#define XPAR_IOMODULE_0_PIT1_READABLE 1
+#define XPAR_IOMODULE_0_PIT1_PRESCALER 0
+#define XPAR_IOMODULE_0_PIT1_INTERRUPT 1
+#define XPAR_IOMODULE_0_USE_PIT2 1
+#define XPAR_IOMODULE_0_PIT2_SIZE 32
+#define XPAR_IOMODULE_0_PIT2_READABLE 1
+#define XPAR_IOMODULE_0_PIT2_PRESCALER 0
+#define XPAR_IOMODULE_0_PIT2_INTERRUPT 1
+#define XPAR_IOMODULE_0_USE_PIT3 1
+#define XPAR_IOMODULE_0_PIT3_SIZE 32
+#define XPAR_IOMODULE_0_PIT3_READABLE 1
+#define XPAR_IOMODULE_0_PIT3_PRESCALER 0
+#define XPAR_IOMODULE_0_PIT3_INTERRUPT 1
+#define XPAR_IOMODULE_0_USE_PIT4 1
+#define XPAR_IOMODULE_0_PIT4_SIZE 32
+#define XPAR_IOMODULE_0_PIT4_READABLE 1
+#define XPAR_IOMODULE_0_PIT4_PRESCALER 0
+#define XPAR_IOMODULE_0_PIT4_INTERRUPT 1
+#define XPAR_IOMODULE_0_USE_GPO1 1
+#define XPAR_IOMODULE_0_GPO1_SIZE 32
+#define XPAR_IOMODULE_0_GPO1_INIT 0x00000000
+#define XPAR_IOMODULE_0_USE_GPO2 1
+#define XPAR_IOMODULE_0_GPO2_SIZE 32
+#define XPAR_IOMODULE_0_GPO2_INIT 0x00000000
+#define XPAR_IOMODULE_0_USE_GPO3 1
+#define XPAR_IOMODULE_0_GPO3_SIZE 32
+#define XPAR_IOMODULE_0_GPO3_INIT 0x00000000
+#define XPAR_IOMODULE_0_USE_GPO4 1
+#define XPAR_IOMODULE_0_GPO4_SIZE 32
+#define XPAR_IOMODULE_0_GPO4_INIT 0x00000000
+#define XPAR_IOMODULE_0_USE_GPI1 1
+#define XPAR_IOMODULE_0_GPI1_SIZE 32
+#define XPAR_IOMODULE_0_USE_GPI2 1
+#define XPAR_IOMODULE_0_GPI2_SIZE 32
+#define XPAR_IOMODULE_0_USE_GPI3 1
+#define XPAR_IOMODULE_0_GPI3_SIZE 32
+#define XPAR_IOMODULE_0_USE_GPI4 1
+#define XPAR_IOMODULE_0_GPI4_SIZE 32
+#define XPAR_IOMODULE_0_INTC_USE_EXT_INTR 1
+#define XPAR_IOMODULE_0_INTC_INTR_SIZE 16
+#define XPAR_IOMODULE_0_INTC_LEVEL_EDGE 0x0000
+#define XPAR_IOMODULE_0_INTC_POSITIVE 0xFFFF
+
+
+/*****************************************************************************
+* Global constant configuration
+* (constants for the Microblaze MCS - should not need to be modified)
+*****************************************************************************/
+#define XPAR_XIOMODULE_NUM_INSTANCES 1
+#define XPAR_IOMODULE_0_DEVICE_ID 0
+#define XPAR_IOMODULE_0_BASEADDR 0x80000000
+#define XPAR_IOMODULE_0_HIGHADDR 0x8000007F
+#define XPAR_IOMODULE_0_MASK 0xC0000000
+#define XPAR_IOMODULE_0_IO_BASEADDR 0xC0000000
+#define XPAR_IOMODULE_0_IO_HIGHADDR 0xFFFFFFFF
+#define XPAR_IOMODULE_0_IO_MASK 0xC0000000
+#define XPAR_IOMODULE_INTC_MAX_INTR_SIZE 32
+#define XPAR_IOMODULE_SINGLE_BASEADDR XPAR_IOMODULE_0_BASEADDR
+#define XPAR_IOMODULE_SINGLE_HIGHADDR XPAR_IOMODULE_0_HIGHADDR
+#define XPAR_IOMODULE_INTC_SINGLE_DEVICE_ID XPAR_IOMODULE_0_DEVICE_ID
+/*
+#define XPAR_SYSTEM_INTC_INTERRUPT_15_MASK 0X00000001
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_15_INTR 0
+#define XPAR_SYSTEM_INTC_INTERRUPT_14_MASK 0X00000002
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_14_INTR 1
+#define XPAR_SYSTEM_INTC_INTERRUPT_13_MASK 0X00000004
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_13_INTR 2
+#define XPAR_SYSTEM_INTC_INTERRUPT_12_MASK 0X00000008
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_12_INTR 3
+#define XPAR_SYSTEM_INTC_INTERRUPT_11_MASK 0X00000010
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_11_INTR 4
+#define XPAR_SYSTEM_INTC_INTERRUPT_10_MASK 0X00000020
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_10_INTR 5
+#define XPAR_SYSTEM_INTC_INTERRUPT_9_MASK 0X00000040
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_9_INTR 6
+#define XPAR_SYSTEM_INTC_INTERRUPT_8_MASK 0X00000080
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_8_INTR 7
+#define XPAR_SYSTEM_INTC_INTERRUPT_7_MASK 0X00000100
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_7_INTR 8
+#define XPAR_SYSTEM_INTC_INTERRUPT_6_MASK 0X00000200
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_6_INTR 9
+#define XPAR_SYSTEM_INTC_INTERRUPT_5_MASK 0X00000400
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_5_INTR 10
+#define XPAR_SYSTEM_INTC_INTERRUPT_4_MASK 0X00000800
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_4_INTR 11
+#define XPAR_SYSTEM_INTC_INTERRUPT_3_MASK 0X00001000
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_3_INTR 12
+#define XPAR_SYSTEM_INTC_INTERRUPT_2_MASK 0X00002000
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_2_INTR 13
+#define XPAR_SYSTEM_INTC_INTERRUPT_1_MASK 0X00004000
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_1_INTR 14
+#define XPAR_SYSTEM_INTC_INTERRUPT_0_MASK 0X00008000
+#define XPAR_IOMODULE_0_SYSTEM_INTC_INTERRUPT_0_INTR 15
+*/
+#define XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORE_CLOCK_FREQ_HZ
+#define XPAR_MICROBLAZE_ID XPAR_CPU_ID
+#define XPAR_MICROBLAZE_FREQ XPAR_CPU_CORE_CLOCK_FREQ_HZ
+#define XPAR_MICROBLAZE_ENDIANNESS 1
+#define XPAR_MICROBLAZE_USE_MSR_INSTR 0
+#define XPAR_MICROBLAZE_USE_PCMP_INSTR 0
+#define XPAR_MICROBLAZE_USE_BARREL 0
+#define XPAR_MICROBLAZE_USE_DIV 0
+#define XPAR_MICROBLAZE_USE_HW_MUL 0
+#define XPAR_MICROBLAZE_USE_FPU 0
+#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 0
+#define XPAR_MICROBLAZE_USE_MMU 0
+#define XPAR_MICROBLAZE_USE_INTERRUPT 1
+#define XPAR_MICROBLAZE_USE_EXT_BRK 1
+#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 1
+#define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 0
+#define XPAR_MICROBLAZE_HW_VER "8.20.b"
+
+#endif /* __XPARAMETERS_H__ */
View
2  ports/microblaze/tests-main.c
@@ -82,7 +82,7 @@ static uint32_t idle_thread_stack[IDLE_STACK_SIZE_BYTES/4];
/* Forward declarations */
static void main_thread_func (uint32_t data);
-
+void microblazeInitSystemTickTimer(void);
/**
* \b main

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