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Merge pull request #99 from arbaal/81-zero-extend-fix

DCPU16: Fixed issue 34, relative offset
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2 parents a891366 + ee4d9fc commit 41a382bdb4a48f3aea9b657685ea0e3dda9cb8bc @hasenbanck hasenbanck committed Apr 12, 2012
Showing with 16 additions and 8 deletions.
  1. +14 −6 lib/Target/DCPU16/InstPrinter/DCPU16InstPrinter.cpp
  2. +2 −2 test/CodeGen/DCPU16/and.ll
@@ -34,9 +34,13 @@ void DCPU16InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
void DCPU16InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
- if (Op.isImm())
- O << Op.getImm();
- else {
+ if (Op.isImm()) {
+ if (Op.getImm() % 2 == 0) {
+ O << Op.getImm() / 2;
+ } else {
+ llvm_unreachable("immediate is not word sized");
+ }
+ } else {
assert(Op.isExpr() && "unknown pcrel immediate operand");
O << *Op.getExpr();
}
@@ -77,8 +81,12 @@ void DCPU16InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo,
else {
assert(Disp.isImm() && "Expected immediate in displacement field");
if(Disp.getImm() != 0) {
- O << Disp.getImm();
- }
+ if (Disp.getImm() % 2 == 0) {
+ O << Disp.getImm() / 2;
+ } else {
+ llvm_unreachable("immediate is not word sized");
+ }
+ }
}
// Print register base field
@@ -88,7 +96,7 @@ void DCPU16InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo,
}
O << getRegisterName(Base.getReg());
}
-
+
O << ']';
}
@@ -14,9 +14,9 @@ entry:
ret i16 %and
}
; CHECK: :f1
-; CHECK: SET [2+I], A
+; CHECK: SET [1+I], A
; CHECK: SET [I], B
-; CHECK: AND B, [2+I]
+; CHECK: AND B, [1+I]
; CHECK: SET A, B
; CHECK: ADD I, 4

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