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from RAMB16_S to RAMB16BWER, soc nows builds please check log

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commit 95d55a016e8966e42bbd37954c5de3e6e5809b0f 1 parent b3ccb64
Cristian Paul Peñaranda Rojas authored

Showing 2 changed files with 600 additions and 211 deletions. Show diff stats Hide diff stats

  1. +571 207 log
  2. +29 4 soc.v
778 log
@@ -69,68 +69,118 @@ Parsing module <soc>.
69 69 =========================================================================
70 70 * HDL Elaboration *
71 71 =========================================================================
72   -WARNING:HDLCompiler:1016 - "/home/paul/j1-soc/soc.v" Line 301: Port DOPA is not connected to this instance
  72 +WARNING:HDLCompiler:1016 - "/home/paul/j1-soc/soc.v" Line 313: Port DOPA is not connected to this instance
73 73
74 74 Elaborating module <soc>.
75 75
76 76 Elaborating module <reset_gen(RESET_CYCLES=10000)>.
77   -WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 213: Result of 32-bit expression is truncated to fit in 14-bit target.
78   -WARNING:HDLCompiler:1016 - "/home/paul/j1-soc/soc.v" Line 49: Port SSRA is not connected to this instance
  77 +WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 225: Result of 32-bit expression is truncated to fit in 14-bit target.
  78 +WARNING:HDLCompiler:1016 - "/home/paul/j1-soc/soc.v" Line 49: Port DOPA is not connected to this instance
79 79
80 80 Elaborating module <j1>.
81 81
82   -Elaborating module <RAMB16_S2_S2>.
83   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 51: Size mismatch in connection of port <DIA>. Formal port size is 2-bit while actual signal size is 32-bit.
84   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 54: Size mismatch in connection of port <WEA>. Formal port size is 1-bit while actual signal size is 32-bit.
85   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 55: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
86   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <ADDRB>. Formal port size is 13-bit while actual signal size is 15-bit.
87   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 51: Size mismatch in connection of port <DIA>. Formal port size is 2-bit while actual signal size is 32-bit.
88   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 54: Size mismatch in connection of port <WEA>. Formal port size is 1-bit while actual signal size is 32-bit.
89   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 55: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
90   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <ADDRB>. Formal port size is 13-bit while actual signal size is 15-bit.
91   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 51: Size mismatch in connection of port <DIA>. Formal port size is 2-bit while actual signal size is 32-bit.
92   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 54: Size mismatch in connection of port <WEA>. Formal port size is 1-bit while actual signal size is 32-bit.
93   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 55: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
94   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <ADDRB>. Formal port size is 13-bit while actual signal size is 15-bit.
95   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 51: Size mismatch in connection of port <DIA>. Formal port size is 2-bit while actual signal size is 32-bit.
96   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 54: Size mismatch in connection of port <WEA>. Formal port size is 1-bit while actual signal size is 32-bit.
97   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 55: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
98   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <ADDRB>. Formal port size is 13-bit while actual signal size is 15-bit.
99   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 51: Size mismatch in connection of port <DIA>. Formal port size is 2-bit while actual signal size is 32-bit.
100   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 54: Size mismatch in connection of port <WEA>. Formal port size is 1-bit while actual signal size is 32-bit.
101   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 55: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
102   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <ADDRB>. Formal port size is 13-bit while actual signal size is 15-bit.
103   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 51: Size mismatch in connection of port <DIA>. Formal port size is 2-bit while actual signal size is 32-bit.
104   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 54: Size mismatch in connection of port <WEA>. Formal port size is 1-bit while actual signal size is 32-bit.
105   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 55: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
106   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <ADDRB>. Formal port size is 13-bit while actual signal size is 15-bit.
107   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 51: Size mismatch in connection of port <DIA>. Formal port size is 2-bit while actual signal size is 32-bit.
108   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 54: Size mismatch in connection of port <WEA>. Formal port size is 1-bit while actual signal size is 32-bit.
109   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 55: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
110   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <ADDRB>. Formal port size is 13-bit while actual signal size is 15-bit.
111   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 51: Size mismatch in connection of port <DIA>. Formal port size is 2-bit while actual signal size is 32-bit.
112   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 54: Size mismatch in connection of port <WEA>. Formal port size is 1-bit while actual signal size is 32-bit.
113   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 55: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
114   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <ADDRB>. Formal port size is 13-bit while actual signal size is 15-bit.
115   -WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 109: Result of 32-bit expression is truncated to fit in 16-bit target.
116   -WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 136: Result of 6-bit expression is truncated to fit in 5-bit target.
117   -WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 148: Result of 32-bit expression is truncated to fit in 5-bit target.
118   -WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 153: Result of 6-bit expression is truncated to fit in 5-bit target.
119   -WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 174: Result of 15-bit expression is truncated to fit in 13-bit target.
120   -WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 176: Result of 16-bit expression is truncated to fit in 13-bit target.
121   -WARNING:HDLCompiler:1127 - "/home/paul/j1-soc/soc.v" Line 268: Assignment to j1_io_rd ignored, since the identifier is never used
122   -WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 280: Result of 32-bit expression is truncated to fit in 9-bit target.
123   -
124   -Elaborating module <RAMB16_S18_S18>.
125   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 302: Size mismatch in connection of port <DIA>. Formal port size is 16-bit while actual signal size is 32-bit.
126   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 303: Size mismatch in connection of port <DIPA>. Formal port size is 2-bit while actual signal size is 32-bit.
127   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 305: Size mismatch in connection of port <WEA>. Formal port size is 1-bit while actual signal size is 32-bit.
128   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 306: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
129   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 308: Size mismatch in connection of port <ADDRA>. Formal port size is 10-bit while actual signal size is 15-bit.
130   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 313: Size mismatch in connection of port <ENB>. Formal port size is 1-bit while actual signal size is 32-bit.
131   -WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 315: Size mismatch in connection of port <ADDRB>. Formal port size is 10-bit while actual signal size is 16-bit.
132   -WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 321: Result of 17-bit expression is truncated to fit in 16-bit target.
133   -WARNING:HDLCompiler:1127 - "/home/paul/j1-soc/soc.v" Line 364: Assignment to trig_reconf ignored, since the identifier is never used
  82 +Elaborating module <RAMB16BWER(DATA_WIDTH_A=36,DATA_WIDTH_B=9,DOA_REG=0,DOB_REG=0,EN_RSTRAM_A="FALSE",EN_RSTRAM_B="FALSE",SIM_DEVICE="SPARTAN6",WRITE_MODE_A="WRITE_FIRST",WRITE_MODE_B="WRITE_FIRST")>.
  83 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 62: Size mismatch in connection of port <DIPA>. Formal port size is 4-bit while actual signal size is 32-bit.
  84 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 63: Size mismatch in connection of port <DOA>. Formal port size is 32-bit while actual signal size is 2-bit.
  85 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <WEA>. Formal port size is 4-bit while actual signal size is 32-bit.
  86 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 65: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
  87 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 68: Size mismatch in connection of port <ADDRA>. Formal port size is 14-bit while actual signal size is 13-bit.
  88 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 70: Size mismatch in connection of port <DIB>. Formal port size is 32-bit while actual signal size is 2-bit.
  89 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 71: Size mismatch in connection of port <DIPB>. Formal port size is 4-bit while actual signal size is 32-bit.
  90 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 72: Size mismatch in connection of port <WEB>. Formal port size is 4-bit while actual signal size is 1-bit.
  91 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 76: Size mismatch in connection of port <ADDRB>. Formal port size is 14-bit while actual signal size is 15-bit.
  92 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 77: Size mismatch in connection of port <DOB>. Formal port size is 32-bit while actual signal size is 2-bit.
  93 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 62: Size mismatch in connection of port <DIPA>. Formal port size is 4-bit while actual signal size is 32-bit.
  94 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 63: Size mismatch in connection of port <DOA>. Formal port size is 32-bit while actual signal size is 2-bit.
  95 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <WEA>. Formal port size is 4-bit while actual signal size is 32-bit.
  96 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 65: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
  97 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 68: Size mismatch in connection of port <ADDRA>. Formal port size is 14-bit while actual signal size is 13-bit.
  98 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 70: Size mismatch in connection of port <DIB>. Formal port size is 32-bit while actual signal size is 2-bit.
  99 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 71: Size mismatch in connection of port <DIPB>. Formal port size is 4-bit while actual signal size is 32-bit.
  100 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 72: Size mismatch in connection of port <WEB>. Formal port size is 4-bit while actual signal size is 1-bit.
  101 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 76: Size mismatch in connection of port <ADDRB>. Formal port size is 14-bit while actual signal size is 15-bit.
  102 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 77: Size mismatch in connection of port <DOB>. Formal port size is 32-bit while actual signal size is 2-bit.
  103 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 62: Size mismatch in connection of port <DIPA>. Formal port size is 4-bit while actual signal size is 32-bit.
  104 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 63: Size mismatch in connection of port <DOA>. Formal port size is 32-bit while actual signal size is 2-bit.
  105 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <WEA>. Formal port size is 4-bit while actual signal size is 32-bit.
  106 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 65: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
  107 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 68: Size mismatch in connection of port <ADDRA>. Formal port size is 14-bit while actual signal size is 13-bit.
  108 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 70: Size mismatch in connection of port <DIB>. Formal port size is 32-bit while actual signal size is 2-bit.
  109 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 71: Size mismatch in connection of port <DIPB>. Formal port size is 4-bit while actual signal size is 32-bit.
  110 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 72: Size mismatch in connection of port <WEB>. Formal port size is 4-bit while actual signal size is 1-bit.
  111 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 76: Size mismatch in connection of port <ADDRB>. Formal port size is 14-bit while actual signal size is 15-bit.
  112 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 77: Size mismatch in connection of port <DOB>. Formal port size is 32-bit while actual signal size is 2-bit.
  113 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 62: Size mismatch in connection of port <DIPA>. Formal port size is 4-bit while actual signal size is 32-bit.
  114 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 63: Size mismatch in connection of port <DOA>. Formal port size is 32-bit while actual signal size is 2-bit.
  115 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <WEA>. Formal port size is 4-bit while actual signal size is 32-bit.
  116 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 65: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
  117 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 68: Size mismatch in connection of port <ADDRA>. Formal port size is 14-bit while actual signal size is 13-bit.
  118 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 70: Size mismatch in connection of port <DIB>. Formal port size is 32-bit while actual signal size is 2-bit.
  119 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 71: Size mismatch in connection of port <DIPB>. Formal port size is 4-bit while actual signal size is 32-bit.
  120 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 72: Size mismatch in connection of port <WEB>. Formal port size is 4-bit while actual signal size is 1-bit.
  121 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 76: Size mismatch in connection of port <ADDRB>. Formal port size is 14-bit while actual signal size is 15-bit.
  122 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 77: Size mismatch in connection of port <DOB>. Formal port size is 32-bit while actual signal size is 2-bit.
  123 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 62: Size mismatch in connection of port <DIPA>. Formal port size is 4-bit while actual signal size is 32-bit.
  124 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 63: Size mismatch in connection of port <DOA>. Formal port size is 32-bit while actual signal size is 2-bit.
  125 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <WEA>. Formal port size is 4-bit while actual signal size is 32-bit.
  126 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 65: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
  127 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 68: Size mismatch in connection of port <ADDRA>. Formal port size is 14-bit while actual signal size is 13-bit.
  128 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 70: Size mismatch in connection of port <DIB>. Formal port size is 32-bit while actual signal size is 2-bit.
  129 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 71: Size mismatch in connection of port <DIPB>. Formal port size is 4-bit while actual signal size is 32-bit.
  130 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 72: Size mismatch in connection of port <WEB>. Formal port size is 4-bit while actual signal size is 1-bit.
  131 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 76: Size mismatch in connection of port <ADDRB>. Formal port size is 14-bit while actual signal size is 15-bit.
  132 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 77: Size mismatch in connection of port <DOB>. Formal port size is 32-bit while actual signal size is 2-bit.
  133 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 62: Size mismatch in connection of port <DIPA>. Formal port size is 4-bit while actual signal size is 32-bit.
  134 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 63: Size mismatch in connection of port <DOA>. Formal port size is 32-bit while actual signal size is 2-bit.
  135 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <WEA>. Formal port size is 4-bit while actual signal size is 32-bit.
  136 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 65: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
  137 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 68: Size mismatch in connection of port <ADDRA>. Formal port size is 14-bit while actual signal size is 13-bit.
  138 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 70: Size mismatch in connection of port <DIB>. Formal port size is 32-bit while actual signal size is 2-bit.
  139 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 71: Size mismatch in connection of port <DIPB>. Formal port size is 4-bit while actual signal size is 32-bit.
  140 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 72: Size mismatch in connection of port <WEB>. Formal port size is 4-bit while actual signal size is 1-bit.
  141 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 76: Size mismatch in connection of port <ADDRB>. Formal port size is 14-bit while actual signal size is 15-bit.
  142 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 77: Size mismatch in connection of port <DOB>. Formal port size is 32-bit while actual signal size is 2-bit.
  143 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 62: Size mismatch in connection of port <DIPA>. Formal port size is 4-bit while actual signal size is 32-bit.
  144 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 63: Size mismatch in connection of port <DOA>. Formal port size is 32-bit while actual signal size is 2-bit.
  145 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <WEA>. Formal port size is 4-bit while actual signal size is 32-bit.
  146 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 65: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
  147 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 68: Size mismatch in connection of port <ADDRA>. Formal port size is 14-bit while actual signal size is 13-bit.
  148 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 70: Size mismatch in connection of port <DIB>. Formal port size is 32-bit while actual signal size is 2-bit.
  149 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 71: Size mismatch in connection of port <DIPB>. Formal port size is 4-bit while actual signal size is 32-bit.
  150 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 72: Size mismatch in connection of port <WEB>. Formal port size is 4-bit while actual signal size is 1-bit.
  151 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 76: Size mismatch in connection of port <ADDRB>. Formal port size is 14-bit while actual signal size is 15-bit.
  152 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 77: Size mismatch in connection of port <DOB>. Formal port size is 32-bit while actual signal size is 2-bit.
  153 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 62: Size mismatch in connection of port <DIPA>. Formal port size is 4-bit while actual signal size is 32-bit.
  154 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 63: Size mismatch in connection of port <DOA>. Formal port size is 32-bit while actual signal size is 2-bit.
  155 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 64: Size mismatch in connection of port <WEA>. Formal port size is 4-bit while actual signal size is 32-bit.
  156 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 65: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
  157 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 68: Size mismatch in connection of port <ADDRA>. Formal port size is 14-bit while actual signal size is 13-bit.
  158 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 70: Size mismatch in connection of port <DIB>. Formal port size is 32-bit while actual signal size is 2-bit.
  159 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 71: Size mismatch in connection of port <DIPB>. Formal port size is 4-bit while actual signal size is 32-bit.
  160 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 72: Size mismatch in connection of port <WEB>. Formal port size is 4-bit while actual signal size is 1-bit.
  161 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 76: Size mismatch in connection of port <ADDRB>. Formal port size is 14-bit while actual signal size is 15-bit.
  162 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 77: Size mismatch in connection of port <DOB>. Formal port size is 32-bit while actual signal size is 2-bit.
  163 +WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 121: Result of 32-bit expression is truncated to fit in 16-bit target.
  164 +WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 148: Result of 6-bit expression is truncated to fit in 5-bit target.
  165 +WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 160: Result of 32-bit expression is truncated to fit in 5-bit target.
  166 +WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 165: Result of 6-bit expression is truncated to fit in 5-bit target.
  167 +WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 186: Result of 15-bit expression is truncated to fit in 13-bit target.
  168 +WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 188: Result of 16-bit expression is truncated to fit in 13-bit target.
  169 +WARNING:HDLCompiler:1127 - "/home/paul/j1-soc/soc.v" Line 280: Assignment to j1_io_rd ignored, since the identifier is never used
  170 +WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 292: Result of 32-bit expression is truncated to fit in 9-bit target.
  171 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 326: Size mismatch in connection of port <DIPA>. Formal port size is 4-bit while actual signal size is 32-bit.
  172 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 327: Size mismatch in connection of port <DOA>. Formal port size is 32-bit while actual signal size is 16-bit.
  173 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 328: Size mismatch in connection of port <WEA>. Formal port size is 4-bit while actual signal size is 32-bit.
  174 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 329: Size mismatch in connection of port <ENA>. Formal port size is 1-bit while actual signal size is 32-bit.
  175 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 332: Size mismatch in connection of port <ADDRA>. Formal port size is 14-bit while actual signal size is 15-bit.
  176 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 334: Size mismatch in connection of port <DIB>. Formal port size is 32-bit while actual signal size is 16-bit.
  177 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 335: Size mismatch in connection of port <DIPB>. Formal port size is 4-bit while actual signal size is 2-bit.
  178 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 336: Size mismatch in connection of port <WEB>. Formal port size is 4-bit while actual signal size is 1-bit.
  179 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 337: Size mismatch in connection of port <ENB>. Formal port size is 1-bit while actual signal size is 32-bit.
  180 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 340: Size mismatch in connection of port <ADDRB>. Formal port size is 14-bit while actual signal size is 16-bit.
  181 +WARNING:HDLCompiler:189 - "/home/paul/j1-soc/soc.v" Line 341: Size mismatch in connection of port <DOB>. Formal port size is 32-bit while actual signal size is 16-bit.
  182 +WARNING:HDLCompiler:413 - "/home/paul/j1-soc/soc.v" Line 346: Result of 17-bit expression is truncated to fit in 16-bit target.
  183 +WARNING:HDLCompiler:1127 - "/home/paul/j1-soc/soc.v" Line 389: Assignment to trig_reconf ignored, since the identifier is never used
134 184
135 185 =========================================================================
136 186 * HDL Synthesis *
@@ -138,13 +188,13 @@ WARNING:HDLCompiler:1127 - "/home/paul/j1-soc/soc.v" Line 364: Assignment to tri
138 188
139 189 Synthesizing Unit <soc>.
140 190 Related source file is "/home/paul/j1-soc/soc.v".
141   -INFO:Xst:3210 - "/home/paul/j1-soc/soc.v" line 261: Output port <io_rd> of the instance <j1> is unconnected or connected to loadless signal.
  191 +INFO:Xst:3210 - "/home/paul/j1-soc/soc.v" line 273: Output port <io_rd> of the instance <j1> is unconnected or connected to loadless signal.
142 192 Found 16-bit register for signal <xorline_addr>.
143 193 Found 16-bit register for signal <slow_io_addr>.
144 194 Found 16-bit register for signal <slow_io_dout>.
145 195 Found 1-bit register for signal <trig_reset>.
146 196 Found 1-bit register for signal <led>.
147   - Found 16-bit adder for signal <xorline_addr[15]_GND_1_o_add_15_OUT> created at line 321.
  197 + Found 16-bit adder for signal <xorline_addr[15]_GND_1_o_add_15_OUT> created at line 346.
148 198 Summary:
149 199 inferred 1 Adder/Subtractor(s).
150 200 inferred 50 D-type flip-flop(s).
@@ -155,7 +205,7 @@ Synthesizing Unit <reset_gen>.
155 205 Related source file is "/home/paul/j1-soc/soc.v".
156 206 RESET_CYCLES = 10000
157 207 Found 14-bit register for signal <reset_count>.
158   - Found 14-bit subtractor for signal <GND_2_o_GND_2_o_sub_3_OUT<13:0>> created at line 213.
  208 + Found 14-bit subtractor for signal <GND_2_o_GND_2_o_sub_3_OUT<13:0>> created at line 225.
159 209 Summary:
160 210 inferred 1 Adder/Subtractor(s).
161 211 inferred 14 D-type flip-flop(s).
@@ -169,23 +219,23 @@ Synthesizing Unit <j1>.
169 219 Found 16-bit register for signal <st0>.
170 220 Found 5-bit register for signal <rsp>.
171 221 Found 13-bit register for signal <pc>.
172   - Found 14-bit adder for signal <n0166[13:0]> created at line 37.
173   - Found 16-bit adder for signal <st0[15]_st1[15]_add_32_OUT> created at line 101.
174   - Found 5-bit adder for signal <dsp[4]_GND_3_o_add_54_OUT> created at line 136.
175   - Found 5-bit adder for signal <dsp[4]_dd[1]_add_55_OUT> created at line 141.
176   - Found 5-bit adder for signal <rsp[4]_rd[1]_add_56_OUT> created at line 142.
177   - Found 5-bit adder for signal <rsp[4]_GND_3_o_add_61_OUT> created at line 153.
178   - Found 16-bit subtractor for signal <GND_3_o_GND_3_o_sub_41_OUT<15:0>> created at line 109.
179   - Found 5-bit subtractor for signal <GND_3_o_GND_3_o_sub_59_OUT<4:0>> created at line 148.
180   - Found 16-bit shifter logical right for signal <st1[15]_st0[3]_shift_right_39_OUT> created at line 108
181   - Found 16-bit shifter logical left for signal <st1[15]_st0[3]_shift_left_43_OUT> created at line 112
182   - Found 16-bit 16-to-1 multiplexer for signal <st0sel[3]_st1[15]_wide_mux_45_OUT> created at line 98.
183   - Found 5-bit 4-to-1 multiplexer for signal <_n0205> created at line 145.
184   - Found 5-bit 3-to-1 multiplexer for signal <_n0207> created at line 145.
185   - Found 16-bit 3-to-1 multiplexer for signal <_n0209> created at line 145.
186   - Found 16-bit comparator equal for signal <st1[15]_st0[15]_equal_38_o> created at line 106
187   - Found 16-bit comparator greater for signal <st0[15]_st1[15]_LessThan_39_o> created at line 107
188   - Found 16-bit comparator greater for signal <st1[15]_st0[15]_LessThan_45_o> created at line 114
  222 + Found 14-bit adder for signal <n0206[13:0]> created at line 37.
  223 + Found 16-bit adder for signal <st0[15]_st1[15]_add_32_OUT> created at line 113.
  224 + Found 5-bit adder for signal <dsp[4]_GND_3_o_add_54_OUT> created at line 148.
  225 + Found 5-bit adder for signal <dsp[4]_dd[1]_add_55_OUT> created at line 153.
  226 + Found 5-bit adder for signal <rsp[4]_rd[1]_add_56_OUT> created at line 154.
  227 + Found 5-bit adder for signal <rsp[4]_GND_3_o_add_61_OUT> created at line 165.
  228 + Found 16-bit subtractor for signal <GND_3_o_GND_3_o_sub_41_OUT<15:0>> created at line 121.
  229 + Found 5-bit subtractor for signal <GND_3_o_GND_3_o_sub_59_OUT<4:0>> created at line 160.
  230 + Found 16-bit shifter logical right for signal <st1[15]_st0[3]_shift_right_39_OUT> created at line 120
  231 + Found 16-bit shifter logical left for signal <st1[15]_st0[3]_shift_left_43_OUT> created at line 124
  232 + Found 16-bit 16-to-1 multiplexer for signal <st0sel[3]_st1[15]_wide_mux_45_OUT> created at line 110.
  233 + Found 5-bit 4-to-1 multiplexer for signal <_n0394> created at line 157.
  234 + Found 5-bit 3-to-1 multiplexer for signal <_n0396> created at line 157.
  235 + Found 16-bit 3-to-1 multiplexer for signal <_n0398> created at line 157.
  236 + Found 16-bit comparator equal for signal <st1[15]_st0[15]_equal_38_o> created at line 118
  237 + Found 16-bit comparator greater for signal <st0[15]_st1[15]_LessThan_39_o> created at line 119
  238 + Found 16-bit comparator greater for signal <st1[15]_st0[15]_LessThan_45_o> created at line 126
189 239 Summary:
190 240 inferred 2 RAM(s).
191 241 inferred 5 Adder/Subtractor(s).
@@ -334,21 +384,8 @@ Macro Statistics
334 384 * Low Level Synthesis *
335 385 =========================================================================
336 386 WARNING:Xst:1710 - FF/Latch <trig_reset> (without init value) has a constant value of 0 in block <soc>. This FF/Latch will be trimmed during the optimization process.
337   -WARNING:Xst:2677 - Node <xorline_addr_10> of sequential type is unconnected in block <soc>.
338   -WARNING:Xst:2677 - Node <xorline_addr_11> of sequential type is unconnected in block <soc>.
339   -WARNING:Xst:2677 - Node <xorline_addr_12> of sequential type is unconnected in block <soc>.
340   -WARNING:Xst:2677 - Node <xorline_addr_13> of sequential type is unconnected in block <soc>.
341 387 WARNING:Xst:2677 - Node <xorline_addr_14> of sequential type is unconnected in block <soc>.
342 388 WARNING:Xst:2677 - Node <xorline_addr_15> of sequential type is unconnected in block <soc>.
343   -INFO:Xst:1901 - Instance ram[0].ram in unit j1 of type RAMB16_S2_S2 has been replaced by RAMB16BWER
344   -INFO:Xst:1901 - Instance ram[1].ram in unit j1 of type RAMB16_S2_S2 has been replaced by RAMB16BWER
345   -INFO:Xst:1901 - Instance ram[2].ram in unit j1 of type RAMB16_S2_S2 has been replaced by RAMB16BWER
346   -INFO:Xst:1901 - Instance ram[3].ram in unit j1 of type RAMB16_S2_S2 has been replaced by RAMB16BWER
347   -INFO:Xst:1901 - Instance ram[4].ram in unit j1 of type RAMB16_S2_S2 has been replaced by RAMB16BWER
348   -INFO:Xst:1901 - Instance ram[5].ram in unit j1 of type RAMB16_S2_S2 has been replaced by RAMB16BWER
349   -INFO:Xst:1901 - Instance ram[6].ram in unit j1 of type RAMB16_S2_S2 has been replaced by RAMB16BWER
350   -INFO:Xst:1901 - Instance ram[7].ram in unit j1 of type RAMB16_S2_S2 has been replaced by RAMB16BWER
351   -INFO:Xst:1901 - Instance xorline_ram in unit soc of type RAMB16_S18_S18 has been replaced by RAMB16BWER
352 389
353 390 Optimizing unit <soc> ...
354 391
@@ -360,11 +397,6 @@ Found area constraint ratio of 100 (+ 0) on block soc, actual ratio is 8.
360 397 FlipFlop j1/dsp_0 has been replicated 1 time(s)
361 398 FlipFlop j1/dsp_2 has been replicated 1 time(s)
362 399 FlipFlop j1/st0_0 has been replicated 1 time(s)
363   -FlipFlop j1/st0_1 has been replicated 2 time(s)
364   -FlipFlop j1/st0_12 has been replicated 1 time(s)
365   -FlipFlop j1/st0_14 has been replicated 1 time(s)
366   -FlipFlop j1/st0_15 has been replicated 1 time(s)
367   -FlipFlop j1/st0_2 has been replicated 1 time(s)
368 400
369 401 Final Macro Processing ...
370 402
@@ -372,8 +404,8 @@ Final Macro Processing ...
372 404 Final Register Report
373 405
374 406 Macro Statistics
375   -# Registers : 90
376   - Flip-Flops : 90
  407 +# Registers : 88
  408 + Flip-Flops : 88
377 409
378 410 =========================================================================
379 411
@@ -396,23 +428,23 @@ Top Level Output File Name : soc.ngc
396 428
397 429 Primitive and Black Box Usage:
398 430 ------------------------------
399   -# BELS : 619
  431 +# BELS : 629
400 432 # GND : 1
401 433 # INV : 15
402   -# LUT1 : 22
  434 +# LUT1 : 26
403 435 # LUT2 : 28
404   -# LUT3 : 43
  436 +# LUT3 : 41
405 437 # LUT4 : 71
406 438 # LUT5 : 75
407 439 # LUT6 : 220
408   -# MUXCY : 80
  440 +# MUXCY : 84
409 441 # MUXF7 : 10
410 442 # VCC : 1
411   -# XORCY : 53
412   -# FlipFlops/Latches : 90
  443 +# XORCY : 57
  444 +# FlipFlops/Latches : 88
413 445 # FDE : 18
414   -# FDR : 48
415   -# FDRE : 19
  446 +# FDR : 42
  447 +# FDRE : 23
416 448 # FDSE : 5
417 449 # RAMS : 21
418 450 # RAM32M : 4
@@ -430,17 +462,17 @@ Selected Device : 6slx9tqg144-2
430 462
431 463
432 464 Slice Logic Utilization:
433   - Number of Slice Registers: 90 out of 11440 0%
434   - Number of Slice LUTs: 506 out of 5720 8%
435   - Number used as Logic: 474 out of 5720 8%
  465 + Number of Slice Registers: 88 out of 11440 0%
  466 + Number of Slice LUTs: 508 out of 5720 8%
  467 + Number used as Logic: 476 out of 5720 8%
436 468 Number used as Memory: 32 out of 1440 2%
437 469 Number used as RAM: 32
438 470
439 471 Slice Logic Distribution:
440   - Number of LUT Flip Flop pairs used: 530
441   - Number with an unused Flip Flop: 440 out of 530 83%
442   - Number with an unused LUT: 24 out of 530 4%
443   - Number of fully used LUT-FF pairs: 66 out of 530 12%
  472 + Number of LUT Flip Flop pairs used: 528
  473 + Number with an unused Flip Flop: 440 out of 528 83%
  474 + Number with an unused LUT: 20 out of 528 3%
  475 + Number of fully used LUT-FF pairs: 68 out of 528 12%
444 476 Number of unique control sets: 5
445 477
446 478 IO Utilization:
@@ -473,7 +505,7 @@ Clock Information:
473 505 -----------------------------------+------------------------+-------+
474 506 Clock Signal | Clock buffer(FF name) | Load |
475 507 -----------------------------------+------------------------+-------+
476   -clk | BUFGP | 111 |
  508 +clk | BUFGP | 109 |
477 509 -----------------------------------+------------------------+-------+
478 510
479 511 Asynchronous Control Signals Information:
@@ -484,7 +516,7 @@ Timing Summary:
484 516 ---------------
485 517 Speed Grade: -2
486 518
487   - Minimum period: 11.935ns (Maximum Frequency: 83.788MHz)
  519 + Minimum period: 11.526ns (Maximum Frequency: 86.758MHz)
488 520 Minimum input arrival time before clock: No path found
489 521 Maximum output required time after clock: 4.118ns
490 522 Maximum combinational path delay: No path found
@@ -495,10 +527,10 @@ All values displayed in nanoseconds (ns)
495 527
496 528 =========================================================================
497 529 Timing constraint: Default period analysis for Clock 'clk'
498   - Clock period: 11.935ns (frequency: 83.788MHz)
499   - Total number of paths / destination ports: 2239667 / 638
  530 + Clock period: 11.526ns (frequency: 86.758MHz)
  531 + Total number of paths / destination ports: 1551951 / 627
500 532 -------------------------------------------------------------------------
501   -Delay: 11.935ns (Levels of Logic = 20)
  533 +Delay: 11.526ns (Levels of Logic = 20)
502 534 Source: j1/ram[6].ram (RAM)
503 535 Destination: j1/ram[7].ram (RAM)
504 536 Source Clock: clk rising
@@ -508,10 +540,10 @@ Delay: 11.935ns (Levels of Logic = 20)
508 540 Gate Net
509 541 Cell:in->out fanout Delay Delay Logical Name (Net Name)
510 542 ---------------------------------------- ------------
511   - RAMB16BWER:CLKA->DOA1 89 2.100 2.232 j1/ram[6].ram (j1/insn<13>)
512   - LUT3:I1->O 12 0.250 1.297 j1/Mmux_st0sel<3>11_2 (j1/Mmux_st0sel<3>11_1)
513   - LUT6:I3->O 2 0.235 0.954 j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_A47 (j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_A46)
514   - LUT6:I3->O 1 0.235 0.682 j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_lut<0>_SW0 (N179)
  543 + RAMB16BWER:CLKA->DOA1 87 2.100 2.216 j1/ram[6].ram (j1/n0082<1>)
  544 + LUT3:I1->O 22 0.250 1.442 j1/Mmux_st0sel<1>11_1 (j1/Mmux_st0sel<1>11)
  545 + LUT6:I4->O 1 0.250 0.958 j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_lut<0>_SW0_SW0 (N183)
  546 + LUT6:I2->O 1 0.254 0.682 j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_lut<0>_SW0 (N179)
515 547 LUT6:I5->O 1 0.254 0.000 j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_lut<0> (j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_lut<0>)
516 548 MUXCY:S->O 1 0.215 0.000 j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_cy<0> (j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_cy<0>)
517 549 MUXCY:CI->O 1 0.023 0.000 j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_cy<1> (j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_cy<1>)
@@ -528,11 +560,11 @@ Delay: 11.935ns (Levels of Logic = 20)
528 560 MUXCY:CI->O 1 0.023 0.000 j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_cy<12> (j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_cy<12>)
529 561 MUXCY:CI->O 1 0.023 0.000 j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_cy<13> (j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_cy<13>)
530 562 XORCY:CI->O 3 0.206 0.874 j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_rs_xor<14> (j1/Mmux_st0sel[3]_st1[15]_wide_mux_45_OUT15_split<14>)
531   - LUT6:I4->O 32 0.250 1.519 j1/ramWE_GND_3_o_AND_1_o1 (j1/ramWE_GND_3_o_AND_1_o)
  563 + LUT6:I4->O 8 0.250 0.943 j1/ramWE_GND_3_o_AND_1_o1 (j1/ramWE_GND_3_o_AND_1_o)
532 564 RAMB16BWER:WEB0 0.330 j1/ram[7].ram
533 565 ----------------------------------------
534   - Total 11.935ns (4.377ns logic, 7.558ns route)
535   - (36.7% logic, 63.3% route)
  566 + Total 11.526ns (4.411ns logic, 7.115ns route)
  567 + (38.3% logic, 61.7% route)
536 568
537 569 =========================================================================
538 570 Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
@@ -563,23 +595,23 @@ Clock to Setup on destination clock clk
563 595 | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
564 596 Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
565 597 ---------------+---------+---------+---------+---------+
566   -clk | 11.935| | | |
  598 +clk | 11.526| | | |
567 599 ---------------+---------+---------+---------+---------+
568 600
569 601 =========================================================================
570 602
571 603
572 604 Total REAL time to Xst completion: 45.00 secs
573   -Total CPU time to Xst completion: 44.53 secs
  605 +Total CPU time to Xst completion: 44.64 secs
574 606
575 607 -->
576 608
577 609
578   -Total memory usage is 117160 kilobytes
  610 +Total memory usage is 117444 kilobytes
579 611
580 612 Number of errors : 0 ( 0 filtered)
581   -Number of warnings : 74 ( 0 filtered)
582   -Number of infos : 14 ( 0 filtered)
  613 +Number of warnings : 122 ( 0 filtered)
  614 +Number of infos : 5 ( 0 filtered)
583 615
584 616 ngdbuild -uc soc.xc6slx9-2-tqg144.ucf soc.ngc
585 617 Release 13.4 - ngdbuild O.87xd (lin)
@@ -639,116 +671,448 @@ Total REAL time at the beginning of Placer: 16 secs
639 671 Total CPU time at the beginning of Placer: 16 secs
640 672
641 673 Phase 1.1 Initial Placement Analysis
642   -Phase 1.1 Initial Placement Analysis (Checksum:a8f683e) REAL time: 18 secs
  674 +Phase 1.1 Initial Placement Analysis (Checksum:54e11a26) REAL time: 18 secs
643 675
644 676 Phase 2.7 Design Feasibility Check
645   -Phase 2.7 Design Feasibility Check (Checksum:a8f683e) REAL time: 18 secs
  677 +Phase 2.7 Design Feasibility Check (Checksum:54e11a26) REAL time: 18 secs
646 678
647 679 Phase 3.31 Local Placement Optimization
648   -Phase 3.31 Local Placement Optimization (Checksum:a8f683e) REAL time: 18 secs
  680 +Phase 3.31 Local Placement Optimization (Checksum:54e11a26) REAL time: 18 secs
649 681
650 682 Phase 4.2 Initial Placement for Architecture Specific Features
651 683
652 684 Phase 4.2 Initial Placement for Architecture Specific Features
653   -(Checksum:ea42981a) REAL time: 28 secs
  685 +(Checksum:75c03fd7) REAL time: 28 secs
654 686
655 687 Phase 5.36 Local Placement Optimization
656   -Phase 5.36 Local Placement Optimization (Checksum:ea42981a) REAL time: 28 secs
  688 +Phase 5.36 Local Placement Optimization (Checksum:75c03fd7) REAL time: 28 secs
657 689
658 690 Phase 6.30 Global Clock Region Assignment
659   -Phase 6.30 Global Clock Region Assignment (Checksum:ea42981a) REAL time: 28 secs
  691 +Phase 6.30 Global Clock Region Assignment (Checksum:75c03fd7) REAL time: 28 secs
660 692
661 693 Phase 7.3 Local Placement Optimization
662   -Phase 7.3 Local Placement Optimization (Checksum:ea42981a) REAL time: 28 secs
  694 +Phase 7.3 Local Placement Optimization (Checksum:75c03fd7) REAL time: 28 secs
663 695
664 696 Phase 8.5 Local Placement Optimization
665   -Phase 8.5 Local Placement Optimization (Checksum:ea42981a) REAL time: 28 secs
  697 +Phase 8.5 Local Placement Optimization (Checksum:75c03fd7) REAL time: 28 secs
666 698
667 699 Phase 9.8 Global Placement
668   -........................................................................................................................
669   -...................................................
670   -..............................................................................................................................
671   -.................................
672   -Phase 9.8 Global Placement (Checksum:797926fd) REAL time: 38 secs
  700 +...............................................................................................................
  701 +..........................................................................................................................
  702 +................................................................................................................................................................................
  703 +....................
  704 +Phase 9.8 Global Placement (Checksum:e9c7cbdf) REAL time: 37 secs
673 705
674 706 Phase 10.5 Local Placement Optimization
675   -Phase 10.5 Local Placement Optimization (Checksum:797926fd) REAL time: 38 secs
  707 +Phase 10.5 Local Placement Optimization (Checksum:e9c7cbdf) REAL time: 37 secs
676 708
677 709 Phase 11.18 Placement Optimization
678   -Phase 11.18 Placement Optimization (Checksum:7528ad4e) REAL time: 51 secs
  710 +Phase 11.18 Placement Optimization (Checksum:4cad8f5b) REAL time: 1 mins 11 secs
679 711
680 712 Phase 12.5 Local Placement Optimization
681   -Phase 12.5 Local Placement Optimization (Checksum:7528ad4e) REAL time: 51 secs
  713 +Phase 12.5 Local Placement Optimization (Checksum:4cad8f5b) REAL time: 1 mins 11 secs
682 714
683 715 Phase 13.34 Placement Validation
684   -Phase 13.34 Placement Validation (Checksum:744fc0d0) REAL time: 51 secs
  716 +Phase 13.34 Placement Validation (Checksum:4cad8f5b) REAL time: 1 mins 11 secs
685 717
686   -Total REAL time to Placer completion: 52 secs
687   -Total CPU time to Placer completion: 51 secs
  718 +Total REAL time to Placer completion: 1 mins 11 secs
  719 +Total CPU time to Placer completion: 1 mins 10 secs
688 720 Running post-placement packing...
689 721 Writing output files...
690   -ERROR:PhysDesignRules:1678 - Issue with pin connections and/or configuration on
691   - block:<xorline_ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_A
692   - attribute the port A control pins for the RAMB16BWER must be used.
693   -ERROR:PhysDesignRules:1679 - Issue with pin connections and/or configuration on
694   - block:<xorline_ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_B
695   - attribute the port B control pins for the RAMB16BWER must be used.
696   -ERROR:PhysDesignRules:1678 - Issue with pin connections and/or configuration on
697   - block:<j1/ram[0].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_A
698   - attribute the port A control pins for the RAMB16BWER must be used.
699   -ERROR:PhysDesignRules:1679 - Issue with pin connections and/or configuration on
700   - block:<j1/ram[0].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_B
701   - attribute the port B control pins for the RAMB16BWER must be used.
702   -ERROR:PhysDesignRules:1678 - Issue with pin connections and/or configuration on
703   - block:<j1/ram[1].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_A
704   - attribute the port A control pins for the RAMB16BWER must be used.
705   -ERROR:PhysDesignRules:1679 - Issue with pin connections and/or configuration on
706   - block:<j1/ram[1].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_B
707   - attribute the port B control pins for the RAMB16BWER must be used.
708   -ERROR:PhysDesignRules:1678 - Issue with pin connections and/or configuration on
709   - block:<j1/ram[2].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_A
710   - attribute the port A control pins for the RAMB16BWER must be used.
711   -ERROR:PhysDesignRules:1679 - Issue with pin connections and/or configuration on
712   - block:<j1/ram[2].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_B
713   - attribute the port B control pins for the RAMB16BWER must be used.
714   -ERROR:PhysDesignRules:1678 - Issue with pin connections and/or configuration on
715   - block:<j1/ram[3].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_A
716   - attribute the port A control pins for the RAMB16BWER must be used.
717   -ERROR:PhysDesignRules:1679 - Issue with pin connections and/or configuration on
718   - block:<j1/ram[3].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_B
719   - attribute the port B control pins for the RAMB16BWER must be used.
720   -ERROR:PhysDesignRules:1678 - Issue with pin connections and/or configuration on
721   - block:<j1/ram[4].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_A
722   - attribute the port A control pins for the RAMB16BWER must be used.
723   -ERROR:PhysDesignRules:1679 - Issue with pin connections and/or configuration on
724   - block:<j1/ram[4].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_B
725   - attribute the port B control pins for the RAMB16BWER must be used.
726   -ERROR:PhysDesignRules:1678 - Issue with pin connections and/or configuration on
727   - block:<j1/ram[5].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_A
728   - attribute the port A control pins for the RAMB16BWER must be used.
729   -ERROR:PhysDesignRules:1679 - Issue with pin connections and/or configuration on
730   - block:<j1/ram[5].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_B
731   - attribute the port B control pins for the RAMB16BWER must be used.
732   -ERROR:PhysDesignRules:1678 - Issue with pin connections and/or configuration on
733   - block:<j1/ram[6].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_A
734   - attribute the port A control pins for the RAMB16BWER must be used.
735   -ERROR:PhysDesignRules:1679 - Issue with pin connections and/or configuration on
736   - block:<j1/ram[6].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_B
737   - attribute the port B control pins for the RAMB16BWER must be used.
738   -ERROR:PhysDesignRules:1678 - Issue with pin connections and/or configuration on
739   - block:<j1/ram[7].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_A
740   - attribute the port A control pins for the RAMB16BWER must be used.
741   -ERROR:PhysDesignRules:1679 - Issue with pin connections and/or configuration on
742   - block:<j1/ram[7].ram>:<RAMB16BWER_RAMB16BWER>. When using the DATA_WIDTH_B
743   - attribute the port B control pins for the RAMB16BWER must be used.
744   -ERROR:Pack:1642 - Errors in physical DRC.
  722 +
  723 +Design Summary:
  724 +Number of errors: 0
  725 +Number of warnings: 22
  726 +Slice Logic Utilization:
  727 + Number of Slice Registers: 88 out of 11,440 1%
  728 + Number used as Flip Flops: 88
  729 + Number used as Latches: 0
  730 + Number used as Latch-thrus: 0
  731 + Number used as AND/OR logics: 0
  732 + Number of Slice LUTs: 471 out of 5,720 8%
  733 + Number used as logic: 443 out of 5,720 7%
  734 + Number using O6 output only: 364
  735 + Number using O5 output only: 25
  736 + Number using O5 and O6: 54
  737 + Number used as ROM: 0
  738 + Number used as Memory: 26 out of 1,440 1%
  739 + Number used as Dual Port RAM: 26
  740 + Number using O6 output only: 2
  741 + Number using O5 output only: 2
  742 + Number using O5 and O6: 22
  743 + Number used as Single Port RAM: 0
  744 + Number used as Shift Register: 0
  745 + Number used exclusively as route-thrus: 2
  746 + Number with same-slice register load: 0
  747 + Number with same-slice carry load: 2
  748 + Number with other load: 0
  749 +
  750 +Slice Logic Distribution:
  751 + Number of occupied Slices: 151 out of 1,430 10%
  752 + Nummber of MUXCYs used: 100 out of 2,860 3%
  753 + Number of LUT Flip Flop pairs used: 484
  754 + Number with an unused Flip Flop: 398 out of 484 82%
  755 + Number with an unused LUT: 13 out of 484 2%
  756 + Number of fully used LUT-FF pairs: 73 out of 484 15%
  757 + Number of unique control sets: 7
  758 + Number of slice register sites lost
  759 + to control set restrictions: 24 out of 11,440 1%
  760 +
  761 + A LUT Flip Flop pair for this architecture represents one LUT paired with
  762 + one Flip Flop within a slice. A control set is a unique combination of
  763 + clock, reset, set, and enable signals for a registered element.
  764 + The Slice Logic Distribution report is not meaningful if the design is
  765 + over-mapped for a non-slice resource or if Placement fails.
  766 +
  767 +IO Utilization:
  768 + Number of bonded IOBs: 2 out of 102 1%
  769 + Number of LOCed IOBs: 2 out of 2 100%
  770 +
  771 +Specific Feature Utilization:
  772 + Number of RAMB16BWERs: 9 out of 32 28%
  773 + Number of RAMB8BWERs: 0 out of 64 0%
  774 + Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
  775 + Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
  776 + Number of BUFG/BUFGMUXs: 1 out of 16 6%
  777 + Number used as BUFGs: 1
  778 + Number used as BUFGMUX: 0
  779 + Number of DCM/DCM_CLKGENs: 0 out of 4 0%
  780 + Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
  781 + Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
  782 + Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
  783 + Number of BSCANs: 0 out of 4 0%
  784 + Number of BUFHs: 0 out of 128 0%
  785 + Number of BUFPLLs: 0 out of 8 0%
  786 + Number of BUFPLL_MCBs: 0 out of 4 0%
  787 + Number of DSP48A1s: 0 out of 16 0%
  788 + Number of ICAPs: 0 out of 1 0%
  789 + Number of MCBs: 0 out of 2 0%
  790 + Number of PCILOGICSEs: 0 out of 2 0%
  791 + Number of PLL_ADVs: 0 out of 2 0%
  792 + Number of PMVs: 0 out of 1 0%
  793 + Number of STARTUPs: 0 out of 1 0%
  794 + Number of SUSPEND_SYNCs: 0 out of 1 0%
  795 +
  796 +Average Fanout of Non-Clock Nets: 4.53
  797 +
  798 +Peak Memory Usage: 226 MB
  799 +Total REAL time to MAP completion: 1 mins 13 secs
  800 +Total CPU time to MAP completion: 1 mins 12 secs
745 801
746 802 Mapping completed.
747 803 See MAP report file "soc.mrp" for details.
748   -Problem encountered during the packing phase.
  804 +par -w soc.ncd soc-routed.ncd
  805 +Release 13.4 - par O.87xd (lin)
  806 +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
  807 +
  808 +
  809 +
  810 +Constraints file: soc.pcf.
  811 +Loading device for application Rf_Device from file '6slx9.nph' in environment /opt/Xilinx/13.4/ISE_DS/ISE/.
  812 + "soc" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
  813 +vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
  814 +INFO:Security:54 - 'xc6slx9' is a WebPack part.
  815 +WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
  816 +to function, but you no longer qualify for Xilinx software updates or new releases.
  817 +
  818 +----------------------------------------------------------------------
  819 +
  820 +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
  821 +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
  822 +
  823 +INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
  824 + -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
  825 + internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
  826 + reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
  827 + Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
  828 +
  829 +Device speed data version: "PRODUCTION 1.21 2012-01-07".
  830 +
  831 +
  832 +
  833 +Device Utilization Summary:
  834 +
  835 +Slice Logic Utilization:
  836 + Number of Slice Registers: 88 out of 11,440 1%
  837 + Number used as Flip Flops: 88
  838 + Number used as Latches: 0
  839 + Number used as Latch-thrus: 0
  840 + Number used as AND/OR logics: 0
  841 + Number of Slice LUTs: 471 out of 5,720 8%
  842 + Number used as logic: 443 out of 5,720 7%
  843 + Number using O6 output only: 364
  844 + Number using O5 output only: 25
  845 + Number using O5 and O6: 54
  846 + Number used as ROM: 0
  847 + Number used as Memory: 26 out of 1,440 1%
  848 + Number used as Dual Port RAM: 26
  849 + Number using O6 output only: 2
  850 + Number using O5 output only: 2
  851 + Number using O5 and O6: 22
  852 + Number used as Single Port RAM: 0
  853 + Number used as Shift Register: 0
  854 + Number used exclusively as route-thrus: 2
  855 + Number with same-slice register load: 0
  856 + Number with same-slice carry load: 2
  857 + Number with other load: 0
  858 +
  859 +Slice Logic Distribution:
  860 + Number of occupied Slices: 151 out of 1,430 10%
  861 + Nummber of MUXCYs used: 100 out of 2,860 3%
  862 + Number of LUT Flip Flop pairs used: 484
  863 + Number with an unused Flip Flop: 398 out of 484 82%
  864 + Number with an unused LUT: 13 out of 484 2%
  865 + Number of fully used LUT-FF pairs: 73 out of 484 15%
  866 + Number of slice register sites lost
  867 + to control set restrictions: 0 out of 11,440 0%
  868 +
  869 + A LUT Flip Flop pair for this architecture represents one LUT paired with
  870 + one Flip Flop within a slice. A control set is a unique combination of
  871 + clock, reset, set, and enable signals for a registered element.
  872 + The Slice Logic Distribution report is not meaningful if the design is
  873 + over-mapped for a non-slice resource or if Placement fails.
  874 +
  875 +IO Utilization:
  876 + Number of bonded IOBs: 2 out of 102 1%
  877 + Number of LOCed IOBs: 2 out of 2 100%
  878 +
  879 +Specific Feature Utilization:
  880 + Number of RAMB16BWERs: 9 out of 32 28%
  881 + Number of RAMB8BWERs: 0 out of 64 0%
  882 + Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
  883 + Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
  884 + Number of BUFG/BUFGMUXs: 1 out of 16 6%
  885 + Number used as BUFGs: 1
  886 + Number used as BUFGMUX: 0
  887 + Number of DCM/DCM_CLKGENs: 0 out of 4 0%
  888 + Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
  889 + Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
  890 + Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
  891 + Number of BSCANs: 0 out of 4 0%
  892 + Number of BUFHs: 0 out of 128 0%
  893 + Number of BUFPLLs: 0 out of 8 0%
  894 + Number of BUFPLL_MCBs: 0 out of 4 0%
  895 + Number of DSP48A1s: 0 out of 16 0%
  896 + Number of ICAPs: 0 out of 1 0%
  897 + Number of MCBs: 0 out of 2 0%
  898 + Number of PCILOGICSEs: 0 out of 2 0%
  899 + Number of PLL_ADVs: 0 out of 2 0%
  900 + Number of PMVs: 0 out of 1 0%
  901 + Number of STARTUPs: 0 out of 1 0%
  902 + Number of SUSPEND_SYNCs: 0 out of 1 0%
  903 +
  904 +
  905 +Overall effort level (-ol): Standard
  906 +Router effort level (-rl): High
  907 +
  908 +Starting initial Timing Analysis. REAL time: 12 secs
  909 +Finished initial Timing Analysis. REAL time: 12 secs
  910 +
  911 +WARNING:Par:288 - The signal j1/Mram_dstack2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  912 +WARNING:Par:288 - The signal j1/Mram_rstack1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  913 +WARNING:Par:288 - The signal j1/Mram_rstack2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  914 +WARNING:Par:288 - The signal j1/Mram_dstack1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
  915 +Starting Router
  916 +
  917 +
  918 +Phase 1 : 3561 unrouted; REAL time: 12 secs
  919 +
  920 +Phase 2 : 2667 unrouted; REAL time: 13 secs
  921 +
  922 +Phase 3 : 1323 unrouted; REAL time: 16 secs
  923 +
  924 +Phase 4 : 1323 unrouted; (Par is working to improve performance) REAL time: 18 secs
  925 +
  926 +Updating file: soc-routed.ncd with current fully routed design.
  927 +
  928 +Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
  929 +
  930 +Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
  931 +
  932 +Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
  933 +
  934 +Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
  935 +
  936 +Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
  937 +
  938 +Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 24 secs
  939 +Total REAL time to Router completion: 24 secs
  940 +Total CPU time to Router completion: 24 secs
  941 +
  942 +Partition Implementation Status
  943 +-------------------------------
  944 +
  945 + No Partitions were found in this design.
  946 +
  947 +-------------------------------
  948 +
  949 +Generating "PAR" statistics.
  950 +INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
  951 +Timing Score: 0 (Setup: 0, Hold: 0)
  952 +
  953 +Asterisk (*) preceding a constraint indicates it was not met.
  954 + This may be due to a setup or hold violation.
  955 +
  956 +----------------------------------------------------------------------------------------------------------
  957 + Constraint | Check | Worst Case | Best Case | Timing | Timing
  958 + | | Slack | Achievable | Errors | Score
  959 +----------------------------------------------------------------------------------------------------------
  960 + Autotimespec constraint for clock net clk | SETUP | N/A| 14.094ns| N/A| 0
  961 + _BUFGP | HOLD | 0.391ns| | 0| 0
  962 +----------------------------------------------------------------------------------------------------------
  963 +
  964 +
  965 +All constraints were met.
  966 +INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
  967 + constraint is not analyzed due to the following: No paths covered by this
  968 + constraint; Other constraints intersect with this constraint; or This
  969 + constraint was disabled by a Path Tracing Control. Please run the Timespec
  970 + Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
  971 +
  972 +
  973 +Generating Pad Report.
  974 +
  975 +All signals are completely routed.
  976 +
  977 +WARNING:Par:283 - There are 4 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
  978 +
  979 +Total REAL time to PAR completion: 25 secs
  980 +Total CPU time to PAR completion: 25 secs
  981 +
  982 +Peak Memory Usage: 176 MB
  983 +
  984 +Placer: Placement generated during map.
  985 +Routing: Completed - No errors found.
  986 +
  987 +Number of error messages: 0
  988 +Number of warning messages: 6
  989 +Number of info messages: 2
  990 +
  991 +Writing design to file soc-routed.ncd
  992 +
  993 +
  994 +
  995 +PAR done!
  996 +if test -f soc-routed.ncd; then bitgen -b -l -w soc-routed.ncd soc.bit; fi
  997 +Release 13.4 - Bitgen O.87xd (lin)
  998 +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
  999 +Loading device for application Rf_Device from file '6slx9.nph' in environment
  1000 +/opt/Xilinx/13.4/ISE_DS/ISE/.
  1001 + "soc" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
  1002 +
  1003 +Sun Dec 30 16:25:48 2012
  1004 +
  1005 +Running DRC.
  1006 +WARNING:PhysDesignRules:367 - The signal <j1/Mram_dstack2_RAMD_D1_O> is
  1007 + incomplete. The signal does not drive any load pins in the design.
  1008 +WARNING:PhysDesignRules:367 - The signal <j1/Mram_rstack1_RAMD_D1_O> is
  1009 + incomplete. The signal does not drive any load pins in the design.
  1010 +WARNING:PhysDesignRules:367 - The signal <j1/Mram_rstack2_RAMD_D1_O> is
  1011 + incomplete. The signal does not drive any load pins in the design.
  1012 +WARNING:PhysDesignRules:367 - The signal <j1/Mram_dstack1_RAMD_D1_O> is
  1013 + incomplete. The signal does not drive any load pins in the design.
  1014 +WARNING:PhysDesignRules:1627 - Issue with pin connections and/or configuration
  1015 + on block:<xorline_ram>:<RAMB16BWER_RAMB16BWER>. Useless input address pin(s)
  1016 + for RAMB16BWER_RAMB16BWER. When port A is configred to a data width greater
  1017 + than 1 the unused LSB bits of the address to that port (ADDRA0 thru ADDRA4
  1018 + pins) must be tied to ground or left unconnected.
  1019 +WARNING:PhysDesignRules:1630 - Issue with pin connections and/or configuration
  1020 + on block:<xorline_ram>:<RAMB16BWER_RAMB16BWER>. Useless input address pin(s)
  1021 + for RAMB16BWER_RAMB16BWER. When port B is configred to a data width greater
  1022 + than 1 the unused LSB bits of the address to that port (ADDRB0 thru ADDRB2
  1023 + pins) must be tied to ground or left unconnected.
  1024 +WARNING:PhysDesignRules:1627 - Issue with pin connections and/or configuration
  1025 + on block:<j1/ram[0].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1026 + pin(s) for RAMB16BWER_RAMB16BWER. When port A is configred to a data width
  1027 + greater than 1 the unused LSB bits of the address to that port (ADDRA0 thru
  1028 + ADDRA4 pins) must be tied to ground or left unconnected.
  1029 +WARNING:PhysDesignRules:1630 - Issue with pin connections and/or configuration
  1030 + on block:<j1/ram[0].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1031 + pin(s) for RAMB16BWER_RAMB16BWER. When port B is configred to a data width
  1032 + greater than 1 the unused LSB bits of the address to that port (ADDRB0 thru
  1033 + ADDRB2 pins) must be tied to ground or left unconnected.
  1034 +WARNING:PhysDesignRules:1627 - Issue with pin connections and/or configuration
  1035 + on block:<j1/ram[1].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1036 + pin(s) for RAMB16BWER_RAMB16BWER. When port A is configred to a data width
  1037 + greater than 1 the unused LSB bits of the address to that port (ADDRA0 thru
  1038 + ADDRA4 pins) must be tied to ground or left unconnected.
  1039 +WARNING:PhysDesignRules:1630 - Issue with pin connections and/or configuration
  1040 + on block:<j1/ram[1].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1041 + pin(s) for RAMB16BWER_RAMB16BWER. When port B is configred to a data width
  1042 + greater than 1 the unused LSB bits of the address to that port (ADDRB0 thru
  1043 + ADDRB2 pins) must be tied to ground or left unconnected.
  1044 +WARNING:PhysDesignRules:1627 - Issue with pin connections and/or configuration
  1045 + on block:<j1/ram[2].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1046 + pin(s) for RAMB16BWER_RAMB16BWER. When port A is configred to a data width
  1047 + greater than 1 the unused LSB bits of the address to that port (ADDRA0 thru
  1048 + ADDRA4 pins) must be tied to ground or left unconnected.
  1049 +WARNING:PhysDesignRules:1630 - Issue with pin connections and/or configuration
  1050 + on block:<j1/ram[2].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1051 + pin(s) for RAMB16BWER_RAMB16BWER. When port B is configred to a data width
  1052 + greater than 1 the unused LSB bits of the address to that port (ADDRB0 thru
  1053 + ADDRB2 pins) must be tied to ground or left unconnected.
  1054 +WARNING:PhysDesignRules:1627 - Issue with pin connections and/or configuration
  1055 + on block:<j1/ram[3].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1056 + pin(s) for RAMB16BWER_RAMB16BWER. When port A is configred to a data width
  1057 + greater than 1 the unused LSB bits of the address to that port (ADDRA0 thru
  1058 + ADDRA4 pins) must be tied to ground or left unconnected.
  1059 +WARNING:PhysDesignRules:1630 - Issue with pin connections and/or configuration
  1060 + on block:<j1/ram[3].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1061 + pin(s) for RAMB16BWER_RAMB16BWER. When port B is configred to a data width
  1062 + greater than 1 the unused LSB bits of the address to that port (ADDRB0 thru
  1063 + ADDRB2 pins) must be tied to ground or left unconnected.
  1064 +WARNING:PhysDesignRules:1627 - Issue with pin connections and/or configuration
  1065 + on block:<j1/ram[4].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1066 + pin(s) for RAMB16BWER_RAMB16BWER. When port A is configred to a data width
  1067 + greater than 1 the unused LSB bits of the address to that port (ADDRA0 thru
  1068 + ADDRA4 pins) must be tied to ground or left unconnected.
  1069 +WARNING:PhysDesignRules:1630 - Issue with pin connections and/or configuration
  1070 + on block:<j1/ram[4].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1071 + pin(s) for RAMB16BWER_RAMB16BWER. When port B is configred to a data width
  1072 + greater than 1 the unused LSB bits of the address to that port (ADDRB0 thru
  1073 + ADDRB2 pins) must be tied to ground or left unconnected.
  1074 +WARNING:PhysDesignRules:1627 - Issue with pin connections and/or configuration
  1075 + on block:<j1/ram[5].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1076 + pin(s) for RAMB16BWER_RAMB16BWER. When port A is configred to a data width
  1077 + greater than 1 the unused LSB bits of the address to that port (ADDRA0 thru
  1078 + ADDRA4 pins) must be tied to ground or left unconnected.
  1079 +WARNING:PhysDesignRules:1630 - Issue with pin connections and/or configuration
  1080 + on block:<j1/ram[5].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1081 + pin(s) for RAMB16BWER_RAMB16BWER. When port B is configred to a data width
  1082 + greater than 1 the unused LSB bits of the address to that port (ADDRB0 thru
  1083 + ADDRB2 pins) must be tied to ground or left unconnected.
  1084 +WARNING:PhysDesignRules:1627 - Issue with pin connections and/or configuration
  1085 + on block:<j1/ram[6].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1086 + pin(s) for RAMB16BWER_RAMB16BWER. When port A is configred to a data width
  1087 + greater than 1 the unused LSB bits of the address to that port (ADDRA0 thru
  1088 + ADDRA4 pins) must be tied to ground or left unconnected.
  1089 +WARNING:PhysDesignRules:1630 - Issue with pin connections and/or configuration
  1090 + on block:<j1/ram[6].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1091 + pin(s) for RAMB16BWER_RAMB16BWER. When port B is configred to a data width
  1092 + greater than 1 the unused LSB bits of the address to that port (ADDRB0 thru
  1093 + ADDRB2 pins) must be tied to ground or left unconnected.
  1094 +WARNING:PhysDesignRules:1627 - Issue with pin connections and/or configuration
  1095 + on block:<j1/ram[7].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1096 + pin(s) for RAMB16BWER_RAMB16BWER. When port A is configred to a data width
  1097 + greater than 1 the unused LSB bits of the address to that port (ADDRA0 thru
  1098 + ADDRA4 pins) must be tied to ground or left unconnected.
  1099 +WARNING:PhysDesignRules:1630 - Issue with pin connections and/or configuration
  1100 + on block:<j1/ram[7].ram>:<RAMB16BWER_RAMB16BWER>. Useless input address
  1101 + pin(s) for RAMB16BWER_RAMB16BWER. When port B is configred to a data width
  1102 + greater than 1 the unused LSB bits of the address to that port (ADDRB0 thru
  1103 + ADDRB2 pins) must be tied to ground or left unconnected.
  1104 +DRC detected 0 errors and 22 warnings. Please see the previously displayed
  1105 +individual error or warning messages for more details.
  1106 +INFO:Security:54 - 'xc6slx9' is a WebPack part.
  1107 +WARNING:Security:42 - Your software subscription period has lapsed. Your current
  1108 +version of Xilinx tools will continue to function, but you no longer qualify for
  1109 +Xilinx software updates or new releases.
749 1110
750   -Design Summary
751   ---------------
752   -Number of errors : 19
753   -Number of warnings : 4
754   -rm soc.xst soc.ngd soc.prj soc.ngc
  1111 +Saving ll file in "soc.ll".
  1112 +Creating bit map...
  1113 +Saving bit stream in "soc.bit".
  1114 +Saving bit stream in "soc.rbt".
  1115 +Bitstream generation is complete.
  1116 +mkdir -p bits
  1117 +cp soc.bit bits/xc6slx9-2-tqg144.soc.bit
  1118 +rm soc-routed.ncd soc.xst soc.ngd soc.ncd soc.prj soc.ngc
33 soc.v
@@ -46,20 +46,32 @@ module j1(
46 46 generate
47 47 for (i = 0; i < (1 << `RAMS); i=i+1) begin : ram
48 48 // RAMB16_S18_S18
49   - RAMB16_S2_S2
  49 + RAMB16BWER #(
  50 + .DATA_WIDTH_A(36),
  51 + .DATA_WIDTH_B(9),
  52 + .DOA_REG(0),
  53 + .DOB_REG(0),
  54 + .EN_RSTRAM_A("FALSE"),
  55 + .EN_RSTRAM_B("FALSE"),
  56 + .SIM_DEVICE("SPARTAN6"),
  57 + .WRITE_MODE_A("WRITE_FIRST"),
  58 + .WRITE_MODE_B("WRITE_FIRST")
  59 +)
50 60 ram(
51 61 .DIA(0),
52   - // .DIPA(0),
  62 + .DIPA(0),
53 63 .DOA(insn[`w*i+`w1:`w*i]),
54 64 .WEA(0),
55 65 .ENA(1),
  66 + .RSTA(1'b0),
56 67 .CLKA(sys_clk_i),
57 68 .ADDRA({_pc}),
58 69
59 70 .DIB(st1[`w*i+`w1:`w*i]),
60   - // .DIPB(2'b0),
  71 + .DIPB(0),
61 72 .WEB(_ramWE & (_st0[15:14] == 0)),
62 73 .ENB(|_st0[15:14] == 0),
  74 + .RSTB(1'b0),
63 75 .CLKB(sys_clk_i),
64 76 .ADDRB(_st0[15:1]),
65 77 .DOB(ramrd[`w*i+`w1:`w*i]));
@@ -298,12 +310,24 @@ module soc(
298 310 wire [15:0] xorline_prev;
299 311 reg [15:0] xorline_addr;
300 312
301   - RAMB16_S18_S18 xorline_ram(
  313 + RAMB16BWER #(
  314 + .DATA_WIDTH_A(36),
  315 + .DATA_WIDTH_B(9),
  316 + .DOA_REG(0),
  317 + .DOB_REG(0),
  318 + .EN_RSTRAM_A("FALSE"),
  319 + .EN_RSTRAM_B("FALSE"),
  320 + .SIM_DEVICE("SPARTAN6"),
  321 + .WRITE_MODE_A("WRITE_FIRST"),
  322 + .WRITE_MODE_B("WRITE_FIRST")
  323 +)
  324 + xorline_ram(
302 325 .DIA(0),
303 326 .DIPA(0),
304 327 .DOA(xorline_rd),
305 328 .WEA(0),
306 329 .ENA(1),
  330 + .RSTA(1'b0),
307 331 .CLKA(clk),
308 332 .ADDRA(j1_io_addr[15:1]),
309 333
@@ -311,6 +335,7 @@ module soc(
311 335 .DIPB(2'b00),
312 336 .WEB((j1_io_addr == 16'h5f00) & j1_io_wr),
313 337 .ENB(1),
  338 + .RSTB(1'b0),
314 339 .CLKB(clk),
315 340 .ADDRB(xorline_addr),
316 341 .DOB(xorline_prev));

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