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466ad2e @kristianpaul Namuru core, WIP, inclusing Altera shift megfunction migration
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1 // -*- Mode: Verilog -*-
2 // Filename : time_base.v
3 // Description : Generates the TIC (tic_enable), preTIC (pre_tic_enable)
4 // ACCUM_INT (accum_enable) and accum_sample_enable.
5
6 // The accumulator sample rate is set at 40/7 MHz in this design.
7 // The accum_sample_enable pulse is derived from the sample clock
8 // driver for the 2015, but is on a different enable phase.
9
10 // Author : Peter Mumford UNSW 2005
11 /*
12 Copyright (C) 2007 Peter Mumford
13
14 This library is free software; you can redistribute it and/or
15 modify it under the terms of the GNU Lesser General Public
16 License as published by the Free Software Foundation; either
17 version 2.1 of the License, or (at your option) any later version.
18
19 This library is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 Lesser General Public License for more details.
23
24 You should have received a copy of the GNU Lesser General Public
25 License along with this library; if not, write to the Free Software
26 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
27 */
28
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29 module time_base (clk, rstn, tic_divide, accum_divide, sample_clk, pre_tic_enable, tic_enable, accum_enable, accum_sample_enable, tic_count, accum_count);
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30
31
32 input clk, rstn;
33 input [23:0] tic_divide;
34 input [23:0] accum_divide;
35 output sample_clk; // to RF front end GP2015
36 output pre_tic_enable; // to code_nco's
37 output tic_enable; // to code_gen's
38 output accum_enable; // accumulation interrupt
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39 output accum_sample_enable; // accumulators sampling enable (65535/4Hz)
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40 output [23:0] tic_count; // the value of the TIC counter
41 output [23:0] accum_count; // the value of the accum counter
42
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43 // wire [3:0] sc_q; // ouput of divide by 4 counter
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44 // wire [23:0] tic_q;
45 // wire [23:0] accum_q;
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46 reg tic_shift; // used to delay TIC 1 clock cycles
47
981e91c @kristianpaul namuru correlator sampling is system_clock (65535Hz)/4 , achieved by …
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48 // divide by 4 for RF front end (SiGE 4162) sample clock
49 // SoC uses gps clock by 4 so this should sync the sampling
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50 // 4 bit counter
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51 /*lpm_counter sc(
466ad2e @kristianpaul Namuru core, WIP, inclusing Altera shift megfunction migration
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52 .clock(clk),
53 .sclr(!rstn),
54 .q(sc_q)
55 );
56
57 defparam sc.lpm_width= 4;
58 defparam sc.lpm_modulus= 7;
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59 */
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60
ed81fa4 @kristianpaul Altera megafunctions for counters replaced by HDL equivalents, also …
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61 //assign sample_clk = (sc_q == 0)? 1:0;
a27c6f2 @kristianpaul comments for both TIC and accum int, set to fit SiGE 4162 real mode
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62 //assign accum_sample_enable = (sc_q == 3)? 1:0; // accumulator sample pulse
981e91c @kristianpaul namuru correlator sampling is system_clock (65535Hz)/4 , achieved by …
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63 reg [3:0] sc_q;
64 always @(posedge clk) begin
65 if(!rstn)
66 sc_q <= 4'b0;
67 else if (sc_q == 4)
68 sc_q <= 4'b0;
69 else
70 sc_q <= sc_q + 1'b1;
71 end
72 assign accum_sample_enable = (sc_q == 1)? 1:0; // accumulator sample pulse
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73
74 //--------------------------------------------------
75 // generate the tic_enable
76 //
77 // tic period = (tic_divide + 1) * Clk period
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78 // If clocked by SiGE 4162 Realmode 16.384Mhz :
79 // tic period = (tic_divide + 1) / 16.384 Mhz
80 // For default tic period (0.1s) tic_divide = 0x18ffff
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81 //----------------------------------------------------
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82 /* lpm_counter te(
466ad2e @kristianpaul Namuru core, WIP, inclusing Altera shift megfunction migration
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83 .clock(clk),
84 .sclr(!rstn),
85 .sload(pre_tic_enable),
86 .data(tic_divide),
87 .q(tic_q)
88 );
89 defparam te.lpm_direction="DOWN";
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90 defparam te.lpm_width=24; */
91
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92 reg [23:0] tic_q;
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93 always @(posedge clk) begin
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94 if(!rstn)
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95 tic_q <= 24'b111111111111111111111111;
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96 else if (pre_tic_enable)
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97 tic_q <= tic_divide;
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98 else if (tic_q == 24'b0)
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99 tic_q <= 24'b111111111111111111111111;
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100 else
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101 tic_q <= tic_q - 1'b1;
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102 end
103
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104
105 // The preTIC comes first latching the code_nco,
106 // followed by the TIC latching everything else.
107 // This is due to the delay between the code_nco phase
108 // and the prompt code.
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109 assign pre_tic_enable = (tic_q == 0)? 1:0;
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110
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111 assign tic_count = tic_q;
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112
113 always @ (posedge clk)
114 begin
115 if (!rstn) // set up shift register
116 begin
117 tic_shift <= 0;
118 end
119 else // run
120 begin
121 tic_shift <= pre_tic_enable;
122 end
123 end // always @ (posedge clk)
124
125 assign tic_enable = tic_shift;
126 //---------------------------------------------------------
127 // generate the accum_enable
128 //
129 // The Accumulator interrupt signal and flag needs to have
130 // between 0.5 ms and about 1 ms period.
131 // This is to ensure that accumulation data can be read
132 // before it is written over by new data.
133 // The accumulators are asynchronous to each other and have a
134 // dump period of nominally 1ms.
135 //
a27c6f2 @kristianpaul comments for both TIC and accum int, set to fit SiGE 4162 real mode
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136 // ACCUM_INT period = (accum_divide + 1) / 16.384MHz
466ad2e @kristianpaul Namuru core, WIP, inclusing Altera shift megfunction migration
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137 // For 0.5 ms accumulator interrupt
a27c6f2 @kristianpaul comments for both TIC and accum int, set to fit SiGE 4162 real mode
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138 // accum_divide = 16.384x10^6 * 0.0005 - 1
139 // accum_divide = 0x1FFF
466ad2e @kristianpaul Namuru core, WIP, inclusing Altera shift megfunction migration
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140 //----------------------------------------------------------
ed81fa4 @kristianpaul Altera megafunctions for counters replaced by HDL equivalents, also …
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141 /* lpm_counter ae(
466ad2e @kristianpaul Namuru core, WIP, inclusing Altera shift megfunction migration
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142 .clock(clk),
143 .sclr(!rstn),
144 .sload(accum_enable),
145 .data(accum_divide),
146 .q(accum_q)
147 );
148 defparam ae.lpm_direction="DOWN";
149 defparam ae.lpm_width=24;
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150 */
8136a61 @kristianpaul New condition added to Counter, thanks Artyom G
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151 reg [23:0] accum_q;
e02076f @kristianpaul bad coding, this is only syncronous
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152 always @(posedge clk) begin
0ce84f0 @kristianpaul missing negation in reset signal
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153 if(!rstn)
56ecae0 @kristianpaul missing overrun condition for the counter
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154 accum_q <= 24'b111111111111111111111111;
ed81fa4 @kristianpaul Altera megafunctions for counters replaced by HDL equivalents, also …
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155 else if (accum_enable)
8136a61 @kristianpaul New condition added to Counter, thanks Artyom G
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156 accum_q <= accum_divide;
56ecae0 @kristianpaul missing overrun condition for the counter
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157 else if (accum_q == 0)
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158 accum_q <= 24'b111111111111111111111111;
ed81fa4 @kristianpaul Altera megafunctions for counters replaced by HDL equivalents, also …
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159 else
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160 accum_q <= accum_q - 1'b1;
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161 end
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162
8136a61 @kristianpaul New condition added to Counter, thanks Artyom G
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163 assign accum_enable = (accum_q == 0)? 1:0;
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164
8136a61 @kristianpaul New condition added to Counter, thanks Artyom G
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165 assign accum_count = accum_q;
466ad2e @kristianpaul Namuru core, WIP, inclusing Altera shift megfunction migration
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166
167 endmodule // time_base
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