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Fix clock frequency to 4x SiGE EVB Sampling clock

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1 parent b1c6d66 commit 5fc3020a58ccfef5bbc73af1349fbdbb4fa76f69 @kristianpaul committed Feb 19, 2012
Showing with 2 additions and 2 deletions.
  1. +2 −2 boards/milkymist-one/rtl/setup.v
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4 boards/milkymist-one/rtl/setup.v
@@ -42,12 +42,12 @@
/*
* System clock frequency in Hz.
*/
-`define CLOCK_FREQUENCY 81920000
+`define CLOCK_FREQUENCY 65536000
/*
* System clock period in ns (must be in sync with CLOCK_FREQUENCY).
*/
-`define CLOCK_PERIOD 61
+`define CLOCK_PERIOD 15.2
/*
* Default baudrate for the debug UART.

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