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back to MM upstream conbus for now

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commit bdfed2abc6c22c2f73ed80bd3b0f3da7302e59e3 1 parent 56a2e75
Cristian Paul Peñaranda Rojas authored November 26, 2011
27  cores/conbus/rtl/conbus5x7.v → cores/conbus/rtl/conbus5x6.v
@@ -26,7 +26,7 @@
26 26
  * from http://www.opencores.org/lgpl.shtml.
27 27
  */
28 28
 
29  
-module conbus5x7 #(
  29
+module conbus5x6 #(
30 30
 	parameter s0_addr = 3'b000,
31 31
 	parameter s1_addr = 3'b001,
32 32
 	parameter s2_addr = 3'b010,
@@ -158,24 +158,13 @@ module conbus5x7 #(
158 158
 	output		s5_cyc_o,
159 159
 	output		s5_stb_o,
160 160
 	input		s5_ack_i
161  
-
162  
-	// Slave 6 Interface
163  
-/*	input	[31:0]	s6_dat_i,
164  
-	output	[31:0]	s6_dat_o,
165  
-	output	[31:0]	s6_adr_o,
166  
-	output	[2:0]	s6_cti_o,
167  
-	output	[3:0]	s6_sel_o,
168  
-	output		s6_we_o,
169  
-	output		s6_cyc_o,
170  
-	output		s6_stb_o,
171  
-	input		s6_ack_i */
172 161
 );
173 162
 
174 163
 // address + CTI + data + byte select
175 164
 // + cyc + we + stb
176 165
 `define mbusw_ls  32 + 3 + 32 + 4 + 3
177 166
 
178  
-wire [6:0] slave_sel;
  167
+wire [5:0] slave_sel;
179 168
 wire [2:0] gnt;
180 169
 reg [`mbusw_ls -1:0] i_bus_m;	// internal shared bus, master data and control to slave
181 170
 wire [31:0] i_dat_s;		// internal shared bus, slave data to master
@@ -201,8 +190,7 @@ assign m3_ack_o = i_bus_ack & (gnt == 3'd3);
201 190
 assign m4_dat_o = i_dat_s;
202 191
 assign m4_ack_o = i_bus_ack & (gnt == 3'd4);
203 192
 
204  
-//assign i_bus_ack = s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i;
205  
-assign i_bus_ack = s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i ;
  193
+assign i_bus_ack = s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i;
206 194
 
207 195
 // slave 0
208 196
 assign {s0_adr_o, s0_cti_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cyc_o, s0_stb_o} 
@@ -228,10 +216,6 @@ assign {s4_adr_o, s4_cti_o, s4_sel_o, s4_dat_o, s4_we_o, s4_cyc_o, s4_stb_o}
228 216
 assign {s5_adr_o, s5_cti_o, s5_sel_o, s5_dat_o, s5_we_o, s5_cyc_o, s5_stb_o} 
229 217
 	= {i_bus_m[`mbusw_ls -1:2], i_bus_m[1] & slave_sel[5], i_bus_m[0]};
230 218
 
231  
-// slave 6
232  
-//assign {s6_adr_o, s6_cti_o, s6_sel_o, s6_dat_o, s6_we_o, s6_cyc_o, s6_stb_o} 
233  
-//	= {i_bus_m[`mbusw_ls -1:2], i_bus_m[1] & slave_sel[6], i_bus_m[0]};
234  
-
235 219
 always @(*) begin
236 220
 	case(gnt)
237 221
 		3'd0:    i_bus_m = {m0_adr_i, m0_cti_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cyc_i, m0_stb_i};
@@ -243,7 +227,6 @@ always @(*) begin
243 227
 end
244 228
 
245 229
 // !!!! This breaks WISHBONE combinatorial feedback. Don't use it !!!!
246  
-//reg [6:0] slave_sel_r;
247 230
 reg [5:0] slave_sel_r;
248 231
 always @(posedge sys_clk)
249 232
 	slave_sel_r <= slave_sel;
@@ -255,8 +238,7 @@ assign i_dat_s =
255 238
 		|({32{slave_sel_r[2]}} & s2_dat_i)
256 239
 		|({32{slave_sel_r[3]}} & s3_dat_i)
257 240
 		|({32{slave_sel_r[4]}} & s4_dat_i)
258  
-                |({32{slave_sel_r[5]}} & s5_dat_i);
259  
-//		|({32{slave_sel_r[6]}} & s6_dat_i);
  241
+		|({32{slave_sel_r[5]}} & s5_dat_i);
260 242
 
261 243
 wire [4:0] req = {m4_cyc_i, m3_cyc_i, m2_cyc_i, m1_cyc_i, m0_cyc_i};
262 244
 
@@ -272,7 +254,6 @@ assign slave_sel[1] = (i_bus_m[`mbusw_ls-2 : `mbusw_ls-3-1] == s1_addr);
272 254
 assign slave_sel[2] = (i_bus_m[`mbusw_ls-2 : `mbusw_ls-3-1] == s2_addr);
273 255
 assign slave_sel[3] = (i_bus_m[`mbusw_ls-2 : `mbusw_ls-3-1] == s3_addr);
274 256
 assign slave_sel[4] = (i_bus_m[`mbusw_ls-2 : `mbusw_ls-2-1] == s4_addr);
275  
-//assign slave_sel[5] = (i_bus_m[`mbusw_ls-2 : `mbusw_ls-3-1] == s5_addr);
276 257
 assign slave_sel[5] = (i_bus_m[`mbusw_ls-2 : `mbusw_ls-2-1] == s5_addr);
277 258
 
278 259
 endmodule

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