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Merge branch 'master' into gps-sdr-testing

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2 parents a6abb25 + 36b1e07 commit f41cc076be908a86349a04ef6a72d9511acaf1c1 @kristianpaul committed Dec 3, 2011
@@ -935,7 +935,7 @@ sysctl #(
.ninputs(7),
.noutputs(2),
.clk_freq(`CLOCK_FREQUENCY),
- .systemid(32'h11004D31) /* 1.1.0 final (0) on M1 */
+ .systemid(32'h12004D31) /* 1.2.0 final (0) on M1 */
) sysctl (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
@@ -15,6 +15,8 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+`define AUTO_ON
+
module standby(
input clk50,
@@ -84,6 +86,7 @@ BUFG b1(
.O(clk)
);
+`ifndef AUTO_ON
reg btn1_r0;
reg btn1_r;
reg btn2_r0;
@@ -111,6 +114,7 @@ end
reg [19:0] debounce_r;
always @(posedge clk) debounce_r <= debounce_r + 20'd1;
assign debounce = &debounce_r;
+`endif
reg ce_r;
reg [15:0] d_r;
@@ -179,27 +183,48 @@ always @(posedge clk, negedge locked)
else
state <= next_state;
+`ifndef AUTO_ON
reg rescue;
reg next_rescue;
always @(posedge clk, negedge locked)
if(~locked)
rescue <= 1'b0;
else
rescue <= next_rescue;
+`endif
+
+`ifdef AUTO_ON
+/* HACK: for some reason, reconfiguring right away fails intermittently.
+ * Work around this with a timer.
+ */
+reg [19:0] timer;
+always @(posedge clk, negedge locked)
+ if(~locked)
+ timer <= 20'd0;
+ else
+ timer <= timer + 20'd1;
+`endif
always @(*) begin
d = 16'hxxxx;
icap_en_n = 1'b1;
+`ifndef AUTO_ON
next_rescue = rescue;
+`endif
next_state = state;
case(state)
IDLE: begin
+`ifdef AUTO_ON
+ if(timer[19])
+ next_state = DUMMY;
+`else
next_rescue = btn1_r;
if(btn2_r & ~btn2_r2)
next_state = DUMMY;
+`endif
end
DUMMY: begin
d = 16'hffff;
@@ -229,7 +254,11 @@ always @(*) begin
GENERAL2_C: begin
d = 16'h3281;
icap_en_n = 1'b0;
+`ifdef AUTO_ON
+ if(btn1)
+`else
if(rescue)
+`endif
next_state = GENERAL2_D_RESCUE;
else
next_state = GENERAL2_D_REGULAR;
@@ -348,6 +348,7 @@ TIMESPEC "TSsdramout" = FROM FFS TO "GRPsdramout" 10 ns;
NET "vga/vga_iclk" TNM_NET = "GRPvga";
TIMESPEC "TSvga_async1" = FROM "GRPsys" TO "GRPvga" TIG;
TIMESPEC "TSvga_async2" = FROM "GRPvga" TO "GRPsys" TIG;
+OFFSET = OUT 5 ns AFTER "vga_clk";
TIMESPEC "TSac97_async1" = FROM "GRPsys" TO "GRPac97_clk" TIG;
TIMESPEC "TSac97_async2" = FROM "GRPac97_clk" TO "GRPsys" TIG;
@@ -96,7 +96,7 @@ always @(posedge usb_clk) begin
if(io_re)
rx_pending <= 1'b0;
end
- 6'h0a: io_do <= rx_pending;
+ 6'h0a: io_do <= { rx_pending, rx_active };
6'h0b: io_do <= rx_active;
6'h0c: begin
io_do <= rx_error_pending;
View
@@ -22,10 +22,12 @@
#define COMLOCV(x) (*(volatile unsigned char *)(x))
#define COMLOC_DEBUG_PRODUCE COMLOC(0x1000)
-#define COMLOC_DEBUG(offset) COMLOC(0x1001+offset)
+#define COMLOC_DEBUG(offset) COMLOC(0x1001+(offset))
#define COMLOC_MEVT_PRODUCE COMLOC(0x1101)
-#define COMLOC_MEVT(offset) COMLOC(0x1102+offset)
+#define COMLOC_MEVT(offset) COMLOC(0x1102+(offset))
#define COMLOC_KEVT_PRODUCE COMLOC(0x1142)
-#define COMLOC_KEVT(offset) COMLOC(0x1143+offset)
+#define COMLOC_KEVT(offset) COMLOC(0x1143+(offset))
+#define COMLOC_MIDI_PRODUCE COMLOC(0x1183)
+#define COMLOC_MIDI(offset) COMLOC(0x1184+(offset))
#endif /* __COMLOC_H */
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