Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
Browse files

namuru gnsssdr initial import

  • Loading branch information...
commit 13ca0cdd2c7a383e71ab2d72f006de3cdf0ba853 1 parent e2d56b8
Cristian Paul Peñaranda Rojas authored
1  .gitignore
View
@@ -10,6 +10,7 @@
*.swn
*.swo
*log*
+*.svn
boards/milkymist-one/synthesis/build
boards/milkymist-one/synthesis/build-rescue
boards/milkymist-one/standby/build
12 boards/milkymist-one/flash/Makefile
View
@@ -1,6 +1,6 @@
MMDIR?=../../..
-TARGETS=standby.fpg soc-rescue.fpg bios-rescue.bin splash-rescue.raw soc.fpg bios.bin splash.raw
+TARGETS=standby.fpg soc-rescue.fpg bios-rescue.bin splash-rescue.raw soc.fpg gps.bin bios.bin splash.raw
SERIAL?=/dev/ttyUSB0
all: $(TARGETS)
@@ -24,6 +24,7 @@ bios-rescue.bin:
$(MAKE) -C $(MMDIR)/software/libhal
$(MAKE) -C $(MMDIR)/software/libnet
$(MAKE) -C $(MMDIR)/software/bios
+ $(MAKE) -C $(MMDIR)/software/gps
cp $(MMDIR)/software/bios/bios-rescue.bin .
splash-rescue.raw: splash-rescue.png
@@ -43,6 +44,15 @@ bios.bin:
$(MAKE) -C $(MMDIR)/software/libnet
$(MAKE) -C $(MMDIR)/software/bios
cp $(MMDIR)/software/bios/bios.bin .
+
+gps.bin:
+ $(MAKE) -C $(MMDIR)/tools
+ $(MAKE) -C $(MMDIR)/software/libhpdmc
+ $(MAKE) -C $(MMDIR)/software/libbase
+ $(MAKE) -C $(MMDIR)/software/libhal
+ $(MAKE) -C $(MMDIR)/software/libnet
+ $(MAKE) -C $(MMDIR)/software/gps
+ cp $(MMDIR)/software/gps/gps.bin .
splash.raw: splash.png
$(MAKE) -C $(MMDIR)/tools
1  boards/milkymist-one/rtl/setup.v
View
@@ -33,6 +33,7 @@
//`define ENABLE_MIDI
//`define ENABLE_DMX
//`define ENABLE_IR
+`define ENABLE_CORRELATOR
`ifndef ENABLE_TMU
`define ENABLE_MEMTEST
40 boards/milkymist-one/rtl/system.v
View
@@ -141,7 +141,6 @@ module system(
input gps_rec_clk,
input gps_rec_sign,
input gps_rec_mag,
- //output gps_led,
// PCB revision
input [3:0] pcb_revision
@@ -379,7 +378,7 @@ wire norflash_ack,
conbus5x6 #(
.s0_addr(3'b000), // norflash
.s1_addr(3'b001), // debug
- .s2_addr(3'b010), // L1 GPS Correlator
+ .s2_addr(3'b010), // Namuru Correlator
.s3_addr(3'b011), // Ethernet
.s4_addr(2'b10), // SDRAM
.s5_addr(2'b11) // CSR
@@ -757,7 +756,7 @@ wire namuru_irq;
wire [31:0] cpu_interrupt;
assign cpu_interrupt = {16'd0,
- namuru_irq,
+ ~namuru_irq,
ir_irq,
midi_irq,
videoin_irq,
@@ -950,7 +949,7 @@ sysctl #(
.csr_do(csr_dr_sysctl),
.gpio_inputs({pcb_revision, btn3, btn2, btn1}),
- .gpio_outputs({led1}),
+ .gpio_outputs({led1,led2}),
.debug_write_lock(debug_write_lock),
.bus_errors_en(bus_errors_en),
@@ -1615,24 +1614,21 @@ FD workaround(
//---------------------------------------------------------------------------
// namuru GPS Correlator
//---------------------------------------------------------------------------
-namuru baseband (
- .sys_clk(sys_clk),
- .sys_rst(sys_rst),
-
- .wb_adr_i(namuru_adr),
- .wb_dat_o(namuru_dat_r),
- .wb_dat_i(namuru_dat_w),
- .wb_sel_i(namuru_sel),
- .wb_stb_i(namuru_stb),
- .wb_cyc_i(namuru_cyc),
- .wb_ack_o(namuru_ack),
- .wb_we_i(namuru_we),
-
-//// .gps_rec_clk(gps_rec_clk),
- .gps_rec_sign(gps_rec_sign),
- .gps_rec_mag(gps_rec_mag),
-
- .gps_led(led2)
+//
+simplified_gps_baseband corr(
+ .clk(sys_clk),
+ .hw_rstn(~sys_rst),
+ .sign(gps_rec_sign),
+ .mag(gps_rec_mag),
+ .wb_adr_i(namuru_adr),
+ .wb_dat_o(namuru_dat_r),
+ .wb_dat_i(namuru_dat_w),
+ .wb_sel_i(namuru_sel),
+ .wb_stb_i(namuru_stb),
+ .wb_cyc_i(namuru_cyc),
+ .wb_ack_o(namuru_ack),
+ .wb_we_i(namuru_we),
+ .accum_int(namuru_irq)
);
endmodule
81 cores/namuru/rtl/accumulator.v
View
@@ -0,0 +1,81 @@
+// -*- Mode: Verilog -*-
+// Filename : accumulator.v
+// Description : accumulate and dump process
+
+// Author : Peter Mumford, UNSW, 2005
+/*
+ carrier_mix_sign provides the sign.
+ 0 for negative, 1 for positive.
+ The three magnitude bits represent the values 1,2,3,6.
+
+ The code is 0 or 1 representing -1 or 1 respectively.
+
+ The multiplication of the carrier_mix and the code
+ is simply the carrier_mix_mag with the sign determined
+ from the multiplication of the carrier_mix sign and the code.
+
+ code 0 0 1 1
+ carrier_mix_sign 0 1 0 1
+ -------
+ result 1 0 0 1 (0 for -ve, 1 for +ve)
+
+ if (code == carrier_mix_sign) result = 1
+ else result = 0
+ */
+/*
+ Copyright (C) 2007 Peter Mumford
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+module accumulator (clk, rstn, sample_enable, code, carrier_mix_sign, carrier_mix_mag, dump_enable, accumulation);
+
+ input clk, rstn, sample_enable, dump_enable;
+ input carrier_mix_sign;
+ input [2:0] carrier_mix_mag;
+ input code;
+
+ //output [31:0] accumulation;
+ output [15:0] accumulation;
+
+ integer accum_i;
+ //reg [31:0] accumulation;
+ reg [15:0] accumulation;
+
+ always @ (posedge clk)
+ begin
+ if (!rstn)
+ begin
+ accumulation <= 0;
+ accum_i <= 0;
+ end
+ else if (dump_enable)
+ begin
+ //accumulation = accum_i; // buffer the accumultion... //xilinx ISE error!
+ accumulation <= accum_i; // buffer the accumultion...
+ //accum_i = 0; // then reset the accumulation
+ accum_i <= 0; // then reset the accumulation //xilinx ISE error!
+ end
+ else if (sample_enable) // 20 MHz rate
+ begin
+ if (code == carrier_mix_sign)
+ accum_i <= accum_i + carrier_mix_mag;
+ else
+ accum_i <= accum_i - carrier_mix_mag;
+ end
+ end // always @ (posedge clk)
+endmodule // accumulator
+
+
65 cores/namuru/rtl/carrier_mixer.v
View
@@ -0,0 +1,65 @@
+// -*- Mode: Verilog -*-
+// Filename : carrier_mixer.v
+// Description : Mix together the incomming signal with the local carrier.
+
+// Author : Peter Mumford, UNSW, 2005
+
+
+/*
+ The IF raw data and carrier are two bit quantities.
+ Each has a sign bit and a mag bit.
+ The IF_mag bit represents the values 1 and 3.
+ The carrier_mag bit represents the values 1 and 2.
+
+ The mix_mag is three bits representing the values 1,2,3,6
+ The mix_sign bit is 0 for negative, 1 for positive.
+
+ truth table
+
+ if_mag | 0 0 1 1 |
+ carrier_mag | 0 1 0 1 |
+ output bit:
+ 0 | 1 0 1 0 | = not carrier_mag
+
+ 1 | 0 1 1 1 | = if_mag or carrier_mag
+ 2 | 0 0 0 1 | = if_mag and carrier_mag
+ -------------|---------|
+ value | 1 2 3 6 |
+
+ if_sign | 0 0 1 1 | (0 = -ve, 1 = +ve)
+ carrier sign | 0 1 0 1 |
+ output sign:
+ | 1 0 0 1 | = not( if_sign xor carrier_sign )
+*/
+/*
+ Copyright (C) 2007 Peter Mumford
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+module carrier_mixer (if_sign, if_mag, carrier_sign, carrier_mag, mix_sign, mix_mag);
+
+input if_sign, if_mag, carrier_sign, carrier_mag;
+output mix_sign;
+output [2:0] mix_mag;
+
+assign mix_mag[0] = !carrier_mag;
+assign mix_mag[1] = if_mag | carrier_mag;
+assign mix_mag[2] = if_mag & carrier_mag;
+assign mix_sign = !(if_sign ^ carrier_sign);
+
+endmodule
+
+
230 cores/namuru/rtl/carrier_nco.v
View
@@ -0,0 +1,230 @@
+// -*- Mode: Verilog -*-
+// Filename : carrier_nco.v
+// Description : Generates the 8 stage carrier local oscilator.
+
+// Author : Peter Mumford, UNSW, 2005
+
+/*
+ Numerically Controlled Oscillator (NCO) which replicates the
+ carrier frequency. This pseudo-sinusoid waveform consists of
+ 8 stages or phases.
+
+ The NCO frequency is:
+
+ f = fControl * Clk / 2^N
+ where:
+ f = the required carrier wave frequency
+ Clk = the system clock (= 40MHz)
+ N = 30 (bit width of the phase accumulator)
+ fControl = the 30 bit (unsigned) control word
+
+ The generated waveforms for I & Q look like:
+ Phase : 0 1 2 3 4 5 6 7
+ ---------------------------------
+ I: -1 +1 +2 +2 +1 -1 -2 -2
+ Q: +2 +2 +1 -1 -2 -2 -1 +1
+
+ The nominal center frequency for the GP2015 is:
+ IF = 1.405396825MHz
+ Clk = 40 MHz
+ fControl = 2^N * IF / Clk
+ fControl = 0x23FA689 for center frequency
+
+ Resolution:
+ fControl increment value = 0.037252902 Hz
+ Put another way:
+ 37mHz is the smallest change in carrier frequency possible
+ with this NCO.
+
+ The carrier phase and carrier cycle count are latched into
+ the carrier_val on the tic_enable. The carrier phase is the
+ 10 msb of the accumulator register (accum_reg). The cycle count
+ is the number of full carrier wave cycles between the last 2
+ tic_enables. The two values are combined into the carrier_val.
+ Bits 9:0 are the carrier phase, bits 31:10 are the cycle count.
+ */
+/*
+ Copyright (C) 2007 Peter Mumford
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+module carrier_nco (clk, rstn, tic_enable, f_control, carrier_val, i_sign, i_mag, q_sign, q_mag);
+
+ input clk, rstn, tic_enable;
+ input [28:0] f_control;
+ output reg [31:0] carrier_val;
+ output reg i_sign, i_mag; // in-phase (cosine) carrier wave
+ output reg q_sign, q_mag; // quadrature (sine) carrier wave
+
+ reg [29:0] accum_reg;
+ reg [21:0] cycle_count_reg;
+
+ wire [3:0] phase_key;
+ wire [30:0] accum_sum;
+ wire accum_carry;
+ wire [31:0] combined_carr_value;
+
+
+ // 30 bit phase accumulator
+ always @ (posedge clk)
+ begin
+ if (!rstn) accum_reg <= 0;
+ else accum_reg <= accum_sum[29:0];
+ end
+
+ assign accum_sum = accum_reg + f_control;
+ assign accum_carry = accum_sum[30];
+ assign phase_key = accum_sum[29:26];
+
+ assign combined_carr_value[9:0] = accum_reg[29:20];
+ assign combined_carr_value[31:10] = cycle_count_reg;
+
+ // cycle counter and value latching
+ always @ (posedge clk)
+ begin
+ if (!rstn) cycle_count_reg <= 0;
+ else if (tic_enable)
+ begin
+ carrier_val = combined_carr_value; // latch in carrier value, then...
+ //cycle_count_reg = 0; // reset counter //xilinx ISE error!
+ cycle_count_reg <= 0; // reset counter
+ end
+ else if (accum_carry)
+ cycle_count_reg <= cycle_count_reg + 1;
+ end
+
+ // look up table for carrier pseudo-sinewave generation
+ always @ (phase_key)
+ // ?? is there a way to have or'ed values in case statements ??
+ case (phase_key)
+ // 0 0 degrees
+ 15 : begin
+ i_sign <= 0;
+ i_mag <= 0;
+ q_sign <= 1;
+ q_mag <= 1;
+ end
+ 0 : begin
+ i_sign <= 0;
+ i_mag <= 0;
+ q_sign <= 1;
+ q_mag <= 1;
+ end
+
+ // 1 45 degrees
+ 1 : begin
+ i_sign <= 1;
+ i_mag <= 0;
+ q_sign <= 1;
+ q_mag <= 1;
+ end
+ 2 : begin
+ i_sign <= 1;
+ i_mag <= 0;
+ q_sign <= 1;
+ q_mag <= 1;
+ end
+
+ // 2 90 degrees
+ 3 : begin
+ i_sign <= 1;
+ i_mag <= 1;
+ q_sign <= 1;
+ q_mag <= 0;
+ end
+ 4 : begin
+ i_sign <= 1;
+ i_mag <= 1;
+ q_sign <= 1;
+ q_mag <= 0;
+ end
+
+ // 3 135 degrees
+ 5 : begin
+ i_sign <= 1;
+ i_mag <= 1;
+ q_sign <= 0;
+ q_mag <= 0;
+ end
+ 6 : begin
+ i_sign <= 1;
+ i_mag <= 1;
+ q_sign <= 0;
+ q_mag <= 0;
+ end
+
+ // 4 180 degrees
+ 7 : begin
+ i_sign <= 1;
+ i_mag <= 0;
+ q_sign <= 0;
+ q_mag <= 1;
+ end
+ 8 : begin
+ i_sign <= 1;
+ i_mag <= 0;
+ q_sign <= 0;
+ q_mag <= 1;
+ end
+
+ // 5 225 degrees
+ 9 : begin
+ i_sign <= 0;
+ i_mag <= 0;
+ q_sign <= 0;
+ q_mag <= 1;
+ end
+ 10 : begin
+ i_sign <= 0;
+ i_mag <= 0;
+ q_sign <= 0;
+ q_mag <= 1;
+ end
+
+ // 6 270 degrees
+ 11 : begin
+ i_sign <= 0;
+ i_mag <= 1;
+ q_sign <= 0;
+ q_mag <= 0;
+ end
+ 12 : begin
+ i_sign <= 0;
+ i_mag <= 1;
+ q_sign <= 0;
+ q_mag <= 0;
+ end
+
+ // 7 315 degrees
+ 13 : begin
+ i_sign <= 0;
+ i_mag <= 1;
+ q_sign <= 1;
+ q_mag <= 0;
+ end
+ 14 : begin
+ i_sign <= 0;
+ i_mag <= 1;
+ q_sign <= 1;
+ q_mag <= 0;
+ end
+ endcase // case(phase_key)
+endmodule // carrier_nco
+
+
+
+
+
253 cores/namuru/rtl/code_gen.v
View
@@ -0,0 +1,253 @@
+// -*- Mode: Verilog -*-
+// Filename : code_gen.v
+// Description : Generates early prompt and late C/A code chips.
+
+// Author : Peter Mumford, 2005, UNSW
+
+// Function : Generate the C/A code early, prompt and late chipping sequence.
+
+/*
+ Copyright (C) 2007 Peter Mumford
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+module code_gen (clk, rstn, tic_enable, hc_enable, prn_key_enable, prn_key, code_slew, slew_enable,
+ dump_enable, code_phase, early, prompt, late);
+
+ input clk, rstn;
+ input tic_enable; // the TIC
+ input hc_enable; // the half-chip enable pulse from the code_nco
+ input prn_key_enable; // pulse to latch in the prn_key and reset the logic (write & chip_select)
+ input slew_enable; // pulse to set the slew_flag (write & chip select)
+ input [9:0] prn_key; // 10 bit number used to select satellite PRN code
+ input [10:0] code_slew; // number of half chips to delay the C/A code after the next dump_enable
+
+ output dump_enable; // pulse at the begining/end of prompt C/A code cycle
+ output reg [10:0] code_phase;// the phase of the C/A code at the TIC
+ output early, prompt, late; // half-chip spaced C/A code sequences
+
+ reg [9:0] g1; // the g1 shift register
+ reg g1_q; // output of the g1 shift register
+ reg [9:0] g2; // the g2 shift register
+ reg g2_q; // output of the g2 shift register
+ wire ca_code; // the C/A code chip sequence from g1 and g2 shifters
+ wire [2:0] srq; // the output of the chip spreader
+
+ reg fc_enable; // full-chip enable that drives the g1 and g2 shifters
+ reg dump_enable; // pulse generated at the begining/end of the prompt C/A code cycle
+ reg [10:0] hc_count1; // counter used for generating the fc_enable and slew logic (max slew 2045)
+
+ reg [10:0] slew; // the code_slew latched if the slew_flag is set
+ reg [11:0] hc_count2; // counter for keeping track of the begining/end of C/A code cycle (max count 4091)
+ reg [11:0] max_count2; // limit of hc_count2, normally = 2045, but increased when slew delays the C/A code
+
+ //reg [1:0] dump = 3; // dump_enable is generated when hc_count2 = 3
+ reg slew_flag; // slew_flag is set on the slew_enable pulse and cleared on the dump_enable
+ reg slew_trigger; // triggers the slew event
+
+ reg [10:0] hc_count3; // this counter is reset at the dump_enable, latched into the code_phase on the TIC
+
+ //shift register GavAI implementation.
+ reg [2:0] shft_reg;
+
+
+
+ // chip spreader: shift register for generating early, prompt and late chips
+ //--------------------------------------------------------------------------
+ // Half a chip separates the early and prompt, and prompt and late codes.
+ /*lpm_shiftreg sr(
+ .clock(clk),
+ .sclr(prn_key_enable),
+ .enable(hc_enable),
+ .shiftin(ca_code),
+ .q(srq)
+ );
+
+ defparam sr.lpm_width= 3;*/
+
+ always @ (posedge clk)
+ begin
+ if (prn_key_enable) //clear register;
+ shft_reg <= 0;
+ else if (hc_enable) //make shifting here;
+ shft_reg <= {shft_reg[1:0], ca_code};
+ end
+ assign srq = shft_reg;
+
+ // The G1 shift register
+ //----------------------
+ always @ (posedge clk)
+ begin
+ if (prn_key_enable) // set up shift register
+ begin
+ g1_q <= 0;
+ g1 <= 10'b1111111111;
+ end
+ else if (fc_enable) // run
+ begin
+ g1_q <= g1[0];
+ g1 <= {(g1[7] ^ g1[0]), g1[9:1]};
+ end
+ end
+
+ // The G2 shift register
+ //----------------------
+ always @ (posedge clk)
+ begin
+ if (prn_key_enable) // set up shift register
+ begin
+ g2_q <= 0;
+ g2 <= prn_key;
+ end
+ else if (fc_enable) // run
+ begin
+ g2_q <= g2[0];
+ g2 <= {(g2[8] ^ g2[7] ^ g2[4] ^ g2[2] ^ g2[1] ^ g2[0]), g2[9:1]};
+ end
+ end
+
+ assign ca_code = g1_q ^ g2_q;
+
+ // assign the early, prompt and late chips, one half chip apart
+ assign early = srq[0];
+ assign prompt = srq[1];
+ assign late = srq[2];
+
+ // hc_count3 process
+ //------------------
+ // Counter 3 counts hc_enables, reset on dump_enable.
+ // If there is slew delay this counter will roll over
+ // before the next dump. However, code_phase measurements
+ // are not valid during slewing.
+ always @ (posedge clk)
+ begin
+ if (prn_key_enable || dump_enable)
+ hc_count3 <= 0;
+ else if (hc_enable)
+ hc_count3 <= hc_count3 + 1;
+ end
+
+ // capture the code phase at TIC
+ //------------------------------
+ // The code_phase is the half-chip count
+ // at the TIC. Half-chips are numbered 0 to 2045.
+ // The code_nco_phase (from the code_nco) provides
+ // the fine (sub half-chip) code phase.
+ always @ (posedge clk)
+ begin
+ if (tic_enable)
+ code_phase <= hc_count3;
+ end
+
+ // The full-chip enable generator
+ //--------------------------------
+ // Without the code_slew being set
+ // this process just creates the full-chip enable
+ // at half the rate of the half-chip enable.
+ // When the code_slew is set, the fc_enable
+ // is delayed for a number of half-chips.
+ always @ (posedge clk)
+ begin
+ if (prn_key_enable)
+ begin
+ hc_count1 <= 0;
+ fc_enable <= 0;
+ slew <= 0; // reset slew
+ end
+ else
+ begin
+ if (slew_trigger)
+ slew <= code_slew;
+ if (hc_enable)
+ begin
+ if (slew == 0) // no delay on code
+ begin
+ if (hc_count1 == 1)
+ begin
+ hc_count1 <= 0;
+ fc_enable <= 1; // create fc_enable pulse
+ end
+ else
+ hc_count1 <= hc_count1 + 1; // increment count
+ end
+ else
+ slew <= slew - 1; // decrement slew
+ end
+ else
+ fc_enable <= 0;
+ end
+ end
+
+ // The dump_enable generator
+ //--------------------------
+ // create the dump_enable
+ //
+ // When a slew value (= x) is written to the code_slew register,
+ // the C/A code is delayed x half-chips at the next dump.
+ always @ (posedge clk)
+ begin
+ if (prn_key_enable)
+ begin
+ dump_enable <= 0;
+ hc_count2 <= 0;
+ slew_trigger <= 0;
+ max_count2 <= 2045; // normal half-chip count in one C/A cycle
+ end
+
+ else if (hc_enable)
+ begin
+ hc_count2 <= hc_count2 + 1;
+ if (hc_count2 == 3)//dump)
+ dump_enable <= 1;
+ else if (hc_count2 == max_count2)
+ hc_count2 <= 0;
+ else if (hc_count2 == 1) // signals the arrival of the first hc_enable
+ begin
+ if (slew_flag) // slew delay
+ begin
+ slew_trigger <= 1;
+ max_count2 <= 2045 + code_slew;
+ end
+ else
+ max_count2 <= 2045;
+ end
+ end
+ else
+ begin
+ dump_enable <= 0;
+ slew_trigger <= 0;
+ end
+
+ end
+
+
+
+ // slew_flag process
+ //------------------
+ // The slew_flag is set on slew_enable and cleared on the dump_enable.
+ always @ (posedge clk)
+ begin
+ if (prn_key_enable)
+ slew_flag <= 0;
+ else if (slew_enable)
+ slew_flag <= 1;
+ else if (dump_enable)
+ slew_flag <= 0;
+ end
+
+endmodule // code_gen
+
+
102 cores/namuru/rtl/code_nco.v
View
@@ -0,0 +1,102 @@
+// -*- Mode: Verilog -*-
+// Filename : code_nco.v
+// Description : Generate the half-chip enable signal
+
+// Author : Peter Mumford, UNSW, 2005
+
+/*
+ The Code_NCO creates the half-chip enable signal.
+ This drives the C/A code generator at the required frequency
+ (nominally 1.023MHz). The frequency must be adjusted by the
+ application code to align the incomming signal with the
+ generated C/A code replica and to account for clock error
+ (TCXO frequency error) and doppler.
+
+ The code_NCO provides the fine code phase (10 bit) value on
+ the TIC signal.
+ Note 1) The full-chip enable (fc_enable) is generated in the code_gen
+ module and is not aligned with the hc_enable.
+ The C/A code chip boundaries align to the fc_enable
+ not the hc_enable. This implies that the fine code phase obtained
+ from the code_nco that generates the hc_enable will be early by
+ one clock cycle. To account for this, the pre_tic_enable is used to
+ latch the code NCO phase.
+
+ The NCO frequency is:
+
+ f = fControl * clk/2^N
+ where:
+ f = the required frequency
+ N = 29 (bit width of the phase accumulator)
+ clk = the system clock (= 40MHz)
+ fControl = the 28 bit (unsigned) control word
+
+ To generate the C/A code at f, the NCO must be set to run
+ at 2f, therefore:
+ code_frequency = 0.5 * fControl * clk/2^N
+
+ For a system clock running @ clk = 40 MHz:
+ fControl = code_frequency * 2^29 / 20[Mhz]
+
+ For code_frequency = 1.023MHz
+ fControl = 0x1A30552
+ */
+/*
+ Copyright (C) 2007 Peter Mumford
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+module code_nco (clk, rstn, tic_enable, f_control, hc_enable, code_nco_phase);
+
+ input clk, rstn, tic_enable;
+ input [27:0] f_control;
+ output reg hc_enable;
+ output reg [9:0] code_nco_phase;
+
+ reg [28:0] accum_reg;
+ wire [29:0] accum_sum;
+ wire accum_carry;
+
+ // 29 bit phase accumulator
+ always @ (posedge clk)
+ begin
+ if (!rstn) accum_reg <= 0;
+ else accum_reg <= accum_sum[28:0];
+ end
+
+ assign accum_sum = accum_reg + f_control;
+ assign accum_carry = accum_sum[29];
+
+ // latch the top 10 bits on the tic_enable
+ always @ (posedge clk)
+ begin
+ if (!rstn) code_nco_phase <= 0;
+ else if (tic_enable) code_nco_phase <= accum_reg[28:19]; // see note 1 above
+ end
+
+ // generate the half-chip enable
+ always @ (posedge clk)
+ begin
+ if (!rstn) hc_enable <= 0;
+ else if (accum_carry) hc_enable <= 1;
+ else hc_enable <= 0;
+ end
+
+endmodule // code_nco
+
+
+
+
102 cores/namuru/rtl/epoch_counter.v
View
@@ -0,0 +1,102 @@
+// -*- Mode: Verilog -*-
+// Filename : epoch_counter.v
+// Description : Count the C/A code cycles.
+
+// Author : Peter Mumford, UNSW, 2005
+
+/* C/A code cycles are counted by two counters;
+ the 1ms epoch counter (or cycle counter)
+ and the 20ms epoch counter (or bit counter).
+ The 1ms epoch counter counts C/A code cycles (by
+ counting dump_enable pulses) that occur every 1ms
+ from 0 to 19. This allows the tracking of the bit
+ boundaries in the broadcast message that occur every
+ 20ms. Every time this counter rolls over, the 20ms
+ epoch counter increments. The 20ms epoch counter
+ goes from 0 to 49 to allow tracking of the message
+ frame boundary.
+
+ The 1ms epoch count is 5 bits wide.
+ The 20ms count count is 6 bits wide.
+
+ The values are latched into epoch on the tic_enable.
+ The epoch_check is for instantaneous values used for finding
+ message bit flips.
+*/
+/*
+ Copyright (C) 2007 Peter Mumford
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+module epoch_counter (clk, rstn, tic_enable, dump_enable, epoch_enable, epoch_load, epoch, epoch_check);
+
+ input clk, rstn, tic_enable, dump_enable, epoch_enable;
+ input [10:0] epoch_load;
+ output reg [10:0] epoch;
+ output reg [10:0]epoch_check;
+
+ reg [4:0] cycle_count;
+ reg [5:0] bit_count;
+ wire cycle_count_overflow;
+
+// the 1ms epoch (C/A code cycle) counter
+ always @ (posedge clk)
+ begin
+ if (!rstn) cycle_count <= 0;
+ else if (epoch_enable)
+ cycle_count <= epoch_load[4:0];
+ else if (dump_enable)
+ begin
+ if (cycle_count_overflow) cycle_count <= 0;
+ else cycle_count <= cycle_count + 1;
+ end
+ end
+
+// look for the overflow
+ assign cycle_count_overflow = (cycle_count == 19)? 1:0;
+
+// the 20ms epoch (bit flip) counter
+ always @ (posedge clk)
+ begin
+ if (!rstn) bit_count <= 0;
+ else if (epoch_enable)
+ bit_count <= epoch_load[10:5];
+ else if (cycle_count_overflow & dump_enable)
+ begin
+ if (bit_count == 49) bit_count <= 0;
+ else bit_count <= bit_count + 1;
+ end
+ end
+
+// latch the epoch into a register
+ always @ (posedge clk)
+ begin
+ if (tic_enable)
+ begin
+ epoch[4:0] <= cycle_count;
+ epoch[10:5] <= bit_count;
+ end
+ end
+
+ always @ (posedge clk)
+ begin
+ epoch_check[4:0] <= cycle_count;
+ epoch_check[10:5] <= bit_count;
+ end
+
+endmodule // epoch_counter
+
+
1,057 cores/namuru/rtl/gps_baseband.v
View
@@ -0,0 +1,1057 @@
+// -*- Mode: Verilog -*-
+// Filename : gps_baseband.v
+// Description : top level, includes address decoder and X tracking channels
+// Author : Peter Mumford UNSW 2005
+
+// ----------------------------------------------------------------------------------------
+// fix log
+// ----------------------------------------------------------------------------------------
+// 2/3/07 : Peter Mumford
+// Fixed a problem when a new data read coincides or imediately
+// follows a dump pulse. In this case the new data flag for that channel is lost.
+// The fix involved capturing the dump state of all channels on a read of the
+// new data register and using it as a mask for the new data flags.
+// The following registers accomplish a two clock cycle wide mask function.
+// reg [11:0] dump_mask; // mask a channel that has a dump aligned with the new data read
+// reg [11:0] dump_mask_2; // mask for two clock cycles
+// ----------------------------------------------------------------------------------------
+
+/* This module connects to the Avalon bus
+
+ address map
+ block address offset
+ -------------------------
+ chan 0 00-0F
+ chan 1 10-1F
+ chan 2 20-2F
+ chan 3 30-3F
+ chan 4 40-4F
+ chan 5 50-5F
+ chan 6 60-6F
+ chan 7 70-7F
+ chan 8 80-8F
+ chan 9 90-9F
+ chan 10 A0-AF
+ chan 11 B0-BF
+ spare C0-CF
+ spare D0-DF
+ status E0-EF
+ control F0-FF
+
+ channel address offset
+ -------------------------
+ prn_key 0 write
+ carrier_nco 1 write
+ code_nco 2 write
+ code_slew 3 write
+ I_early 4 read
+ Q_early 5 read
+ I_prompt 6 read
+ Q_prompt 7 read
+ I_late 8 read
+ Q_late 9 read
+ carrier_val A read
+ code_val B read
+ epoch C read
+ epoch_check D read
+ spare E-F
+
+ status address offset
+ -------------------------
+ status 0 read
+ new_data 1 read
+ tic_count 2 read
+ accum_count 3 read
+ spare 4-F
+
+ control address offset
+ -------------------------
+ reset 0
+ prog_tic 1 write
+ prog_accum_int 2 write
+ spare 3-F
+
+ */
+
+module gps_baseband (clk, hw_rstn,
+ sign, mag,
+ chip_select, write, read,
+ address, write_data,
+ sample_clk, accum_int, read_data
+ );
+
+ input clk, hw_rstn, chip_select, write, read;
+ input sign, mag; // raw data in from RF front end
+ input [7:0] address;
+ input [31:0] write_data;
+ output sample_clk; // to drive RF front end sampler @ 40/7 MHz
+ output reg accum_int; // interrupt pulse to tell FW to collect accumulation data, cleared on STATUS read
+ output reg [31:0] read_data;
+
+ wire s_clk;
+ wire accum_enable_s;
+ wire pre_tic_enable, tic_enable, accum_sample_enable;
+
+ wire [23:0] tic_count;
+ wire [23:0] accum_count;
+
+ reg sw_rst; // reset to tracking module
+ wire rstn; // software generated reset
+
+ // channel 0 registers
+ reg [9:0] ch0_prn_key;
+ reg [28:0] ch0_carr_nco;
+ reg [27:0] ch0_code_nco;
+ reg [10:0] ch0_code_slew;
+ reg [10:0] ch0_epoch_load;
+ reg ch0_prn_key_enable, ch0_slew_enable, ch0_epoch_enable;
+ wire ch0_dump;
+ //wire [31:0] ch0_i_early, ch0_q_early, ch0_i_prompt, ch0_q_prompt, ch0_i_late, ch0_q_late;
+ wire [15:0] ch0_i_early, ch0_q_early, ch0_i_prompt, ch0_q_prompt, ch0_i_late, ch0_q_late;
+ wire [31:0] ch0_carrier_val;
+ wire [20:0] ch0_code_val;
+ wire [10:0] ch0_epoch, ch0_epoch_check;
+
+ // channel 1 registers
+ reg [9:0] ch1_prn_key;
+ reg [28:0] ch1_carr_nco;
+ reg [27:0] ch1_code_nco;
+ reg [10:0] ch1_code_slew;
+ reg [10:0] ch1_epoch_load;
+ reg ch1_prn_key_enable, ch1_slew_enable, ch1_epoch_enable;
+ wire ch1_dump;
+ //wire [31:0] ch1_i_early, ch1_q_early, ch1_i_prompt, ch1_q_prompt, ch1_i_late, ch1_q_late;
+ wire [15:0] ch1_i_early, ch1_q_early, ch1_i_prompt, ch1_q_prompt, ch1_i_late, ch1_q_late;
+ wire [31:0] ch1_carrier_val;
+ wire [20:0] ch1_code_val;
+ wire [10:0] ch1_epoch, ch1_epoch_check;
+
+ // channel 2 registers
+ reg [9:0] ch2_prn_key;
+ reg [28:0] ch2_carr_nco;
+ reg [27:0] ch2_code_nco;
+ reg [10:0] ch2_code_slew;
+ reg [10:0] ch2_epoch_load;
+ reg ch2_prn_key_enable, ch2_slew_enable, ch2_epoch_enable;
+ wire ch2_dump;
+ //wire [31:0] ch2_i_early, ch2_q_early, ch2_i_prompt, ch2_q_prompt, ch2_i_late, ch2_q_late;
+ wire [15:0] ch2_i_early, ch2_q_early, ch2_i_prompt, ch2_q_prompt, ch2_i_late, ch2_q_late;
+ wire [31:0] ch2_carrier_val;
+ wire [20:0] ch2_code_val;
+ wire [10:0] ch2_epoch, ch2_epoch_check;
+
+ // channel 3 registers
+ reg [9:0] ch3_prn_key;
+ reg [28:0] ch3_carr_nco;
+ reg [27:0] ch3_code_nco;
+ reg [10:0] ch3_code_slew;
+ reg [10:0] ch3_epoch_load;
+ reg ch3_prn_key_enable, ch3_slew_enable, ch3_epoch_enable;
+ wire ch3_dump;
+ //wire [31:0] ch3_i_early, ch3_q_early, ch3_i_prompt, ch3_q_prompt, ch3_i_late, ch3_q_late;
+ wire [15:0] ch3_i_early, ch3_q_early, ch3_i_prompt, ch3_q_prompt, ch3_i_late, ch3_q_late;
+ wire [31:0] ch3_carrier_val;
+ wire [20:0] ch3_code_val;
+ wire [10:0] ch3_epoch, ch3_epoch_check;
+
+ // channel 4 registers
+ reg [9:0] ch4_prn_key;
+ reg [28:0] ch4_carr_nco;
+ reg [27:0] ch4_code_nco;
+ reg [10:0] ch4_code_slew;
+ reg [10:0] ch4_epoch_load;
+ reg ch4_prn_key_enable, ch4_slew_enable, ch4_epoch_enable;
+ wire ch4_dump;
+ //wire [31:0] ch4_i_early, ch4_q_early, ch4_i_prompt, ch4_q_prompt, ch4_i_late, ch4_q_late;
+ wire [15:0] ch4_i_early, ch4_q_early, ch4_i_prompt, ch4_q_prompt, ch4_i_late, ch4_q_late;
+ wire [31:0] ch4_carrier_val;
+ wire [20:0] ch4_code_val;
+ wire [10:0] ch4_epoch, ch4_epoch_check;
+
+ // channel 5 registers
+ reg [9:0] ch5_prn_key;
+ reg [28:0] ch5_carr_nco;
+ reg [27:0] ch5_code_nco;
+ reg [10:0] ch5_code_slew;
+ reg [10:0] ch5_epoch_load;
+ reg ch5_prn_key_enable, ch5_slew_enable, ch5_epoch_enable;
+ wire ch5_dump;
+ //wire [31:0] ch5_i_early, ch5_q_early, ch5_i_prompt, ch5_q_prompt, ch5_i_late, ch5_q_late;
+ wire [15:0] ch5_i_early, ch5_q_early, ch5_i_prompt, ch5_q_prompt, ch5_i_late, ch5_q_late;
+ wire [31:0] ch5_carrier_val;
+ wire [20:0] ch5_code_val;
+ wire [10:0] ch5_epoch, ch5_epoch_check;
+
+ // channel 6 registers
+ reg [9:0] ch6_prn_key;
+ reg [28:0] ch6_carr_nco;
+ reg [27:0] ch6_code_nco;
+ reg [10:0] ch6_code_slew;
+ reg [10:0] ch6_epoch_load;
+ reg ch6_prn_key_enable, ch6_slew_enable, ch6_epoch_enable;
+ wire ch6_dump;
+ //wire [31:0] ch6_i_early, ch6_q_early, ch6_i_prompt, ch6_q_prompt, ch6_i_late, ch6_q_late;
+ wire [15:0] ch6_i_early, ch6_q_early, ch6_i_prompt, ch6_q_prompt, ch6_i_late, ch6_q_late;
+ wire [31:0] ch6_carrier_val;
+ wire [20:0] ch6_code_val;
+ wire [10:0] ch6_epoch, ch6_epoch_check;
+
+ // channel 7 registers
+ reg [9:0] ch7_prn_key;
+ reg [28:0] ch7_carr_nco;
+ reg [27:0] ch7_code_nco;
+ reg [10:0] ch7_code_slew;
+ reg [10:0] ch7_epoch_load;
+ reg ch7_prn_key_enable, ch7_slew_enable, ch7_epoch_enable;
+ wire ch7_dump;
+ //wire [31:0] ch7_i_early, ch7_q_early, ch7_i_prompt, ch7_q_prompt, ch7_i_late, ch7_q_late;
+ wire [15:0] ch7_i_early, ch7_q_early, ch7_i_prompt, ch7_q_prompt, ch7_i_late, ch7_q_late;
+ wire [31:0] ch7_carrier_val;
+ wire [20:0] ch7_code_val;
+ wire [10:0] ch7_epoch, ch7_epoch_check;
+
+ // channel 8 registers
+ reg [9:0] ch8_prn_key;
+ reg [28:0] ch8_carr_nco;
+ reg [27:0] ch8_code_nco;
+ reg [10:0] ch8_code_slew;
+ reg [10:0] ch8_epoch_load;
+ reg ch8_prn_key_enable, ch8_slew_enable, ch8_epoch_enable;
+ wire ch8_dump;
+ //wire [31:0] ch8_i_early, ch8_q_early, ch8_i_prompt, ch8_q_prompt, ch8_i_late, ch8_q_late;
+ wire [15:0] ch8_i_early, ch8_q_early, ch8_i_prompt, ch8_q_prompt, ch8_i_late, ch8_q_late;
+ wire [31:0] ch8_carrier_val;
+ wire [20:0] ch8_code_val;
+ wire [10:0] ch8_epoch, ch8_epoch_check;
+
+ // channel 9 registers
+ reg [9:0] ch9_prn_key;
+ reg [28:0] ch9_carr_nco;
+ reg [27:0] ch9_code_nco;
+ reg [10:0] ch9_code_slew;
+ reg [10:0] ch9_epoch_load;
+ reg ch9_prn_key_enable, ch9_slew_enable, ch9_epoch_enable;
+ wire ch9_dump;
+ //wire [31:0] ch9_i_early, ch9_q_early, ch9_i_prompt, ch9_q_prompt, ch9_i_late, ch9_q_late;
+ wire [15:0] ch9_i_early, ch9_q_early, ch9_i_prompt, ch9_q_prompt, ch9_i_late, ch9_q_late;
+ wire [31:0] ch9_carrier_val;
+ wire [20:0] ch9_code_val;
+ wire [10:0] ch9_epoch, ch9_epoch_check;
+
+ // channel 10 registers
+ reg [9:0] ch10_prn_key;
+ reg [28:0] ch10_carr_nco;
+ reg [27:0] ch10_code_nco;
+ reg [10:0] ch10_code_slew;
+ reg [10:0] ch10_epoch_load;
+ reg ch10_prn_key_enable, ch10_slew_enable, ch10_epoch_enable;
+ wire ch10_dump;
+ //wire [31:0] ch10_i_early, ch10_q_early, ch10_i_prompt, ch10_q_prompt, ch10_i_late, ch10_q_late;
+ wire [15:0] ch10_i_early, ch10_q_early, ch10_i_prompt, ch10_q_prompt, ch10_i_late, ch10_q_late;
+ wire [31:0] ch10_carrier_val;
+ wire [20:0] ch10_code_val;
+ wire [10:0] ch10_epoch, ch10_epoch_check;
+
+ // channel 11 registers
+ reg [9:0] ch11_prn_key;
+ reg [28:0] ch11_carr_nco;
+ reg [27:0] ch11_code_nco;
+ reg [10:0] ch11_code_slew;
+ reg [10:0] ch11_epoch_load;
+ reg ch11_prn_key_enable, ch11_slew_enable, ch11_epoch_enable;
+ wire ch11_dump;
+ //wire [31:0] ch11_i_early, ch11_q_early, ch11_i_prompt, ch11_q_prompt, ch11_i_late, ch11_q_late;
+ wire [15:0] ch11_i_early, ch11_q_early, ch11_i_prompt, ch11_q_prompt, ch11_i_late, ch11_q_late;
+ wire [31:0] ch11_carrier_val;
+ wire [20:0] ch11_code_val;
+ wire [10:0] ch11_epoch, ch11_epoch_check;
+
+ // status registers
+ reg [1:0] status; // TIC = bit 0, ACCUM_INT = bit 1, cleared on read
+ reg status_read; // pulse when status register is read
+ reg [11:0] new_data; // chan0 = bit 0, chan1 = bit 1 etc, cleared on read
+ reg new_data_read; // pules when new_data register is read
+ reg [11:0] dump_mask; // mask a channel that has a dump aligned with the new data read
+ reg [11:0] dump_mask_2; // mask for two clock cycles
+
+ // control registers
+ reg [23:0] prog_tic;
+ reg [23:0] prog_accum_int;
+
+ // connect up time base
+ time_base tb (.clk(clk), .rstn(rstn),
+ .tic_divide(prog_tic),
+ .accum_divide(prog_accum_int),
+ //.sample_clk(s_clk),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .accum_enable(accum_enable_s),
+ .accum_sample_enable(accum_sample_enable),
+ .tic_count(tic_count),
+ .accum_count(accum_count)
+ );
+
+ assign sample_clk = s_clk;
+ assign rstn = hw_rstn & ~sw_rst;
+
+ // connect up tracking channels
+ tracking_channel tc0 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch0_carr_nco),
+ .code_nco_fc(ch0_code_nco),
+ .prn_key(ch0_prn_key),
+ .prn_key_enable(ch0_prn_key_enable),
+ .code_slew(ch0_code_slew),
+ .slew_enable(ch0_slew_enable),
+ .epoch_enable(ch0_epoch_enable),
+ .dump(ch0_dump),
+ .i_early(ch0_i_early),
+ .q_early(ch0_q_early),
+ .i_prompt(ch0_i_prompt),
+ .q_prompt(ch0_q_prompt),
+ .i_late(ch0_i_late),
+ .q_late(ch0_q_late),
+ .carrier_val(ch0_carrier_val),
+ .code_val(ch0_code_val),
+ .epoch_load(ch0_epoch_load),
+ .epoch(ch0_epoch),
+ .epoch_check(ch0_epoch_check));
+
+ tracking_channel tc1 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch1_carr_nco),
+ .code_nco_fc(ch1_code_nco),
+ .prn_key(ch1_prn_key),
+ .prn_key_enable(ch1_prn_key_enable),
+ .code_slew(ch1_code_slew),
+ .slew_enable(ch1_slew_enable),
+ .epoch_enable(ch1_epoch_enable),
+ .dump(ch1_dump),
+ .i_early(ch1_i_early),
+ .q_early(ch1_q_early),
+ .i_prompt(ch1_i_prompt),
+ .q_prompt(ch1_q_prompt),
+ .i_late(ch1_i_late),
+ .q_late(ch1_q_late),
+ .carrier_val(ch1_carrier_val),
+ .code_val(ch1_code_val),
+ .epoch_load(ch1_epoch_load),
+ .epoch(ch1_epoch),
+ .epoch_check(ch1_epoch_check));
+
+ tracking_channel tc2 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch2_carr_nco),
+ .code_nco_fc(ch2_code_nco),
+ .prn_key(ch2_prn_key),
+ .prn_key_enable(ch2_prn_key_enable),
+ .code_slew(ch2_code_slew),
+ .slew_enable(ch2_slew_enable),
+ .epoch_enable(ch2_epoch_enable),
+ .dump(ch2_dump),
+ .i_early(ch2_i_early),
+ .q_early(ch2_q_early),
+ .i_prompt(ch2_i_prompt),
+ .q_prompt(ch2_q_prompt),
+ .i_late(ch2_i_late),
+ .q_late(ch2_q_late),
+ .carrier_val(ch2_carrier_val),
+ .code_val(ch2_code_val),
+ .epoch_load(ch2_epoch_load),
+ .epoch(ch2_epoch),
+ .epoch_check(ch2_epoch_check));
+
+ tracking_channel tc3 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch3_carr_nco),
+ .code_nco_fc(ch3_code_nco),
+ .prn_key(ch3_prn_key),
+ .prn_key_enable(ch3_prn_key_enable),
+ .code_slew(ch3_code_slew),
+ .slew_enable(ch3_slew_enable),
+ .epoch_enable(ch3_epoch_enable),
+ .dump(ch3_dump),
+ .i_early(ch3_i_early),
+ .q_early(ch3_q_early),
+ .i_prompt(ch3_i_prompt),
+ .q_prompt(ch3_q_prompt),
+ .i_late(ch3_i_late),
+ .q_late(ch3_q_late),
+ .carrier_val(ch3_carrier_val),
+ .code_val(ch3_code_val),
+ .epoch_load(ch3_epoch_load),
+ .epoch(ch3_epoch),
+ .epoch_check(ch3_epoch_check));
+
+ tracking_channel tc4 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch4_carr_nco),
+ .code_nco_fc(ch4_code_nco),
+ .prn_key(ch4_prn_key),
+ .prn_key_enable(ch4_prn_key_enable),
+ .code_slew(ch4_code_slew),
+ .slew_enable(ch4_slew_enable),
+ .epoch_enable(ch4_epoch_enable),
+ .dump(ch4_dump),
+ .i_early(ch4_i_early),
+ .q_early(ch4_q_early),
+ .i_prompt(ch4_i_prompt),
+ .q_prompt(ch4_q_prompt),
+ .i_late(ch4_i_late),
+ .q_late(ch4_q_late),
+ .carrier_val(ch4_carrier_val),
+ .code_val(ch4_code_val),
+ .epoch_load(ch4_epoch_load),
+ .epoch(ch4_epoch),
+ .epoch_check(ch4_epoch_check));
+
+ tracking_channel tc5 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch5_carr_nco),
+ .code_nco_fc(ch5_code_nco),
+ .prn_key(ch5_prn_key),
+ .prn_key_enable(ch5_prn_key_enable),
+ .code_slew(ch5_code_slew),
+ .slew_enable(ch5_slew_enable),
+ .epoch_enable(ch5_epoch_enable),
+ .dump(ch5_dump),
+ .i_early(ch5_i_early),
+ .q_early(ch5_q_early),
+ .i_prompt(ch5_i_prompt),
+ .q_prompt(ch5_q_prompt),
+ .i_late(ch5_i_late),
+ .q_late(ch5_q_late),
+ .carrier_val(ch5_carrier_val),
+ .code_val(ch5_code_val),
+ .epoch_load(ch5_epoch_load),
+ .epoch(ch5_epoch),
+ .epoch_check(ch5_epoch_check));
+
+ tracking_channel tc6 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch6_carr_nco),
+ .code_nco_fc(ch6_code_nco),
+ .prn_key(ch6_prn_key),
+ .prn_key_enable(ch6_prn_key_enable),
+ .code_slew(ch6_code_slew),
+ .slew_enable(ch6_slew_enable),
+ .epoch_enable(ch6_epoch_enable),
+ .dump(ch6_dump),
+ .i_early(ch6_i_early),
+ .q_early(ch6_q_early),
+ .i_prompt(ch6_i_prompt),
+ .q_prompt(ch6_q_prompt),
+ .i_late(ch6_i_late),
+ .q_late(ch6_q_late),
+ .carrier_val(ch6_carrier_val),
+ .code_val(ch6_code_val),
+ .epoch_load(ch6_epoch_load),
+ .epoch(ch6_epoch),
+ .epoch_check(ch6_epoch_check));
+
+ tracking_channel tc7 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch7_carr_nco),
+ .code_nco_fc(ch7_code_nco),
+ .prn_key(ch7_prn_key),
+ .prn_key_enable(ch7_prn_key_enable),
+ .code_slew(ch7_code_slew),
+ .slew_enable(ch7_slew_enable),
+ .epoch_enable(ch7_epoch_enable),
+ .dump(ch7_dump),
+ .i_early(ch7_i_early),
+ .q_early(ch7_q_early),
+ .i_prompt(ch7_i_prompt),
+ .q_prompt(ch7_q_prompt),
+ .i_late(ch7_i_late),
+ .q_late(ch7_q_late),
+ .carrier_val(ch7_carrier_val),
+ .code_val(ch7_code_val),
+ .epoch_load(ch7_epoch_load),
+ .epoch(ch7_epoch),
+ .epoch_check(ch7_epoch_check));
+
+ tracking_channel tc8 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch8_carr_nco),
+ .code_nco_fc(ch8_code_nco),
+ .prn_key(ch8_prn_key),
+ .prn_key_enable(ch8_prn_key_enable),
+ .code_slew(ch8_code_slew),
+ .slew_enable(ch8_slew_enable),
+ .epoch_enable(ch8_epoch_enable),
+ .dump(ch8_dump),
+ .i_early(ch8_i_early),
+ .q_early(ch8_q_early),
+ .i_prompt(ch8_i_prompt),
+ .q_prompt(ch8_q_prompt),
+ .i_late(ch8_i_late),
+ .q_late(ch8_q_late),
+ .carrier_val(ch8_carrier_val),
+ .code_val(ch8_code_val),
+ .epoch_load(ch8_epoch_load),
+ .epoch(ch8_epoch),
+ .epoch_check(ch8_epoch_check));
+
+ tracking_channel tc9 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch9_carr_nco),
+ .code_nco_fc(ch9_code_nco),
+ .prn_key(ch9_prn_key),
+ .prn_key_enable(ch9_prn_key_enable),
+ .code_slew(ch9_code_slew),
+ .slew_enable(ch9_slew_enable),
+ .epoch_enable(ch9_epoch_enable),
+ .dump(ch9_dump),
+ .i_early(ch9_i_early),
+ .q_early(ch9_q_early),
+ .i_prompt(ch9_i_prompt),
+ .q_prompt(ch9_q_prompt),
+ .i_late(ch9_i_late),
+ .q_late(ch9_q_late),
+ .carrier_val(ch9_carrier_val),
+ .code_val(ch9_code_val),
+ .epoch_load(ch9_epoch_load),
+ .epoch(ch9_epoch),
+ .epoch_check(ch9_epoch_check));
+
+ tracking_channel tc10 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch10_carr_nco),
+ .code_nco_fc(ch10_code_nco),
+ .prn_key(ch10_prn_key),
+ .prn_key_enable(ch10_prn_key_enable),
+ .code_slew(ch10_code_slew),
+ .slew_enable(ch10_slew_enable),
+ .epoch_enable(ch10_epoch_enable),
+ .dump(ch10_dump),
+ .i_early(ch10_i_early),
+ .q_early(ch10_q_early),
+ .i_prompt(ch10_i_prompt),
+ .q_prompt(ch10_q_prompt),
+ .i_late(ch10_i_late),
+ .q_late(ch10_q_late),
+ .carrier_val(ch10_carrier_val),
+ .code_val(ch10_code_val),
+ .epoch_load(ch10_epoch_load),
+ .epoch(ch10_epoch),
+ .epoch_check(ch10_epoch_check));
+
+ tracking_channel tc11 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch11_carr_nco),
+ .code_nco_fc(ch11_code_nco),
+ .prn_key(ch11_prn_key),
+ .prn_key_enable(ch11_prn_key_enable),
+ .code_slew(ch11_code_slew),
+ .slew_enable(ch11_slew_enable),
+ .epoch_enable(ch11_epoch_enable),
+ .dump(ch11_dump),
+ .i_early(ch11_i_early),
+ .q_early(ch11_q_early),
+ .i_prompt(ch11_i_prompt),
+ .q_prompt(ch11_q_prompt),
+ .i_late(ch11_i_late),
+ .q_late(ch11_q_late),
+ .carrier_val(ch11_carrier_val),
+ .code_val(ch11_code_val),
+ .epoch_load(ch11_epoch_load),
+ .epoch(ch11_epoch),
+ .epoch_check(ch11_epoch_check));
+
+ // address decoder ----------------------------------
+
+ always @ (posedge clk)
+ begin
+ if (!hw_rstn)
+ begin
+ // Need to initialize nco's (at least for simulation) or they don't run.
+ ch0_carr_nco <= 0;
+ ch0_code_nco <= 0;
+ ch1_carr_nco <= 0;
+ ch1_code_nco <= 0;
+ ch2_carr_nco <= 0;
+ ch2_code_nco <= 0;
+ ch3_carr_nco <= 0;
+ ch3_code_nco <= 0;
+ ch4_carr_nco <= 0;
+ ch4_code_nco <= 0;
+ ch5_carr_nco <= 0;
+ ch5_code_nco <= 0;
+ ch6_carr_nco <= 0;
+ ch6_code_nco <= 0;
+ ch7_carr_nco <= 0;
+ ch7_code_nco <= 0;
+ ch8_carr_nco <= 0;
+ ch8_code_nco <= 0;
+ ch9_carr_nco <= 0;
+ ch9_code_nco <= 0;
+ ch10_carr_nco <= 0;
+ ch10_code_nco <= 0;
+ ch11_carr_nco <= 0;
+ ch11_code_nco <= 0;
+ // Anything else need initializing here?
+ end
+ else
+
+ case (address)
+ // channel 0
+ 8'h00 : begin
+ ch0_prn_key_enable <= write & chip_select;
+ if (write & chip_select) ch0_prn_key <= write_data[9:0];
+ end
+ 8'h01 : if (write & chip_select) ch0_carr_nco <= write_data[28:0];
+ 8'h02 : if (write & chip_select) ch0_code_nco <= write_data[27:0];
+ 8'h03 : begin
+ ch0_slew_enable <= write & chip_select;
+ if (write & chip_select) ch0_code_slew <= write_data[10:0];
+ end
+ 8'h04 : read_data <= {16'h0, ch0_i_early};
+ 8'h05 : read_data <= {16'h0, ch0_q_early};
+ 8'h06 : read_data <= {16'h0, ch0_i_prompt};
+ 8'h07 : read_data <= {16'h0, ch0_q_prompt};
+ 8'h08 : read_data <= {16'h0, ch0_i_late};
+ 8'h09 : read_data <= {16'h0, ch0_q_late};
+ 8'h0A : read_data <= ch0_carrier_val; // 32 bits
+ 8'h0B : read_data <= {11'h0, ch0_code_val}; // 21 bits
+ 8'h0C : read_data <= {21'h0, ch0_epoch}; // 11 bits
+ 8'h0D : read_data <= {21'h0, ch0_epoch_check}; // 11 bits
+ 8'h0E : begin
+ ch0_epoch_enable <= write & chip_select;
+ if (write & chip_select) ch0_epoch_load <= write_data[10:0];
+ end
+
+ // channel 1
+ 8'h10 : begin
+ ch1_prn_key_enable <= write & chip_select;
+ if (write & chip_select) ch1_prn_key <= write_data[9:0];
+ end
+ 8'h11 : if (write & chip_select) ch1_carr_nco <= write_data[28:0];
+ 8'h12 : if (write & chip_select) ch1_code_nco <= write_data[27:0];
+ 8'h13 : begin
+ ch1_slew_enable <= write & chip_select;
+ if (write & chip_select) ch1_code_slew <= write_data[10:0];
+ end
+ 8'h14 : read_data <= {16'h0, ch1_i_early};
+ 8'h15 : read_data <= {16'h0, ch1_q_early};
+ 8'h16 : read_data <= {16'h0, ch1_i_prompt};
+ 8'h17 : read_data <= {16'h0, ch1_q_prompt};
+ 8'h18 : read_data <= {16'h0, ch1_i_late};
+ 8'h19 : read_data <= {16'h0, ch1_q_late};
+ 8'h1A : read_data <= ch1_carrier_val; // 32 bits
+ 8'h1B : read_data <= {11'h0, ch1_code_val}; // 21 bits
+ 8'h1C : read_data <= {21'h0, ch1_epoch}; // 11 bits
+ 8'h1D : read_data <= {21'h0, ch1_epoch_check};
+ 8'h1E : begin
+ ch1_epoch_enable <= write & chip_select;
+ if (write & chip_select) ch1_epoch_load <= write_data[10:0];
+ end
+
+ // channel 2
+ 8'h20 : begin
+ ch2_prn_key_enable <= write & chip_select;
+ if (write & chip_select) ch2_prn_key <= write_data[9:0];
+ end
+ 8'h21 : if (write & chip_select) ch2_carr_nco <= write_data[28:0];
+ 8'h22 : if (write & chip_select) ch2_code_nco <= write_data[27:0];
+ 8'h23 : begin
+ ch2_slew_enable <= write & chip_select;
+ if (write & chip_select) ch2_code_slew <= write_data[10:0];
+ end
+ 8'h24 : read_data <= {16'h0, ch2_i_early};
+ 8'h25 : read_data <= {16'h0, ch2_q_early};
+ 8'h26 : read_data <= {16'h0, ch2_i_prompt};
+ 8'h27 : read_data <= {16'h0, ch2_q_prompt};
+ 8'h28 : read_data <= {16'h0, ch2_i_late};
+ 8'h29 : read_data <= {16'h0, ch2_q_late};
+ 8'h2A : read_data <= ch2_carrier_val; // 32 bits
+ 8'h2B : read_data <= {11'h0, ch2_code_val}; // 21 bits
+ 8'h2C : read_data <= {21'h0, ch2_epoch}; // 11 bits
+ 8'h2D : read_data <= {21'h0, ch2_epoch_check};
+ 8'h2E : begin
+ ch2_epoch_enable <= write & chip_select;
+ if (write & chip_select) ch2_epoch_load <= write_data[10:0];
+ end
+
+ // channel 3
+ 8'h30 : begin
+ ch3_prn_key_enable <= write & chip_select;
+ if (write & chip_select) ch3_prn_key <= write_data[9:0];
+ end
+ 8'h31 : if (write & chip_select) ch3_carr_nco <= write_data[28:0];
+ 8'h32 : if (write & chip_select) ch3_code_nco <= write_data[27:0];
+ 8'h33 : begin
+ ch3_slew_enable <= write & chip_select;
+ if (write & chip_select) ch3_code_slew <= write_data[10:0];
+ end
+ 8'h34 : read_data <= {16'h0, ch3_i_early};
+ 8'h35 : read_data <= {16'h0, ch3_q_early};
+ 8'h36 : read_data <= {16'h0, ch3_i_prompt};
+ 8'h37 : read_data <= {16'h0, ch3_q_prompt};
+ 8'h38 : read_data <= {16'h0, ch3_i_late};
+ 8'h39 : read_data <= {16'h0, ch3_q_late};
+ 8'h3A : read_data <= ch3_carrier_val; // 32 bits
+ 8'h3B : read_data <= {11'h0, ch3_code_val}; // 21 bits
+ 8'h3C : read_data <= {21'h0, ch3_epoch}; // 11 bits
+ 8'h3D : read_data <= {21'h0, ch3_epoch_check};
+ 8'h3E : begin
+ ch3_epoch_enable <= write & chip_select;
+ if (write & chip_select) ch3_epoch_load <= write_data[10:0];
+ end
+
+ // channel 4
+ 8'h40 : begin
+ ch4_prn_key_enable <= write & chip_select;
+ if (write & chip_select) ch4_prn_key <= write_data[9:0];
+ end
+ 8'h41 : if (write & chip_select) ch4_carr_nco <= write_data[28:0];
+ 8'h42 : if (write & chip_select) ch4_code_nco <= write_data[27:0];
+ 8'h43 : begin
+ ch4_slew_enable <= write & chip_select;
+ if (write & chip_select) ch4_code_slew <= write_data[10:0];
+ end
+ 8'h44 : read_data <= {16'h0, ch4_i_early};
+ 8'h45 : read_data <= {16'h0, ch4_q_early};
+ 8'h46 : read_data <= {16'h0, ch4_i_prompt};
+ 8'h47 : read_data <= {16'h0, ch4_q_prompt};
+ 8'h48 : read_data <= {16'h0, ch4_i_late};
+ 8'h49 : read_data <= {16'h0, ch4_q_late};
+ 8'h4A : read_data <= ch4_carrier_val; // 32 bits
+ 8'h4B : read_data <= {11'h0, ch4_code_val}; // 21 bits
+ 8'h4C : read_data <= {21'h0, ch4_epoch}; // 11 bits
+ 8'h4D : read_data <= {21'h0, ch4_epoch_check};
+ 8'h4E : begin
+ ch4_epoch_enable <= write & chip_select;
+ if (write & chip_select) ch4_epoch_load <= write_data[10:0];
+ end
+
+ // channel 5
+ 8'h50 : begin
+ ch5_prn_key_enable <= write & chip_select;
+ if (write & chip_select) ch5_prn_key <= write_data[9:0];
+ end
+ 8'h51 : if (write & chip_select) ch5_carr_nco <= write_data[28:0];
+ 8'h52 : if (write & chip_select) ch5_code_nco <= write_data[27:0];
+ 8'h53 : begin
+ ch5_slew_enable <= write & chip_select;
+ if (write & chip_select) ch5_code_slew <= write_data[10:0];
+ end
+ 8'h54 : read_data <= {16'h0, ch5_i_early};
+ 8'h55 : read_data <= {16'h0, ch5_q_early};
+ 8'h56 : read_data <= {16'h0, ch5_i_prompt};
+ 8'h57 : read_data <= {16'h0, ch5_q_prompt};
+ 8'h58 : read_data <= {16'h0, ch5_i_late};
+ 8'h59 : read_data <= {16'h0, ch5_q_late};
+ 8'h5A : read_data <= ch5_carrier_val; // 32 bits
+ 8'h5B : read_data <= {11'h0, ch5_code_val}; // 21 bits
+ 8'h5C : read_data <= {21'h0, ch5_epoch}; // 11 bits
+ 8'h5D : read_data <= {21'h0, ch5_epoch_check};
+ 8'h5E : begin
+ ch5_epoch_enable <= write & chip_select;
+ if (write & chip_select) ch5_epoch_load <= write_data[10:0];
+ end
+
+ // channel 6
+ 8'h60 : begin
+ ch6_prn_key_enable <= write & chip_select;
+ if (write & chip_select) ch6_prn_key <= write_data[9:0];
+ end
+ 8'h61 : if (write & chip_select) ch6_carr_nco <= write_data[28:0];
+ 8'h62 : if (write & chip_select) ch6_code_nco <= write_data[27:0];
+ 8'h63 : begin
+ ch6_slew_enable <= write & chip_select;
+ if (write & chip_select) ch6_code_slew <= write_data[10:0];
+ end
+ 8'h64 : read_data <= {16'h0, ch6_i_early};
+ 8'h65 : read_data <= {16'h0, ch6_q_early};
+ 8'h66 : read_data <= {16'h0, ch6_i_prompt};
+ 8'h67 : read_data <= {16'h0, ch6_q_prompt};
+ 8'h68 : read_data <= {16'h0, ch6_i_late};
+ 8'h69 : read_data <= {16'h0, ch6_q_late};
+ 8'h6A : read_data <= ch6_carrier_val; // 32 bits
+ 8'h6B : read_data <= {11'h0, ch6_code_val}; // 21 bits
+ 8'h6C : read_data <= {21'h0, ch6_epoch}; // 11 bits
+ 8'h6D : read_data <= {21'h0, ch6_epoch_check};
+ 8'h6E : begin
+ ch6_epoch_enable <= write & chip_select;
+ if (write & chip_select) ch6_epoch_load <= write_data[10:0];
+ end
+
+ // channel 7
+ 8'h70 : begin
+ ch7_prn_key_enable <= write & chip_select;
+ if (write & chip_select) ch7_prn_key <= write_data[9:0];
+ end
+ 8'h71 : if (write & chip_select) ch7_carr_nco <= write_data[28:0];
+ 8'h72 : if (write & chip_select) ch7_code_nco <= write_data[27:0];
+ 8'h73 : begin
+ ch7_slew_enable <= write & chip_select;
+ if (write & chip_select) ch7_code_slew <= write_data[10:0];
+ end
+ 8'h74 : read_data <= {16'h0, ch7_i_early};
+ 8'h75 : read_data <= {16'h0, ch7_q_early};
+ 8'h76 : read_data <= {16'h0, ch7_i_prompt};
+ 8'h77 : read_data <= {16'h0, ch7_q_prompt};
+ 8'h78 : read_data <= {16'h0, ch7_i_late};
+ 8'h79 : read_data <= {16'h0, ch7_q_late};
+ 8'h7A : read_data <= ch7_carrier_val; // 32 bits
+ 8'h7B : read_data <= {11'h0, ch7_code_val}; // 21 bits
+ 8'h7C : read_data <= {21'h0, ch7_epoch}; // 11 bits
+ 8'h7D : read_data <= {21'h0, ch7_epoch_check};
+ 8'h7E : begin
+ ch7_epoch_enable <= write & chip_select;
+ if (write & chip_select) ch7_epoch_load <= write_data[10:0];
+ end
+
+ // channel 8
+ 8'h80 : begin
+ ch8_prn_key_enable <= write & chip_select;
+ if (write & chip_select) ch8_prn_key <= write_data[9:0];
+ end
+ 8'h81 : if (write & chip_select) ch8_carr_nco <= write_data[28:0];
+ 8'h82 : if (write & chip_select) ch8_code_nco <= write_data[27:0];
+ 8'h83 : begin
+ ch8_slew_enable <= write & chip_select;
+ if (write & chip_select) ch8_code_slew <= write_data[10:0];
+ end
+ 8'h84 : read_data <= {16'h0, ch8_i_early};
+ 8'h85 : read_data <= {16'h0, ch8_q_early};
+ 8'h86 : read_data <= {16'h0, ch8_i_prompt};
+ 8'h87 : read_data <= {16'h0, ch8_q_prompt};
+ 8'h88 : read_data <= {16'h0, ch8_i_late};
+ 8'h89 : read_data <= {16'h0, ch8_q_late};
+ 8'h8A : read_data <= ch8_carrier_val; // 32 bits
+ 8'h8B : read_data <= {11'h0, ch8_code_val}; // 21 bits
+ 8'h8C : read_data <= {21'h0, ch8_epoch}; // 11 bits
+ 8'h8D : read_data <= {21'h0, ch8_epoch_check};
+ 8'h8E : begin
+ ch8_epoch_enable <= write & chip_select;
+ if (write & chip_select) ch8_epoch_load <= write_data[10:0];
+ end
+
+ // channel 9
+ 8'h90 : begin
+ ch9_prn_key_enable <= write & chip_select;
+ if (write & chip_select) ch1_prn_key <= write_data[9:0];
+ end
+ 8'h91 : if (write & chip_select) ch9_carr_nco <= write_data[28:0];
+ 8'h92 : if (write & chip_select) ch9_code_nco <= write_data[27:0];
+ 8'h93 : begin
+ ch9_slew_enable <= write & chip_select;
+ if (write & chip_select) ch9_code_slew <= write_data[10:0];
+ end
+ 8'h94 : read_data <= {16'h0, ch9_i_early};
+ 8'h95 : read_data <= {16'h0, ch9_q_early};
+ 8'h96 : read_data <= {16'h0, ch9_i_prompt};
+ 8'h97 : read_data <= {16'h0, ch9_q_prompt};
+ 8'h98 : read_data <= {16'h0, ch9_i_late};
+ 8'h99 : read_data <= {16'h0, ch9_q_late};
+ 8'h9A : read_data <= ch9_carrier_val; // 32 bits
+ 8'h9B : read_data <= {11'h0, ch9_code_val}; // 21 bits
+ 8'h9C : read_data <= {21'h0, ch9_epoch}; // 11 bits
+ 8'h9D : read_data <= {21'h0, ch9_epoch_check};
+ 8'h9E : begin
+ ch9_epoch_enable <= write & chip_select;
+ if (write & chip_select) ch9_epoch_load <= write_data[10:0];
+ end
+
+ // channel 10
+ 8'hA0 : begin
+ ch10_prn_key_enable <= write & chip_select;
+ if (write & chip_select) ch10_prn_key <= write_data[9:0];
+ end
+ 8'hA1 : if (write & chip_select) ch10_carr_nco <= write_data[28:0];
+ 8'hA2 : if (write & chip_select) ch10_code_nco <= write_data[27:0];
+ 8'hA3 : begin
+ ch10_slew_enable <= write & chip_select;
+ if (write & chip_select) ch1_code_slew <= write_data[10:0];
+ end
+ 8'hA4 : read_data <= {16'h0, ch10_i_early};
+ 8'hA5 : read_data <= {16'h0, ch10_q_early};
+ 8'hA6 : read_data <= {16'h0, ch10_i_prompt};
+ 8'hA7 : read_data <= {16'h0, ch10_q_prompt};
+ 8'hA8 : read_data <= {16'h0, ch10_i_late};
+ 8'hA9 : read_data <= {16'h0, ch10_q_late};
+ 8'hAA : read_data <= ch10_carrier_val; // 32 bits
+ 8'hAB : read_data <= {11'h0, ch10_code_val}; // 21 bits
+ 8'hAC : read_data <= {21'h0, ch10_epoch}; // 11 bits
+ 8'hAD : read_data <= {21'h0, ch10_epoch_check};
+ 8'hAE : begin
+ ch10_epoch_enable <= write & chip_select;
+ if (write & chip_select) ch10_epoch_load <= write_data[10:0];
+ end
+
+ // channel 11
+ 8'hB0 : begin
+ ch11_prn_key_enable <= write & chip_select;
+ if (write & chip_select) ch11_prn_key <= write_data[9:0];
+ end
+ 8'hB1 : if (write & chip_select) ch11_carr_nco <= write_data[28:0];
+ 8'hB2 : if (write & chip_select) ch11_code_nco <= write_data[27:0];
+ 8'hB3 : begin
+ ch11_slew_enable <= write & chip_select;
+ if (write & chip_select) ch11_code_slew <= write_data[10:0];
+ end
+ 8'hB4 : read_data <= {16'h0, ch11_i_early};
+ 8'hB5 : read_data <= {16'h0, ch11_q_early};
+ 8'hB6 : read_data <= {16'h0, ch11_i_prompt};
+ 8'hB7 : read_data <= {16'h0, ch11_q_prompt};
+ 8'hB8 : read_data <= {16'h0, ch11_i_late};
+ 8'hB9 : read_data <= {16'h0, ch11_q_late};
+ 8'hBA : read_data <= ch11_carrier_val; // 32 bits
+ 8'hBB : read_data <= {11'h0, ch11_code_val}; // 21 bits
+ 8'hBC : read_data <= {21'h0, ch11_epoch}; // 11 bits
+ 8'hBD : read_data <= {21'h0, ch11_epoch_check};
+ 8'hBE : begin
+ ch11_epoch_enable <= write & chip_select;
+ if (write & chip_select) ch11_epoch_load <= write_data[10:0];
+ end
+
+ // status
+ 8'hE0 : begin // get status and pulse status_flag to clear status
+ read_data <= {30'h0, status}; // only 2 status bits, therefore need to pad 30ms bits
+ status_read <= read & chip_select; // pulse status flag to clear status register
+ end
+ 8'hE1 : begin // get new_data
+ read_data <= {30'h0,new_data}; // one new_data bit per channel, need to pad other bits
+ // pulse the new data flag to clear new_data register
+ new_data_read <= read & chip_select;
+ // make sure the flag is not cleared if a dump is aligned to new_data_read
+ dump_mask[0] <= ch0_dump;
+ dump_mask[1] <= ch1_dump;
+ dump_mask[2] <= ch2_dump;
+ dump_mask[3] <= ch3_dump;
+ dump_mask[4] <= ch4_dump;
+ dump_mask[5] <= ch5_dump;
+ dump_mask[6] <= ch6_dump;
+ dump_mask[7] <= ch7_dump;
+ dump_mask[8] <= ch8_dump;
+ dump_mask[9] <= ch9_dump;
+ dump_mask[10] <= ch10_dump;
+ dump_mask[11] <= ch11_dump;
+ end
+ 8'hE2 : begin // tic count read
+ read_data <= {8'h0,tic_count}; // 24 bits of TIC count
+ end
+ 8'hE3 : begin // accum count read
+ read_data <= {8'h0,accum_count}; // 24 bits of accum count
+ end
+
+ // control
+ 8'hF0 : sw_rst <= write & chip_select; // software reset
+ 8'hF1 : if (write & chip_select) prog_tic <= write_data[23:0]; // program TIC
+ 8'hF2 : if (write & chip_select) prog_accum_int <= write_data[23:0]; // program ACCUM_INT
+
+ default : read_data <= 0;
+
+ endcase // case(address)
+ end
+
+ // process to create a two clk wide dump_mask pulse
+ always @ (posedge clk)
+ begin
+ if (!rstn)
+ dump_mask_2 <= 0;
+ else
+ dump_mask_2 <= dump_mask;
+ end
+
+ // process to reset the status register after a read
+ // also create accum_int signal that is cleared after status read
+
+ always @ (posedge clk)
+ begin
+ if (!rstn || status_read)
+ begin
+ status <= 0;
+ accum_int <= 0;
+ end
+ else
+ begin
+ if (tic_enable)
+ status[0] <= 1;
+ if (accum_enable_s)
+ begin
+ status[1] <= 1;
+ accum_int <= 1;
+ end
+ end
+ end
+
+ // process to reset the new_data register after a read
+ // set new data bits when channel dumps occur
+ always @ (posedge clk)
+ begin
+ if (!rstn || new_data_read)
+ begin
+ new_data <= dump_mask | dump_mask_2;
+ end
+ else
+ begin
+ if (ch0_dump)
+ new_data[0] <= 1;
+ if (ch1_dump)
+ new_data[1] <= 1;
+ if (ch2_dump)
+ new_data[2] <= 1;
+ if (ch3_dump)
+ new_data[3] <= 1;
+ if (ch4_dump)
+ new_data[4] <= 1;
+ if (ch5_dump)
+ new_data[5] <= 1;
+ if (ch6_dump)
+ new_data[6] <= 1;
+ if (ch7_dump)
+ new_data[7] <= 1;
+ if (ch8_dump)
+ new_data[8] <= 1;
+ if (ch9_dump)
+ new_data[9] <= 1;
+ if (ch10_dump)
+ new_data[10] <= 1;
+ if (ch11_dump)
+ new_data[11] <= 1;
+ end // else: !if(!rstn || new_data_read)
+ end // always @ (posedge clk)
+
+endmodule // gps_baseband
+
+
+
504 cores/namuru/rtl/lgpl.txt
View
@@ -0,0 +1,504 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 2.1, February 1999
+
+ Copyright (C) 1991, 1999 Free Software Foundation, Inc.
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+[This is the first released version of the Lesser GPL. It also counts
+ as the successor of the GNU Library Public License, version 2, hence
+ the version number 2.1.]
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+Licenses are intended to guarantee your freedom to share and change
+free software--to make sure the software is free for all its users.
+
+ This license, the Lesser General Public License, applies to some
+specially designated software packages--typically libraries--of the
+Free Software Foundation and other authors who decide to use it. You
+can use it too, but we suggest you first think carefully about whether
+this license or the ordinary General Public License is the better
+strategy to use in any particular case, based on the explanations below.
+
+ When we speak of free software, we are referring to freedom of use,
+not price. Our General Public Licenses are designed to make sure that
+you have the freedom to distribute copies of free software (and charge
+for this service if you wish); that you receive source code or can get
+it if you want it; that you can change the software and use pieces of
+it in new free programs; and that you are informed that you can do
+these things.
+
+ To protect your rights, we need to make restrictions that forbid
+distributors to deny you these rights or to ask you to surrender these
+rights. These restrictions translate to certain responsibilities for
+you if you distribute copies of the library or if you modify it.
+
+ For example, if you distribute copies of the library, whether gratis
+or for a fee, you must give the recipients all the rights that we gave
+you. You must make sure that they, too, receive or can get the source
+code. If you link other code with the library, you must provide
+complete object files to the recipients, so that they can relink them
+with the library after making changes to the library and recompiling
+it. And you must show them these terms so they know their rights.
+
+ We protect your rights with a two-step method: (1) we copyright the
+library, and (2) we offer you this license, which gives you legal
+permission to copy, distribute and/or modify the library.
+
+ To protect each distributor, we want to make it very clear that
+there is no warranty for the free library. Also, if the library is
+modified by someone else and passed on, the recipients should know
+that what they have is not the original version, so that the original
+author's reputation will not be affected by problems that might be
+introduced by others.
+
+ Finally, software patents pose a constant threat to the existence of
+any free program. We wish to make sure that a company cannot
+effectively restrict the users of a free program by obtaining a
+restrictive license from a patent holder. Therefore, we insist that
+any patent license obtained for a version of the library must be
+consistent with the full freedom of use specified in this license.
+
+ Most GNU software, including some libraries, is covered by the
+ordinary GNU General Public License. This license, the GNU Lesser
+General Public License, applies to certain designated libraries, and
+is quite different from the ordinary General Public License. We use
+this license for certain libraries in order to permit linking those
+libraries into non-free programs.
+
+ When a program is linked with a library, whether statically or using
+a shared library, the combination of the two is legally speaking a
+combined work, a derivative of the original library. The ordinary
+General Public License therefore permits such linking only if the
+entire combination fits its criteria of freedom. The Lesser General
+Public License permits more lax criteria for linking other code with
+the library.
+
+ We call this license the "Lesser" General Public License because it
+does Less to protect the user's freedom than the ordinary General
+Public License. It also provides other free software developers Less
+of an advantage over competing non-free programs. These disadvantages
+are the reason we use the ordinary General Public License for many
+libraries. However, the Lesser license provides advantages in certain
+special circumstances.
+
+ For example, on rare occasions, there may be a special need to
+encourage the widest possible use of a certain library, so that it becomes
+a de-facto standard. To achieve this, non-free programs must be
+allowed to use the library. A more frequent case is that a free
+library does the same job as widely used non-free libraries. In this
+case, there is little to gain by limiting the free library to free
+software only, so we use the Lesser General Public License.
+
+ In other cases, permission to use a particular library in non-free
+programs enables a greater number of people to use a large body of
+free software. For example, permission to use the GNU C Library in
+non-free programs enables many more people to use the whole GNU
+operating system, as well as its variant, the GNU/Linux operating
+system.
+
+ Although the Lesser General Public License is Less protective of the
+users' freedom, it does ensure that the user of a program that is
+linked with the Library has the freedom and the wherewithal to run
+that program using a modified version of the Library.
+
+ The precise terms and conditions for copying, distribution and
+modification follow. Pay close attention to the difference between a
+"work based on the library" and a "work that uses the library". The
+former contains code derived from the library, whereas the latter must
+be combined with the library in order to run.
+
+ GNU LESSER GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License Agreement applies to any software library or other
+program which contains a notice placed by the copyright holder or
+other authorized party saying it may be distributed under the terms of
+this Lesser General Public License (also called "this License").
+Each licensee is addressed as "you".
+
+ A "library" means a collection of software functions and/or data
+prepared so as to be conveniently linked with application programs
+(which use some of those functions and data) to form executables.
+
+ The "Library", below, refers to any such software library or work
+which has been distributed under these terms. A "work based on the
+Library" means either the Library or any derivative work under
+copyright law: that is to say, a work containing the Library or a
+portion of it, either verbatim or with modifications and/or translated
+straightforwardly into another language. (Hereinafter, translation is
+included without limitation in the term "modification".)
+
+ "Source code" for a work means the preferred form of the work for
+making modifications to it. For a library, complete source code means
+all the source code for all modules it contains, plus any associated
+interface definition files, plus the scripts used to control compilation
+and installation of the library.
+
+ Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running a program using the Library is not restricted, and output from
+such a program is covered only if its contents constitute a work based
+on the Library (independent of the use of the Library in a tool for
+writing it). Whether that is true depends on what the Library does
+and what the program that uses the Library does.
+
+ 1. You may copy and distribute verbatim copies of the Library's
+complete source code as you receive it, in any medium, provided that
+you conspicuously and appropriately publish on each copy an
+appropriate copyright notice and disclaimer of warranty; keep intact
+all the notices that refer to this License and to the absence of any
+warranty; and distribute a copy of this License along with the
+Library.
+
+ You may charge a fee for the physical act of transferring a copy,
+and you may at your option offer warranty protection in exchange for a
+fee.
+
+ 2. You may modify your copy or copies of the Library or any portion
+of it, thus forming a work based on the Library, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) The modified work must itself be a software library.
+
+ b) You must cause the files modified to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ c) You must cause the whole of the work to be licensed at no
+ charge to all third parties under the terms of this License.
+
+ d) If a facility in the modified Library refers to a function or a
+ table of data to be supplied by an application program that uses
+ the facility, other than as an argument passed when the facility
+ is invoked, then you must make a good faith effort to ensure that,
+ in the event an application does not supply such function or
+ table, the facility still operates, and performs whatever part of
+ its purpose remains meaningful.
+
+ (For example, a function in a library to compute square roots has
+ a purpose that is entirely well-defined independent of the
+ application. Therefore, Subsection 2d requires that any
+ application-supplied function or table used by this function must
+ be optional: if the application does not supply it, the square
+ root function must still compute square roots.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Library,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Library, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote
+it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Library.
+
+In addition, mere aggregation of another work not based on the Library
+with the Library (or with a work based on the Library) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may opt to apply the terms of the ordinary GNU General Public
+License instead of this License to a given copy of the Library. To do
+this, you must alter all the notices that refer to this License, so
+that they refer to the ordinary GNU General Public License, version 2,
+instead of to this License. (If a newer version than version 2 of the
+ordinary GNU General Public License has appeared, then you can specify
+that version instead if you wish.) Do not make any other change in
+these notices.
+
+ Once this change is made in a given copy, it is irreversible for
+that copy, so the ordinary GNU General Public License applies to all
+subsequent copies and derivative works made from that copy.
+
+ This option is useful when you wish to copy part of the code of
+the Library into a program that is not a library.
+
+ 4. You may copy and distribute the Library (or a portion or
+derivative of it, under Section 2) in object code or executable form
+under the terms of Sections 1 and 2 above provided that you accompany
+it with the complete corresponding machine-readable source code, which
+must be distributed under the terms of Sections 1 and 2 above on a
+medium customarily used for software interchange.
+
+ If distribution of object code is made by offering access to copy
+from a designated place, then offering equivalent access to copy the
+source code from the same place satisfies the requirement to
+distribute the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 5. A program that contains no derivative of any portion of the
+Library, but is designed to work with the Library by being compiled or
+linked with it, is called a "work that uses the Library". Such a
+work, in isolation, is not a derivative work of the Library, and
+therefore falls outside the scope of this License.
+
+ However, linking a "work that uses the Library" with the Library
+creates an executable that is a derivative of the Library (because it
+contains portions of the Library), rather than a "work that uses the
+library". The executable is therefore covered by this License.
+Section 6 states terms for distribution of such executables.
+
+ When a "work that uses the Library" uses material from a header file
+that is part of the Library, the object code for the work may be a
+derivative work of the Library even though the source code is not.
+Whether this is true is especially significant if the work can be
+linked without the Library, or if the work is itself a library. The
+threshold for this to be true is not precisely defined by law.
+
+ If such an object file uses only numerical parameters, data
+structure layouts and accessors, and small macros and small inline
+functions (ten lines or less in length), then the use of the object
+file is unrestricted, regardless of whether it is legally a derivative
+work. (Executables containing this object code plus portions of the
+Library will still fall under Section 6.)
+
+ Otherwise, if the work is a derivative of the Library, you may
+distribute the object code for the work under the terms of Section 6.
+Any executables containing that work also fall under Section 6,
+whether or not they are linked directly with the Library itself.
+
+ 6. As an exception to the Sections above, you may also combine or
+link a "work that uses the Library" with the Library to produce a
+work containing portions of the Library, and distribute that work
+under terms of your choice, provided that the terms permit
+modification of the work for the customer's own use and reverse
+engineering for debugging such modifications.
+
+ You must give prominent notice with each copy of the work that the
+Library is used in it and that the Library and its use are covered by
+this License. You must supply a copy of this License. If the work
+during execution displays copyright notices, you must include the
+copyright notice for the Library among them, as well as a reference
+directing the user to the copy of this License. Also, you must do one
+of these things:
+
+ a) Accompany the work with the complete corresponding
+ machine-readable source code for the Library including whatever
+ changes were used in the work (which must be distributed under
+ Sections 1 and 2 above); and, if the work is an executable linked
+ with the Library, with the complete machine-readable "work that
+ uses the Library", as object code and/or source code, so that the
+ user can modify the Library and then relink to produce a modified
+ executable containing the modified Library. (It is understood
+ that the user who changes the contents of definitions files in the
+ Library will not necessarily be able to recompile the application
+ to use the modified definitions.)
+
+ b) Use a suitable shared library mechanism for linking with the
+ Library. A suitable mechanism is one that (1) uses at run time a
+ copy of the library already present on the user's computer system,
+ rather than copying library functions into the executable, and (2)
+ will operate properly with a modified version of the library, if
+ the user installs one, as long as the modified version is
+ interface-compatible with the version that the work was made with.
+
+ c) Accompany the work with a written offer, valid for at
+ least three years, to give the same user the materials
+ specified in Subsection 6a, above, for a charge no more
+ than the cost of performing this distribution.
+
+ d) If distribution of the work is made by offering access to copy
+ from a designated place, offer equivalent access to copy the above
+ specified materials from the same place.
+
+ e) Verify that the user has already received a copy of these
+ materials or that you have already sent this user a copy.
+
+ For an executable, the required form of the "work that uses the
+Library" must include any data and utility programs needed for
+reproducing the executable from it. However, as a special exception,
+the materials to be distributed need not include anything that is
+normally distributed (in either source or binary form) with the major
+components (compiler, kernel, and so on) of the operating system on
+which the executable runs, unless that component itself accompanies
+the executable.
+
+ It may happen that this requirement contradicts the license
+restrictions of other proprietary libraries that do not normally
+accompany the operating system. Such a contradiction means you cannot
+use both them and the Library together in an executable that you
+distribute.
+
+ 7. You may place library facilities that are a work based on the
+Library side-by-side in a single library together with other library
+facilities not covered by this License, and distribute such a combined
+library, provided that the separate distribution of the work based on
+the Library and of the other library facilities is otherwise
+permitted, and provided that you do these two things:
+
+ a) Accompany the combined library with a copy of the same work
+ based on the Library, uncombined with any other library
+ facilities. This must be distributed under the terms of the
+ Sections above.
+
+ b) Give prominent notice with the combined library of the fact
+ that part of it is a work based on the Library, and explaining
+ where to find the accompanying uncombined form of the same work.
+
+ 8. You may not copy, modify, sublicense, link with, or distribute
+the Library except as expressly provided under this License. Any
+attempt otherwise to copy, modify, sublicense, link with, or
+distribute the Library is void, and will automatically terminate your
+rights under this License. However, parties who have received copies,
+or rights, from you under this License will not have their licenses
+terminated so long as such parties remain in full compliance.
+
+ 9. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Library or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Library (or any work based on the
+Library), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Library or works based on it.
+
+ 10. Each time you redistribute the Library (or any work based on the
+Library), the recipient automatically receives a license from the
+original licensor to copy, distribute, link with or modify the Library
+subject to these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties with
+this License.
+
+ 11. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Library at all. For example, if a patent
+license would not permit royalty-free redistribution of the Library by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Library.
+
+If any portion of this section is held invalid or unenforceable under any
+particular circumstance, the balance of the section is intended to apply,
+and the section as a whole is intended to apply in other circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 12. If the distribution and/or use of the Library is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Library under this License may add
+an explicit geographical distribution limitation excluding those countries,
+so that distribution is permitted only in or among countries not thus
+excluded. In such case, this License incorporates the limitation as if
+written in the body of this License.
+
+ 13. The Free Software Foundation may publish revised and/or new
+versions of the Lesser General Public License from time to time.
+Such new versions will be similar in spirit to the present version,
+but may differ in detail to address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Library
+specifies a version number of this License which applies to it and
+"any later version", you have the option of following the terms and
+conditions either of that version or of any later version published by
+the Free Software Foundation. If the Library does not specify a
+license version number, you may choose any version ever published by
+the Free Software Foundation.
+
+ 14. If you wish to incorporate parts of the Library into other free
+programs whose distribution conditions are incompatible with these,
+write to the author to ask for permission. For software which is
+copyrighted by the Free Software Foundation, write to the Free
+Software Foundation; we sometimes make exceptions for this. Our
+decision will be guided by the two goals of preserving the free status
+of all derivatives of our free software and of promoting the sharing
+and reuse of software generally.
+
+ NO WARRANTY
+
+ 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO
+WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW.
+EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
+OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY
+KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
+LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME
+THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+ 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN
+WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY
+AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU
+FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR
+CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE
+LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING
+RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A
+FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF
+SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Libraries
+
+ If you develop a new library, and you want it to be of the greatest
+possible use to the public, we recommend making it free software that
+everyone can redistribute and change. You can do so by permitting
+redistribution under these terms (or, alternatively, under the terms of the
+ordinary General Public License).
+
+ To apply these terms, attach the following notices to the library. It is
+safest to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least the
+"copyright" line and a pointer to where the full notice is found.
+
+ <one line to give the library's name and a brief idea of what it does.>
+ Copyright (C) <year> <name of author>
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+Also add information on how to contact you by electronic and paper mail.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the library, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the
+ library `Frob' (a library for tweaking knobs) written by James Random Hacker.
+
+ <signature of Ty Coon>, 1 April 1990
+ Ty Coon, President of Vice
+
+That's all there is to it!
+
+
480 cores/namuru/rtl/simplified_gps_baseband.v
View
@@ -0,0 +1,480 @@
+/*
+Engineer: Artyom Gavrilov, gnss-sdr.com, 2012
+*/
+
+module simplified_gps_baseband (clk, hw_rstn,
+ //input from front-end:
+ sign, mag,
+ //wishbone bus:
+ wb_adr_i, wb_dat_o, wb_dat_i,
+ wb_sel_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_we_i,
+ //interrupt for mcu:
+ accum_int,
+ test_point_01, test_point_02, test_point_03,
+ test_point_04, test_point_05
+ );
+
+ input clk, hw_rstn;
+ input sign, mag; // raw data in from RF front end
+ input [31:0] wb_adr_i, wb_dat_i;//, wb_dat_o;
+ input [3:0] wb_sel_i;
+ input wb_stb_i, wb_cyc_i, wb_we_i;
+
+ output reg accum_int; // interrupt pulse to tell FW to collect accumulation data, cleared on STATUS read
+ output reg [31:0] wb_dat_o;
+ output reg wb_ack_o;
+ output test_point_01, test_point_02, test_point_03;
+ output test_point_04, test_point_05;
+
+ wire accum_enable_s;
+ wire pre_tic_enable, tic_enable, accum_sample_enable;
+
+ wire [23:0] tic_count;
+ wire [23:0] accum_count;
+
+ reg sw_rst; // reset to tracking module
+ wire rstn; // software generated reset
+
+ // channel 0 registers
+ reg [9:0] ch0_prn_key;
+ reg [28:0] ch0_carr_nco;
+ reg [27:0] ch0_code_nco;
+ reg [10:0] ch0_code_slew;
+ reg [10:0] ch0_epoch_load;
+ reg ch0_prn_key_enable, ch0_slew_enable, ch0_epoch_enable;
+ wire ch0_dump;
+ //wire [31:0] ch0_i_early, ch0_q_early, ch0_i_prompt, ch0_q_prompt, ch0_i_late, ch0_q_late;
+ wire [15:0] ch0_i_early, ch0_q_early, ch0_i_prompt, ch0_q_prompt, ch0_i_late, ch0_q_late;
+ wire [31:0] ch0_carrier_val;
+ wire [20:0] ch0_code_val;
+ wire [10:0] ch0_epoch, ch0_epoch_check;
+
+ // channel 1 registers
+ reg [9:0] ch1_prn_key;
+ reg [28:0] ch1_carr_nco;
+ reg [27:0] ch1_code_nco;
+ reg [10:0] ch1_code_slew;
+ reg [10:0] ch1_epoch_load;
+ reg ch1_prn_key_enable, ch1_slew_enable, ch1_epoch_enable;
+ wire ch1_dump;
+ //wire [31:0] ch1_i_early, ch1_q_early, ch1_i_prompt, ch1_q_prompt, ch1_i_late, ch1_q_late;
+ wire [15:0] ch1_i_early, ch1_q_early, ch1_i_prompt, ch1_q_prompt, ch1_i_late, ch1_q_late;
+ wire [31:0] ch1_carrier_val;
+ wire [20:0] ch1_code_val;
+ wire [10:0] ch1_epoch, ch1_epoch_check;
+
+ // channel 2 registers
+ reg [9:0] ch2_prn_key;
+ reg [28:0] ch2_carr_nco;
+ reg [27:0] ch2_code_nco;
+ reg [10:0] ch2_code_slew;
+ reg [10:0] ch2_epoch_load;
+ reg ch2_prn_key_enable, ch2_slew_enable, ch2_epoch_enable;
+ wire ch2_dump;
+ //wire [31:0] ch2_i_early, ch2_q_early, ch2_i_prompt, ch2_q_prompt, ch2_i_late, ch2_q_late;
+ wire [15:0] ch2_i_early, ch2_q_early, ch2_i_prompt, ch2_q_prompt, ch2_i_late, ch2_q_late;
+ wire [31:0] ch2_carrier_val;
+ wire [20:0] ch2_code_val;
+ wire [10:0] ch2_epoch, ch2_epoch_check;
+
+ // channel 3 registers
+ reg [9:0] ch3_prn_key;
+ reg [28:0] ch3_carr_nco;
+ reg [27:0] ch3_code_nco;
+ reg [10:0] ch3_code_slew;
+ reg [10:0] ch3_epoch_load;
+ reg ch3_prn_key_enable, ch3_slew_enable, ch3_epoch_enable;
+ wire ch3_dump;
+ //wire [31:0] ch3_i_early, ch3_q_early, ch3_i_prompt, ch3_q_prompt, ch3_i_late, ch3_q_late;
+ wire [15:0] ch3_i_early, ch3_q_early, ch3_i_prompt, ch3_q_prompt, ch3_i_late, ch3_q_late;
+ wire [31:0] ch3_carrier_val;
+ wire [20:0] ch3_code_val;
+ wire [10:0] ch3_epoch, ch3_epoch_check;
+
+ //test_points
+ wire ch0_test_point_01, ch0_test_point_02, ch0_test_point_03;
+
+ // status registers
+ reg [1:0] status; // TIC = bit 0, ACCUM_INT = bit 1, cleared on read
+ reg status_read; // pulse when status register is read
+ reg [3:0] new_data; // chan0 = bit 0, chan1 = bit 1 etc, cleared on read
+ reg new_data_read; // pules when new_data register is read
+ reg [3:0] dump_mask; // mask a channel that has a dump aligned with the new data read
+ reg [3:0] dump_mask_2; // mask for two clock cycles
+
+ // control registers
+ reg [23:0] prog_tic;
+ reg [23:0] prog_accum_int;
+
+ //memory for testing wishbone-interface:
+ reg [31:0] test_memory [0:7]; //eight 32-bit-wide words;
+
+ // connect up time base
+ time_base tb (.clk(clk), .rstn(rstn),
+ .tic_divide(prog_tic),
+ .accum_divide(prog_accum_int),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .accum_enable(accum_enable_s),
+ .accum_sample_enable(accum_sample_enable),
+ .tic_count(tic_count),
+ .accum_count(accum_count)
+ );
+
+ assign rstn = hw_rstn & ~sw_rst;
+
+ // connect up tracking channels
+ tracking_channel tc0 (.clk(clk), .rstn(rstn),
+ .accum_sample_enable(accum_sample_enable),
+ .if_sign(sign), .if_mag(mag),
+ .pre_tic_enable(pre_tic_enable),
+ .tic_enable(tic_enable),
+ .carr_nco_fc(ch0_carr_nco),
+ .code_nco_fc(ch0_code_nco),
+ .prn_key(ch0_prn_key),
+ .prn_key_enable(ch0_prn_key_enable),
+ .code_slew(ch0_code_slew),
+ .slew_enable(ch0_slew_enable),
+ .epoch_enable(ch0_epoch_enable),