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  1. 14  .gitignore
  2. 2  boards/milkymist-one/flash/Makefile
  3. 132  boards/milkymist-one/rtl/system.v
  4. 3  boards/milkymist-one/sources.mak
  5. 16  boards/milkymist-one/synthesis/common.ucf
  6. 2  cores/ac97/rtl/ac97.v
  7. 4  cores/ac97/rtl/ac97_ctlif.v
  8. 2  cores/bt656cap/rtl/bt656cap.v
  9. 4  cores/bt656cap/rtl/bt656cap_ctlif.v
  10. 32  cores/conbus/rtl/{conbus5x6.v → conbus5x7.v}
  11. 4  cores/csrbrg/rtl/csrbrg.v
  12. 4  cores/dmx/rtl/dmx_rx.v
  13. 4  cores/dmx/rtl/dmx_tx.v
  14. 4  cores/fmlmeter/rtl/fmlmeter.v
  15. 104  cores/hello_conbus/rtl/hello_conbus.v
  16. 2  cores/hpdmc_ddr32/rtl/hpdmc.v
  17. 4  cores/hpdmc_ddr32/rtl/hpdmc_ctlif.v
  18. 4  cores/memcard/rtl/memcard.v
  19. 4  cores/memtest/rtl/memtest.v
  20. 2  cores/minimac2/rtl/minimac2.v
  21. 4  cores/minimac2/rtl/minimac2_ctlif.v
  22. 2  cores/pfpu/rtl/pfpu.v
  23. 4  cores/pfpu/rtl/pfpu_ctlif.v
  24. 4  cores/rc5/rtl/rc5.v
  25. 2  cores/softusb/rtl/softusb.v
  26. 4  cores/softusb/rtl/softusb_hostif.v
  27. 4  cores/sysctl/rtl/sysctl.v
  28. 2  cores/tmu2/rtl/tmu2.v
  29. 4  cores/tmu2/rtl/tmu2_ctlif.v
  30. 4  cores/uart/rtl/uart.v
  31. 2  cores/vgafb/rtl/vgafb.v
  32. 4  cores/vgafb/rtl/vgafb_ctlif.v
  33. 2  software/bios/crt0.S
14  .gitignore
@@ -4,6 +4,19 @@
4 4
 *.swp
5 5
 *.elf
6 6
 *.bin
  7
+<<<<<<< HEAD
  8
+boards/milkymist-one/synthesis/build
  9
+boards/milkymist-one/synthesis/build-rescue
  10
+boards/milkymist-one/standby/build
  11
+boards/milkymist-one/flash/soc-rescue.fpg
  12
+boards/milkymist-one/flash/soc.fpg
  13
+boards/milkymist-one/flash/splash-rescue.raw
  14
+boards/milkymist-one/flash/splash.raw
  15
+boards/milkymist-one/flash/standby.fpg
  16
+software/demo/boot.fbi
  17
+software/demo/logo.h
  18
+software/demo/logo.raw
  19
+=======
7 20
 *.fpg
8 21
 *.raw
9 22
 *.fbi
@@ -11,6 +24,7 @@ boards/milkymist-one/synthesis/build
11 24
 boards/milkymist-one/synthesis/build-rescue
12 25
 boards/milkymist-one/standby/build
13 26
 software/demo/logo.h
  27
+>>>>>>> e39899e271a1d1b9e6199eb25faecb65262be8ce
14 28
 software/libfpvm/parser.c
15 29
 software/libfpvm/parser.h
16 30
 software/libfpvm/parser.out
2  boards/milkymist-one/flash/Makefile
@@ -49,7 +49,7 @@ splash.raw: splash.png
49 49
 	$(MMDIR)/tools/makeraw splash.png
50 50
 
51 51
 flash: all
52  
-	jtag -n flashall.batch
  52
+	sudo jtag -n flashall.batch
53 53
 
54 54
 connect:
55 55
 	stty -F $(SERIAL) raw 115200
132  boards/milkymist-one/rtl/system.v
@@ -18,6 +18,7 @@
18 18
 `include "setup.v"
19 19
 `include "lm32_include.v"
20 20
 
  21
+
21 22
 module system(
22 23
 	input clk50,
23 24
 
@@ -135,7 +136,14 @@ module system(
135 136
 	input ir_rx,
136 137
 
137 138
 	// Expansion connector
138  
-	input [11:0] exp,
  139
+	input [9:0] exp,
  140
+
  141
+	// UART1 
  142
+	input uart1_rx,
  143
+	output uart1_tx,
  144
+
  145
+	// Debug Led
  146
+	output debug_led,
139 147
 
140 148
 	// PCB revision
141 149
 	input [3:0] pcb_revision
@@ -297,7 +305,8 @@ wire [31:0]	norflash_adr,
297 305
 		usb_adr,
298 306
 		eth_adr,
299 307
 		brg_adr,
300  
-		csrbrg_adr;
  308
+		csrbrg_adr,
  309
+		hello_adr;
301 310
 
302 311
 wire [2:0]	brg_cti;
303 312
 
@@ -312,7 +321,9 @@ wire [31:0]	norflash_dat_r,
312 321
 		brg_dat_r,
313 322
 		brg_dat_w,
314 323
 		csrbrg_dat_r,
315  
-		csrbrg_dat_w;
  324
+		csrbrg_dat_w,
  325
+		hello_dat_r,
  326
+		hello_dat_w;
316 327
 
317 328
 wire [3:0]	norflash_sel,
318 329
 		monitor_sel,
@@ -325,28 +336,32 @@ wire		norflash_we,
325 336
 		usb_we,
326 337
 		eth_we,
327 338
 		brg_we,
328  
-		csrbrg_we;
  339
+		csrbrg_we,
  340
+		hello_we;
329 341
 
330 342
 wire		norflash_cyc,
331 343
 		monitor_cyc,
332 344
 		usb_cyc,
333 345
 		eth_cyc,
334 346
 		brg_cyc,
335  
-		csrbrg_cyc;
  347
+		csrbrg_cyc,
  348
+		hello_cyc;
336 349
 
337 350
 wire		norflash_stb,
338 351
 		monitor_stb,
339 352
 		usb_stb,
340 353
 		eth_stb,
341 354
 		brg_stb,
342  
-		csrbrg_stb;
  355
+		csrbrg_stb,
  356
+		hello_stb;
343 357
 
344 358
 wire		norflash_ack,
345 359
 		monitor_ack,
346 360
 		usb_ack,
347 361
 		eth_ack,
348 362
 		brg_ack,
349  
-		csrbrg_ack;
  363
+		csrbrg_ack,
  364
+		hello_ack;
350 365
 
351 366
 //---------------------------------------------------------------------------
352 367
 // Wishbone switch
@@ -357,15 +372,17 @@ wire		norflash_ack,
357 372
 // Ethernet     0x30000000 (shadow @0xb0000000)
358 373
 // SDRAM        0x40000000 (shadow @0xc0000000)
359 374
 // CSR bridge   0x60000000 (shadow @0xe0000000)
  375
+// Hello Core   0x70000000 (shadow @0xf0000000)
360 376
 
361 377
 // MSB (Bit 31) is ignored for slave address decoding
362  
-conbus5x6 #(
  378
+conbus5x7 #(
363 379
 	.s0_addr(3'b000), // norflash
364 380
 	.s1_addr(3'b001), // debug
365 381
 	.s2_addr(3'b010), // USB
366 382
 	.s3_addr(3'b011), // Ethernet
367 383
 	.s4_addr(2'b10),  // SDRAM
368  
-	.s5_addr(2'b11)   // CSR
  384
+	.s5_addr(2'b11),  // CSR
  385
+	.s6_addr(3'b111)  // Hello Core
369 386
 ) wbswitch (
370 387
 	.sys_clk(sys_clk),
371 388
 	.sys_rst(sys_rst),
@@ -489,13 +506,23 @@ conbus5x6 #(
489 506
 	.s5_we_o(csrbrg_we),
490 507
 	.s5_cyc_o(csrbrg_cyc),
491 508
 	.s5_stb_o(csrbrg_stb),
492  
-	.s5_ack_i(csrbrg_ack)
  509
+	.s5_ack_i(csrbrg_ack),
  510
+	// Slave 6
  511
+	.s6_dat_i(hello_dat_r),
  512
+	.s6_dat_o(hello_dat_w),
  513
+	.s6_adr_o(hello_adr),
  514
+	.s6_cti_o(),
  515
+	.s6_sel_o(),
  516
+	.s6_we_o(hello_we),
  517
+	.s6_cyc_o(hello_cyc),
  518
+	.s6_stb_o(hello_stb),
  519
+	.s6_ack_i(hello_ack)
493 520
 );
494 521
 
495 522
 //------------------------------------------------------------------
496 523
 // CSR bus
497 524
 //------------------------------------------------------------------
498  
-wire [13:0]	csr_a;
  525
+wire [14:0]	csr_a;
499 526
 wire		csr_we;
500 527
 wire [31:0]	csr_dw;
501 528
 wire [31:0]	csr_dr_uart,
@@ -513,7 +540,8 @@ wire [31:0]	csr_dr_uart,
513 540
 		csr_dr_dmx_tx,
514 541
 		csr_dr_dmx_rx,
515 542
 		csr_dr_ir,
516  
-		csr_dr_usb;
  543
+		csr_dr_usb,
  544
+		csr_dr_uart1;
517 545
 
518 546
 //------------------------------------------------------------------
519 547
 // FML master wires
@@ -676,6 +704,7 @@ csrbrg csrbrg(
676 704
 		|csr_dr_dmx_rx
677 705
 		|csr_dr_ir
678 706
 		|csr_dr_usb
  707
+		|csr_dr_uart1
679 708
 	)
680 709
 );
681 710
 
@@ -738,9 +767,13 @@ wire midirx_irq;
738 767
 wire miditx_irq;
739 768
 wire ir_irq;
740 769
 wire usb_irq;
  770
+wire uart1rx_irq;
  771
+wire uart1tx_irq;
741 772
 
742 773
 wire [31:0] cpu_interrupt;
743 774
 assign cpu_interrupt = {14'd0,
  775
+	uart1tx_irq,
  776
+	uart1rx_irq,
744 777
 	usb_irq,
745 778
 	ir_irq,
746 779
 	miditx_irq,
@@ -863,7 +896,7 @@ assign monitor_ack = 1'b0;
863 896
 // UART
864 897
 //---------------------------------------------------------------------------
865 898
 uart #(
866  
-	.csr_addr(4'h0),
  899
+	.csr_addr(5'h0),
867 900
 	.clk_freq(`CLOCK_FREQUENCY),
868 901
 	.baud(`BAUD_RATE),
869 902
 	.break_en_default(1'b1)
@@ -896,7 +929,7 @@ wire [13:0] gpio_outputs;
896 929
 wire [31:0] capabilities;
897 930
 
898 931
 sysctl #(
899  
-	.csr_addr(4'h1),
  932
+	.csr_addr(5'h1),
900 933
 	.ninputs(7),
901 934
 	.noutputs(2),
902 935
 	.systemid(32'h10044D31) /* 1.0.0 RC4 on M1 */
@@ -928,7 +961,7 @@ gen_capabilities gen_capabilities(
928 961
 // DDR SDRAM
929 962
 //---------------------------------------------------------------------------
930 963
 ddram #(
931  
-	.csr_addr(4'h2)
  964
+	.csr_addr(5'h2)
932 965
 ) ddram (
933 966
 	.sys_clk(sys_clk),
934 967
 	.sys_clk_n(sys_clk_n),
@@ -965,7 +998,7 @@ ddram #(
965 998
 // VGA
966 999
 //---------------------------------------------------------------------------
967 1000
 vga #(
968  
-	.csr_addr(4'h3),
  1001
+	.csr_addr(5'h3),
969 1002
 	.fml_depth(`SDRAM_DEPTH)
970 1003
 ) vga (
971 1004
 	.sys_clk(sys_clk),
@@ -1004,7 +1037,7 @@ vga #(
1004 1037
 //---------------------------------------------------------------------------
1005 1038
 `ifdef ENABLE_MEMORYCARD
1006 1039
 memcard #(
1007  
-	.csr_addr(4'h4)
  1040
+	.csr_addr(5'h4)
1008 1041
 ) memcard (
1009 1042
 	.sys_clk(sys_clk),
1010 1043
 	.sys_rst(sys_rst),
@@ -1040,7 +1073,7 @@ BUFG b_ac97(
1040 1073
 );
1041 1074
 `ifdef ENABLE_AC97
1042 1075
 ac97 #(
1043  
-	.csr_addr(4'h5)
  1076
+	.csr_addr(5'h5)
1044 1077
 ) ac97 (
1045 1078
 	.sys_clk(sys_clk),
1046 1079
 	.sys_rst(sys_rst),
@@ -1095,7 +1128,7 @@ assign ac97bus_dat_w = 32'bx;
1095 1128
 //---------------------------------------------------------------------------
1096 1129
 `ifdef ENABLE_PFPU
1097 1130
 pfpu #(
1098  
-	.csr_addr(4'h6)
  1131
+	.csr_addr(5'h6)
1099 1132
 ) pfpu (
1100 1133
 	.sys_clk(sys_clk),
1101 1134
 	.sys_rst(sys_rst),
@@ -1130,7 +1163,7 @@ assign pfpubus_stb = 1'b0;
1130 1163
 //---------------------------------------------------------------------------
1131 1164
 `ifdef ENABLE_TMU
1132 1165
 tmu2 #(
1133  
-	.csr_addr(4'h7),
  1166
+	.csr_addr(5'h7),
1134 1167
 	.fml_depth(`SDRAM_DEPTH)
1135 1168
 ) tmu (
1136 1169
 	.sys_clk(sys_clk),
@@ -1170,7 +1203,7 @@ tmu2 #(
1170 1203
 `else
1171 1204
 `ifdef ENABLE_MEMTEST
1172 1205
 memtest #(
1173  
-	.csr_addr(4'h7),
  1206
+	.csr_addr(5'h7),
1174 1207
 	.fml_depth(`SDRAM_DEPTH)
1175 1208
 ) memtest (
1176 1209
 	.sys_clk(sys_clk),
@@ -1244,7 +1277,7 @@ BUFG b_phy_rx_clk(
1244 1277
 );
1245 1278
 `ifdef ENABLE_ETHERNET
1246 1279
 minimac2 #(
1247  
-	.csr_addr(4'h8)
  1280
+	.csr_addr(5'h8)
1248 1281
 ) ethernet (
1249 1282
 	.sys_clk(sys_clk),
1250 1283
 	.sys_rst(sys_rst),
@@ -1300,7 +1333,7 @@ always @(posedge clk50) phy_clk <= ~phy_clk;
1300 1333
 //---------------------------------------------------------------------------
1301 1334
 `ifdef ENABLE_FMLMETER
1302 1335
 fmlmeter #(
1303  
-	.csr_addr(4'h9)
  1336
+	.csr_addr(5'h9)
1304 1337
 ) fmlmeter (
1305 1338
 	.sys_clk(sys_clk),
1306 1339
 	.sys_rst(sys_rst),
@@ -1327,7 +1360,7 @@ BUFG b_videoin(
1327 1360
 );
1328 1361
 `ifdef ENABLE_VIDEOIN
1329 1362
 bt656cap #(
1330  
-	.csr_addr(4'ha),
  1363
+	.csr_addr(5'ha),
1331 1364
 	.fml_depth(`SDRAM_DEPTH)
1332 1365
 ) videoin (
1333 1366
 	.sys_clk(sys_clk),
@@ -1367,7 +1400,7 @@ assign videoin_sdc = 1'b0;
1367 1400
 //---------------------------------------------------------------------------
1368 1401
 `ifdef ENABLE_MIDI
1369 1402
 uart #(
1370  
-	.csr_addr(4'hb),
  1403
+	.csr_addr(5'hb),
1371 1404
 	.clk_freq(`CLOCK_FREQUENCY),
1372 1405
 	.baud(31250),
1373 1406
 	.break_en_default(1'b0)
@@ -1398,7 +1431,7 @@ assign midi_tx = 1'b1;
1398 1431
 //---------------------------------------------------------------------------
1399 1432
 `ifdef ENABLE_DMX
1400 1433
 dmx_tx #(
1401  
-	.csr_addr(4'hc),
  1434
+	.csr_addr(5'hc),
1402 1435
 	.clk_freq(`CLOCK_FREQUENCY)
1403 1436
 ) dmx_tx (
1404 1437
 	.sys_clk(sys_clk),
@@ -1414,7 +1447,7 @@ dmx_tx #(
1414 1447
 );
1415 1448
 assign dmxa_de = 1'b1;
1416 1449
 dmx_rx #(
1417  
-	.csr_addr(4'hd),
  1450
+	.csr_addr(5'hd),
1418 1451
 	.clk_freq(`CLOCK_FREQUENCY)
1419 1452
 ) dmx_rx (
1420 1453
 	.sys_clk(sys_clk),
@@ -1443,7 +1476,7 @@ assign dmxb_d = 1'b0;
1443 1476
 //---------------------------------------------------------------------------
1444 1477
 `ifdef ENABLE_IR
1445 1478
 rc5 #(
1446  
-	.csr_addr(4'he),
  1479
+	.csr_addr(5'he),
1447 1480
 	.clk_freq(`CLOCK_FREQUENCY)
1448 1481
 ) ir (
1449 1482
 	.sys_clk(sys_clk),
@@ -1507,7 +1540,7 @@ BUFG usb_b_p(
1507 1540
 );
1508 1541
 `ifdef ENABLE_USB
1509 1542
 softusb #(
1510  
-	.csr_addr(4'hf)
  1543
+	.csr_addr(5'hf)
1511 1544
 ) usb (
1512 1545
 	.sys_clk(sys_clk),
1513 1546
 	.sys_rst(sys_rst),
@@ -1571,4 +1604,45 @@ FD workaround(
1571 1604
 
1572 1605
 `endif
1573 1606
 
  1607
+//---------------------------------------------------------------------------
  1608
+// UART1
  1609
+//---------------------------------------------------------------------------
  1610
+uart #(
  1611
+	.csr_addr(5'h10),
  1612
+	.clk_freq(`CLOCK_FREQUENCY),
  1613
+	.baud(`BAUD_RATE)
  1614
+) uart1 (
  1615
+		.sys_clk(sys_clk),
  1616
+		.sys_rst(sys_rst),
  1617
+	
  1618
+		.csr_a(csr_a),
  1619
+		.csr_we(csr_we),
  1620
+		.csr_di(csr_dw),
  1621
+		.csr_do(csr_dr_uart1),
  1622
+	
  1623
+		.rx_irq(uart1rx_irq),
  1624
+		.tx_irq(uart1tx_irq),
  1625
+	
  1626
+		.uart_rx(uart1_rx),
  1627
+		.uart_tx(uart1_tx)
  1628
+	);
  1629
+
  1630
+//---------------------------------------------------------------------------
  1631
+// Debug led 
  1632
+//---------------------------------------------------------------------------
  1633
+hello hello(
  1634
+	.sys_clk(sys_clk),
  1635
+	.sys_rst(sys_rst),
  1636
+
  1637
+	.wb_adr_i(hello_adr),
  1638
+	.wb_dat_i(hello_dat_w),
  1639
+	.wb_dat_o(hello_dat_r),
  1640
+	.wb_cyc_i(hello_cyc),
  1641
+	.wb_stb_i(hello_stb),
  1642
+	.wb_we_i(hello_we),
  1643
+	.wb_ack_o(hello_ack),
  1644
+
  1645
+	.debug_led(debug_led)
  1646
+);
  1647
+
1574 1648
 endmodule
3  boards/milkymist-one/sources.mak
@@ -43,5 +43,6 @@ DMX_SRC=$(wildcard $(CORES_DIR)/dmx/rtl/*.v)
43 43
 USB_SRC=$(wildcard $(CORES_DIR)/softusb/rtl/*.v)
44 44
 MEMTEST_SRC=$(wildcard $(CORES_DIR)/memtest/rtl/*.v)
45 45
 MONITOR_SRC=$(wildcard $(CORES_DIR)/monitor/rtl/*.v)
  46
+HELLO_CONBUS_SRC=$(wildcard $(CORES_DIR)/hello_conbus/rtl/*.v)
46 47
 
47  
-CORES_SRC=$(ASFIFO_SRC) $(CONBUS_SRC) $(LM32_SRC) $(FMLARB_SRC) $(FMLBRG_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(UART_SRC) $(SYSCTL_SRC) $(HPDMC_SRC) $(VGAFB_SRC) $(MEMCARD_SRC) $(AC97_SRC) $(PFPU_SRC) $(TMU_SRC) $(ETHERNET_SRC) $(FMLMETER_SRC) $(VIDEOIN_SRC) $(DMX_SRC) $(IR_SRC) $(USB_SRC) $(MEMTEST_SRC) $(MONITOR_SRC)
  48
+CORES_SRC=$(ASFIFO_SRC) $(CONBUS_SRC) $(LM32_SRC) $(FMLARB_SRC) $(FMLBRG_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(UART_SRC) $(SYSCTL_SRC) $(HPDMC_SRC) $(VGAFB_SRC) $(MEMCARD_SRC) $(AC97_SRC) $(PFPU_SRC) $(TMU_SRC) $(ETHERNET_SRC) $(FMLMETER_SRC) $(VIDEOIN_SRC) $(DMX_SRC) $(IR_SRC) $(USB_SRC) $(MEMTEST_SRC) $(MONITOR_SRC) $(HELLO_CONBUS_SRC)
16  boards/milkymist-one/synthesis/common.ucf
@@ -302,15 +302,19 @@ NET "exp(2)" LOC = A21;
302 302
 NET "exp(3)" LOC = F17;
303 303
 NET "exp(4)" LOC = B21;
304 304
 NET "exp(5)" LOC = H16;
305  
-NET "exp(6)" LOC = B22;
306  
-NET "exp(7)" LOC = H17;
307  
-NET "exp(8)" LOC = G16;
308  
-NET "exp(9)" LOC = J16;
309  
-NET "exp(10)" LOC = G17;
310  
-NET "exp(11)" LOC = K16;
  305
+NET "exp(6)" LOC = H17;
  306
+NET "exp(7)" LOC = J16;
  307
+NET "exp(8)" LOC = K16;
311 308
 
312 309
 NET "exp(*)" IOSTANDARD = LVCMOS33;
313 310
 
  311
+# ==== Debug Led ====
  312
+NET "debug_led" LOC = B22 | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO | DRIVE = 24;
  313
+
  314
+# ==== UART1 ====
  315
+NET "uart1_rx" LOC = G17 | IOSTANDARD = LVCMOS33 | PULLUP;		#IO_L13P_1
  316
+NET "uart1_tx" LOC = G16 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
  317
+
314 318
 # avoid floating signals
315 319
 NET "exp(*)" PULLDOWN;
316 320
 
2  cores/ac97/rtl/ac97.v
@@ -29,7 +29,7 @@ module ac97 #(
29 29
 	output ac97_sync,
30 30
 	
31 31
 	/* Control interface */
32  
-	input [13:0] csr_a,
  32
+	input [14:0] csr_a,
33 33
 	input csr_we,
34 34
 	input [31:0] csr_di,
35 35
 	output [31:0] csr_do,
4  cores/ac97/rtl/ac97_ctlif.v
@@ -21,7 +21,7 @@ module ac97_ctlif #(
21 21
 	input sys_clk,
22 22
 	input sys_rst,
23 23
 
24  
-	input [13:0] csr_a,
  24
+	input [14:0] csr_a,
25 25
 	input csr_we,
26 26
 	input [31:0] csr_di,
27 27
 	output reg [31:0] csr_do,
@@ -73,7 +73,7 @@ always @(posedge sys_clk) begin
73 73
 		dmaw_finished_r <= dmaw_finished;
74 74
 end
75 75
 
76  
-wire csr_selected = csr_a[13:10] == csr_addr;
  76
+wire csr_selected = csr_a[14:10] == csr_addr;
77 77
 
78 78
 reg request_en;
79 79
 reg request_write;
2  cores/bt656cap/rtl/bt656cap.v
@@ -22,7 +22,7 @@ module bt656cap #(
22 22
 	input sys_clk,
23 23
 	input sys_rst,
24 24
 
25  
-	input [13:0] csr_a,
  25
+	input [14:0] csr_a,
26 26
 	input csr_we,
27 27
 	input [31:0] csr_di,
28 28
 	output [31:0] csr_do,
4  cores/bt656cap/rtl/bt656cap_ctlif.v
@@ -22,7 +22,7 @@ module bt656cap_ctlif #(
22 22
 	input sys_clk,
23 23
 	input sys_rst,
24 24
 
25  
-	input [13:0] csr_a,
  25
+	input [14:0] csr_a,
26 26
 	input csr_we,
27 27
 	input [31:0] csr_di,
28 28
 	output reg [31:0] csr_do,
@@ -55,7 +55,7 @@ assign sda = (sda_oe & ~sda_o) ? 1'b0 : 1'bz;
55 55
 
56 56
 /* CSR IF */
57 57
 
58  
-wire csr_selected = csr_a[13:10] == csr_addr;
  58
+wire csr_selected = csr_a[14:10] == csr_addr;
59 59
 
60 60
 reg [14:0] max_bursts;
61 61
 reg [14:0] done_bursts;
32  cores/conbus/rtl/conbus5x6.v → cores/conbus/rtl/conbus5x7.v
@@ -26,13 +26,14 @@
26 26
  * from http://www.opencores.org/lgpl.shtml.
27 27
  */
28 28
 
29  
-module conbus5x6 #(
  29
+module conbus5x7 #(
30 30
 	parameter s0_addr = 3'b000,
31 31
 	parameter s1_addr = 3'b001,
32 32
 	parameter s2_addr = 3'b010,
33 33
 	parameter s3_addr = 3'b011,
34 34
 	parameter s4_addr = 2'b10,
35  
-	parameter s5_addr = 2'b11
  35
+	parameter s5_addr = 2'b11,
  36
+	parameter s6_addr = 3'b111
36 37
 ) (
37 38
 	input sys_clk,
38 39
 	input sys_rst,
@@ -157,14 +158,25 @@ module conbus5x6 #(
157 158
 	output		s5_we_o,
158 159
 	output		s5_cyc_o,
159 160
 	output		s5_stb_o,
160  
-	input		s5_ack_i
  161
+	input		s5_ack_i,
  162
+
  163
+	// Slave 6 Interface
  164
+	input	[31:0]	s6_dat_i,
  165
+	output	[31:0]	s6_dat_o,
  166
+	output	[31:0]	s6_adr_o,
  167
+	output	[2:0]	s6_cti_o,
  168
+	output	[3:0]	s6_sel_o,
  169
+	output		s6_we_o,
  170
+	output		s6_cyc_o,
  171
+	output		s6_stb_o,
  172
+	input		s6_ack_i
161 173
 );
162 174
 
163 175
 // address + CTI + data + byte select
164 176
 // + cyc + we + stb
165 177
 `define mbusw_ls  32 + 3 + 32 + 4 + 3
166 178
 
167  
-wire [5:0] slave_sel;
  179
+wire [6:0] slave_sel;
168 180
 wire [2:0] gnt;
169 181
 reg [`mbusw_ls -1:0] i_bus_m;	// internal shared bus, master data and control to slave
170 182
 wire [31:0] i_dat_s;		// internal shared bus, slave data to master
@@ -190,7 +202,7 @@ assign m3_ack_o = i_bus_ack & (gnt == 3'd3);
190 202
 assign m4_dat_o = i_dat_s;
191 203
 assign m4_ack_o = i_bus_ack & (gnt == 3'd4);
192 204
 
193  
-assign i_bus_ack = s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i;
  205
+assign i_bus_ack = s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i;
194 206
 
195 207
 // slave 0
196 208
 assign {s0_adr_o, s0_cti_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cyc_o, s0_stb_o} 
@@ -216,6 +228,10 @@ assign {s4_adr_o, s4_cti_o, s4_sel_o, s4_dat_o, s4_we_o, s4_cyc_o, s4_stb_o}
216 228
 assign {s5_adr_o, s5_cti_o, s5_sel_o, s5_dat_o, s5_we_o, s5_cyc_o, s5_stb_o} 
217 229
 	= {i_bus_m[`mbusw_ls -1:2], i_bus_m[1] & slave_sel[5], i_bus_m[0]};
218 230
 
  231
+// slave 6
  232
+assign {s6_adr_o, s6_cti_o, s6_sel_o, s6_dat_o, s6_we_o, s6_cyc_o, s6_stb_o} 
  233
+	= {i_bus_m[`mbusw_ls -1:2], i_bus_m[1] & slave_sel[6], i_bus_m[0]};
  234
+
219 235
 always @(*) begin
220 236
 	case(gnt)
221 237
 		3'd0:    i_bus_m = {m0_adr_i, m0_cti_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cyc_i, m0_stb_i};
@@ -227,7 +243,7 @@ always @(*) begin
227 243
 end
228 244
 
229 245
 // !!!! This breaks WISHBONE combinatorial feedback. Don't use it !!!!
230  
-reg [5:0] slave_sel_r;
  246
+reg [6:0] slave_sel_r;
231 247
 always @(posedge sys_clk)
232 248
 	slave_sel_r <= slave_sel;
233 249
 // !!!! This breaks WISHBONE combinatorial feedback. Don't use it !!!!
@@ -238,7 +254,8 @@ assign i_dat_s =
238 254
 		|({32{slave_sel_r[2]}} & s2_dat_i)
239 255
 		|({32{slave_sel_r[3]}} & s3_dat_i)
240 256
 		|({32{slave_sel_r[4]}} & s4_dat_i)
241  
-		|({32{slave_sel_r[5]}} & s5_dat_i);
  257
+                |({32{slave_sel_r[5]}} & s5_dat_i)
  258
+		|({32{slave_sel_r[6]}} & s6_dat_i);
242 259
 
243 260
 wire [4:0] req = {m4_cyc_i, m3_cyc_i, m2_cyc_i, m1_cyc_i, m0_cyc_i};
244 261
 
@@ -255,5 +272,6 @@ assign slave_sel[2] = (i_bus_m[`mbusw_ls-2 : `mbusw_ls-3-1] == s2_addr);
255 272
 assign slave_sel[3] = (i_bus_m[`mbusw_ls-2 : `mbusw_ls-3-1] == s3_addr);
256 273
 assign slave_sel[4] = (i_bus_m[`mbusw_ls-2 : `mbusw_ls-2-1] == s4_addr);
257 274
 assign slave_sel[5] = (i_bus_m[`mbusw_ls-2 : `mbusw_ls-2-1] == s5_addr);
  275
+assign slave_sel[6] = (i_bus_m[`mbusw_ls-2 : `mbusw_ls-3-1] == s6_addr);
258 276
 
259 277
 endmodule
4  cores/csrbrg/rtl/csrbrg.v
@@ -29,7 +29,7 @@ module csrbrg(
29 29
 	output reg wb_ack_o,
30 30
 	
31 31
 	/* CSR */
32  
-	output reg [13:0] csr_a,
  32
+	output reg [14:0] csr_a,
33 33
 	output reg csr_we,
34 34
 	output reg [31:0] csr_do,
35 35
 	input [31:0] csr_di
@@ -43,7 +43,7 @@ end
43 43
 /* Datapath: CSR <- WB */
44 44
 reg next_csr_we;
45 45
 always @(posedge sys_clk) begin
46  
-	csr_a <= wb_adr_i[15:2];
  46
+	csr_a <= wb_adr_i[16:2];
47 47
 	csr_we <= next_csr_we;
48 48
 	csr_do <= wb_dat_i;
49 49
 end
4  cores/dmx/rtl/dmx_rx.v
@@ -22,7 +22,7 @@ module dmx_rx #(
22 22
 	input sys_clk,
23 23
 	input sys_rst,
24 24
 
25  
-	input [13:0] csr_a,
  25
+	input [14:0] csr_a,
26 26
 	input csr_we,
27 27
 	input [31:0] csr_di,
28 28
 	output [31:0] csr_do,
@@ -32,7 +32,7 @@ module dmx_rx #(
32 32
 
33 33
 /* RAM and CSR interface */
34 34
 
35  
-wire csr_selected = csr_a[13:10] == csr_addr;
  35
+wire csr_selected = csr_a[14:10] == csr_addr;
36 36
 
37 37
 wire [7:0] csr_channel;
38 38
 reg [8:0] channel_a;
4  cores/dmx/rtl/dmx_tx.v
@@ -22,7 +22,7 @@ module dmx_tx #(
22 22
 	input sys_clk,
23 23
 	input sys_rst,
24 24
 
25  
-	input [13:0] csr_a,
  25
+	input [14:0] csr_a,
26 26
 	input csr_we,
27 27
 	input [31:0] csr_di,
28 28
 	output [31:0] csr_do,
@@ -33,7 +33,7 @@ module dmx_tx #(
33 33
 
34 34
 /* RAM and CSR interface */
35 35
 
36  
-wire csr_selected = csr_a[13:10] == csr_addr;
  36
+wire csr_selected = csr_a[14:10] == csr_addr;
37 37
 
38 38
 wire csr_channels_we;
39 39
 wire [31:0] csr_do_channels;
4  cores/fmlmeter/rtl/fmlmeter.v
@@ -21,7 +21,7 @@ module fmlmeter #(
21 21
 	input sys_clk,
22 22
 	input sys_rst,
23 23
 
24  
-	input [13:0] csr_a,
  24
+	input [14:0] csr_a,
25 25
 	input csr_we,
26 26
 	input [31:0] csr_di,
27 27
 	output reg [31:0] csr_do,
@@ -42,7 +42,7 @@ reg en;			// @ 00
42 42
 reg [31:0] stb_count;	// @ 04
43 43
 reg [31:0] ack_count;	// @ 08
44 44
 
45  
-wire csr_selected = csr_a[13:10] == csr_addr;
  45
+wire csr_selected = csr_a[14:10] == csr_addr;
46 46
 
47 47
 always @(posedge sys_clk) begin
48 48
 	if(sys_rst) begin
104  cores/hello_conbus/rtl/hello_conbus.v
... ...
@@ -0,0 +1,104 @@
  1
+/*
  2
+ * Milkymist VJ SoC
  3
+ * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
  4
+ * Copyleft   2011 Cristian Paul Peñaranda Rojas
  5
+ *
  6
+ * This program is free software: you can redistribute it and/or modify
  7
+ * it under the terms of the GNU General Public License as published by
  8
+ * the Free Software Foundation, version 3 of the License.
  9
+ *
  10
+ * This program is distributed in the hope that it will be useful,
  11
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13
+ * GNU General Public License for more details.
  14
+ *
  15
+ * You should have received a copy of the GNU General Public License
  16
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17
+ */
  18
+
  19
+module hello(
  20
+	input sys_clk,
  21
+	input sys_rst,
  22
+	
  23
+	/* WB */
  24
+	input [31:0] wb_adr_i,
  25
+	input [31:0] wb_dat_i,
  26
+	output reg [31:0] wb_dat_o,
  27
+	input wb_cyc_i,
  28
+	input wb_stb_i,
  29
+	input wb_we_i,
  30
+	output reg wb_ack_o,
  31
+	
  32
+	/* LED */
  33
+	output debug_led
  34
+);
  35
+
  36
+reg [31:0] data_i;
  37
+/* Sync data */
  38
+reg next_csr_we;
  39
+always @(posedge sys_clk) begin
  40
+	data_i <= wb_dat_i;
  41
+end
  42
+
  43
+/* Controller */
  44
+reg [1:0] state;
  45
+reg [1:0] next_state;
  46
+
  47
+reg led_state = 1'b0;
  48
+
  49
+parameter IDLE		= 2'd0;
  50
+parameter DELAYACK1	= 2'd1;
  51
+parameter DELAYACK2	= 2'd2;
  52
+parameter ACK		= 2'd3;
  53
+
  54
+parameter OFF		= 1'd0;
  55
+
  56
+always @(posedge sys_clk) begin
  57
+	if(sys_rst)
  58
+		state <= IDLE;
  59
+	else
  60
+		state <= next_state;
  61
+end
  62
+
  63
+always @(*) begin
  64
+	next_state = state;
  65
+	
  66
+	wb_ack_o = 1'b0;
  67
+	
  68
+	case(state)
  69
+		IDLE: begin
  70
+			if(wb_cyc_i & wb_stb_i) begin
  71
+				/* We have a request for us */
  72
+				if(wb_we_i)
  73
+					next_state = ACK;
  74
+				else
  75
+					next_state = DELAYACK1;
  76
+			end
  77
+		end
  78
+		DELAYACK1: next_state = DELAYACK2;
  79
+		DELAYACK2: next_state = ACK;
  80
+		ACK: begin
  81
+			wb_ack_o = 1'b1;
  82
+			next_state = IDLE;
  83
+		end
  84
+	endcase
  85
+end
  86
+//parameter csr_addr = 4'h0
  87
+//wire csr_selected = csr_a[14:10] == csr_addr;
  88
+
  89
+/* fake read data */
  90
+always @(posedge sys_clk) begin
  91
+	if(next_state == DELAYACK1)
  92
+		wb_dat_o <= 4'hffff;
  93
+end
  94
+
  95
+/* Drive LEd */
  96
+always @(posedge sys_clk) begin
  97
+	// ACK!!!
  98
+	if(next_state == ACK)
  99
+		led_state <= data_i[0];
  100
+end
  101
+
  102
+assign  debug_led = led_state;
  103
+
  104
+endmodule
2  cores/hpdmc_ddr32/rtl/hpdmc.v
@@ -33,7 +33,7 @@ module hpdmc #(
33 33
 	input sys_rst,
34 34
 	
35 35
 	/* Control interface */
36  
-	input [13:0] csr_a,
  36
+	input [14:0] csr_a,
37 37
 	input csr_we,
38 38
 	input [31:0] csr_di,
39 39
 	output [31:0] csr_do,
4  cores/hpdmc_ddr32/rtl/hpdmc_ctlif.v
@@ -21,7 +21,7 @@ module hpdmc_ctlif #(
21 21
 	input sys_clk,
22 22
 	input sys_rst,
23 23
 	
24  
-	input [13:0] csr_a,
  24
+	input [14:0] csr_a,
25 25
 	input csr_we,
26 26
 	input [31:0] csr_di,
27 27
 	output reg [31:0] csr_do,
@@ -56,7 +56,7 @@ module hpdmc_ctlif #(
56 56
 	output reg idelay_cal
57 57
 );
58 58
 
59  
-wire csr_selected = csr_a[13:10] == csr_addr;
  59
+wire csr_selected = csr_a[14:10] == csr_addr;
60 60
 
61 61
 always @(posedge sys_clk) begin
62 62
 	if(sys_rst) begin
4  cores/memcard/rtl/memcard.v
@@ -21,7 +21,7 @@ module memcard #(
21 21
 	input sys_clk,
22 22
 	input sys_rst,
23 23
 
24  
-	input [13:0] csr_a,
  24
+	input [14:0] csr_a,
25 25
 	input csr_we,
26 26
 	input [31:0] csr_di,
27 27
 	output reg [31:0] csr_do,
@@ -98,7 +98,7 @@ always @(posedge sys_clk) begin
98 98
 	mc_d_r2 <= mc_d_r1;
99 99
 end
100 100
 
101  
-wire csr_selected = csr_a[13:10] == csr_addr;
  101
+wire csr_selected = csr_a[14:10] == csr_addr;
102 102
 
103 103
 reg [2:0] cmd_bitcount;
104 104
 reg [2:0] dat_bitcount;
4  cores/memtest/rtl/memtest.v
@@ -23,7 +23,7 @@ module memtest #(
23 23
 	input sys_rst,
24 24
 
25 25
 	/* Configuration interface */
26  
-	input [13:0] csr_a,
  26
+	input [14:0] csr_a,
27 27
 	input csr_we,
28 28
 	input [31:0] csr_di,
29 29
 	output reg [31:0] csr_do,
@@ -41,7 +41,7 @@ module memtest #(
41 41
 wire rand_ce;
42 42
 wire [63:0] rand;
43 43
 
44  
-wire csr_selected = csr_a[13:10] == csr_addr;
  44
+wire csr_selected = csr_a[14:10] == csr_addr;
45 45
 wire load_nbursts = csr_selected & (csr_a[2:0] == 3'd0) & csr_we;
46 46
 wire load_address = csr_selected & (csr_a[2:0] == 3'd2) & csr_we;
47 47
 
2  cores/minimac2/rtl/minimac2.v
@@ -22,7 +22,7 @@ module minimac2 #(
22 22
 	input sys_rst,
23 23
 
24 24
 	/* CSR */
25  
-	input [13:0] csr_a,
  25
+	input [14:0] csr_a,
26 26
 	input csr_we,
27 27
 	input [31:0] csr_di,
28 28
 	output [31:0] csr_do,
4  cores/minimac2/rtl/minimac2_ctlif.v
@@ -21,7 +21,7 @@ module minimac2_ctlif #(
21 21
 	input sys_clk,
22 22
 	input sys_rst,
23 23
 
24  
-	input [13:0] csr_a,
  24
+	input [14:0] csr_a,
25 25
 	input csr_we,
26 26
 	input [31:0] csr_di,
27 27
 	output reg [31:0] csr_do,
@@ -70,7 +70,7 @@ assign phy_rst_n = ~(phy_rst | sys_rst);
70 70
 reg [1:0] slot0_state;
71 71
 reg [1:0] slot1_state;
72 72
 
73  
-wire csr_selected = csr_a[13:10] == csr_addr;
  73
+wire csr_selected = csr_a[14:10] == csr_addr;
74 74
 
75 75
 always @(posedge sys_clk) begin
76 76
 	if(sys_rst) begin
2  cores/pfpu/rtl/pfpu.v
@@ -22,7 +22,7 @@ module pfpu #(
22 22
 	input sys_rst,
23 23
 	
24 24
 	/* Control interface */
25  
-	input [13:0] csr_a,
  25
+	input [14:0] csr_a,
26 26
 	input csr_we,
27 27
 	input [31:0] csr_di,
28 28
 	output [31:0] csr_do,
4  cores/pfpu/rtl/pfpu_ctlif.v
@@ -21,7 +21,7 @@ module pfpu_ctlif #(
21 21
 	input sys_clk,
22 22
 	input sys_rst,
23 23
 	
24  
-	input [13:0] csr_a,
  24
+	input [14:0] csr_a,
25 25
 	input csr_we,
26 26
 	input [31:0] csr_di,
27 27
 	output [31:0] csr_do,
@@ -76,7 +76,7 @@ reg [13:0] vertex_counter;
76 76
 reg [10:0] collision_counter;
77 77
 reg [10:0] stray_counter;
78 78
 
79  
-wire csr_selected = csr_a[13:10] == csr_addr;
  79
+wire csr_selected = csr_a[14:10] == csr_addr;
80 80
 
81 81
 reg [31:0] csr_do_r;
82 82
 reg csr_do_cont;
4  cores/rc5/rtl/rc5.v
@@ -23,7 +23,7 @@ module rc5 #(
23 23
 	input sys_clk,
24 24
 	input sys_rst,
25 25
 
26  
-	input [13:0] csr_a,
  26
+	input [14:0] csr_a,
27 27
 	input csr_we,
28 28
 	input [31:0] csr_di,
29 29
 	output reg [31:0] csr_do,
@@ -114,7 +114,7 @@ end
114 114
 // CSR interface
115 115
 //-----------------------------------------------------------------
116 116
 
117  
-wire csr_selected = csr_a[13:10] == csr_addr;
  117
+wire csr_selected = csr_a[14:10] == csr_addr;
118 118
 
119 119
 always @(posedge sys_clk) begin
120 120
 	if(sys_rst) begin
2  cores/softusb/rtl/softusb.v
@@ -27,7 +27,7 @@ module softusb #(
27 27
 	input usb_clk,
28 28
 
29 29
 	/* CSR interface */
30  
-	input [13:0] csr_a,
  30
+	input [14:0] csr_a,
31 31
 	input csr_we,
32 32
 	input [31:0] csr_di,
33 33
 	output [31:0] csr_do,
4  cores/softusb/rtl/softusb_hostif.v
@@ -24,7 +24,7 @@ module softusb_hostif #(
24 24
 	input usb_clk,
25 25
 	output reg usb_rst,
26 26
 
27  
-	input [13:0] csr_a,
  27
+	input [14:0] csr_a,
28 28
 	input csr_we,
29 29
 	input [31:0] csr_di,
30 30
 	output reg [31:0] csr_do,
@@ -35,7 +35,7 @@ module softusb_hostif #(
35 35
 	input [5:0] io_a
36 36
 );
37 37
 
38  
-wire csr_selected = csr_a[13:10] == csr_addr;
  38
+wire csr_selected = csr_a[14:10] == csr_addr;
39 39
 
40 40
 reg usb_rst0;
41 41
 
4  cores/sysctl/rtl/sysctl.v
@@ -30,7 +30,7 @@ module sysctl #(
30 30
 	output reg timer1_irq,
31 31
 
32 32
 	/* CSR bus interface */
33  
-	input [13:0] csr_a,
  33
+	input [14:0] csr_a,
34 34
 	input csr_we,
35 35
 	input [31:0] csr_di,
36 36
 	output reg [31:0] csr_do,
@@ -107,7 +107,7 @@ reg [7:0] debug_scratchpad;
107 107
  * Logic and CSR interface
108 108
  */
109 109
 
110  
-wire csr_selected = csr_a[13:10] == csr_addr;
  110
+wire csr_selected = csr_a[14:10] == csr_addr;
111 111
 
112 112
 assign icap_we = csr_selected & csr_we & (csr_a[3:0] == 4'b1101);
113 113
 
2  cores/tmu2/rtl/tmu2.v
@@ -25,7 +25,7 @@ module tmu2 #(
25 25
 	input sys_rst,
26 26
 	
27 27
 	/* Control interface */
28  
-	input [13:0] csr_a,
  28
+	input [14:0] csr_a,
29 29
 	input csr_we,
30 30
 	input [31:0] csr_di,
31 31
 	output [31:0] csr_do,
4  cores/tmu2/rtl/tmu2_ctlif.v
@@ -22,7 +22,7 @@ module tmu2_ctlif #(
22 22
 	input sys_clk,
23 23
 	input sys_rst,
24 24
 	
25  
-	input [13:0] csr_a,
  25
+	input [14:0] csr_a,
26 26
 	input csr_we,
27 27
 	input [31:0] csr_di,
28 28
 	output reg [31:0] csr_do,
@@ -63,7 +63,7 @@ always @(posedge sys_clk) begin
63 63
 		old_busy <= busy;
64 64
 end
65 65
 
66  
-wire csr_selected = csr_a[13:10] == csr_addr;
  66
+wire csr_selected = csr_a[14:10] == csr_addr;
67 67
 
68 68
 always @(posedge sys_clk) begin
69 69
 	if(sys_rst) begin
4  cores/uart/rtl/uart.v
@@ -24,7 +24,7 @@ module uart #(
24 24
 	input sys_clk,
25 25
 	input sys_rst,
26 26
 	
27  
-	input [13:0] csr_a,
  27
+	input [14:0] csr_a,
28 28
 	input csr_we,
29 29
 	input [31:0] csr_di,
30 30
 	output reg [31:0] csr_do,
@@ -68,7 +68,7 @@ assign uart_tx = thru ? uart_rx : uart_tx_transceiver;
68 68
 assign break = break_en & break_transceiver;
69 69
 
70 70
 /* CSR interface */
71  
-wire csr_selected = csr_a[13:10] == csr_addr;
  71
+wire csr_selected = csr_a[14:10] == csr_addr;
72 72
 
73 73
 assign tx_data = csr_di[7:0];
74 74
 assign tx_wr = csr_selected & csr_we & (csr_a[1:0] == 2'b00);
2  cores/vgafb/rtl/vgafb.v
@@ -23,7 +23,7 @@ module vgafb #(
23 23
 	input sys_rst,
24 24
 	
25 25
 	/* Configuration interface */
26  
-	input [13:0] csr_a,
  26
+	input [14:0] csr_a,
27 27
 	input csr_we,
28 28
 	input [31:0] csr_di,
29 29
 	output [31:0] csr_do,
4  cores/vgafb/rtl/vgafb_ctlif.v
@@ -22,7 +22,7 @@ module vgafb_ctlif #(
22 22
 	input sys_clk,
23 23
 	input sys_rst,
24 24
 	
25  
-	input [13:0] csr_a,
  25
+	input [14:0] csr_a,
26 26
 	input csr_we,
27 27
 	input [31:0] csr_di,
28 28
 	output reg [31:0] csr_do,
@@ -74,7 +74,7 @@ always @(posedge sys_clk) begin
74 74
 		baseaddress_act <= baseaddress;
75 75
 end
76 76
 
77  
-wire csr_selected = csr_a[13:10] == csr_addr;
  77
+wire csr_selected = csr_a[14:10] == csr_addr;
78 78
 
79 79
 always @(posedge sys_clk) begin
80 80
 	if(sys_rst) begin
2  software/bios/crt0.S
@@ -73,7 +73,7 @@ macaddress:
73 73
 	.byte 0xd5
74 74
 	.byte 0x00
75 75
 	.byte 0x00
76  
-	.byte 0x00
  76
+	.byte 0x2e
77 77
 
78 78
 	/* padding to align to a 32-bit boundary */
79 79
 	.byte 0x00

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