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  • 2 commits
  • 2 files changed
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  • 1 contributor
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2  cores/namuru/rtl/namuru_baseband.v
@@ -212,7 +212,7 @@ always @(posedge correlator_clk) begin
ch0_epoch_load <= wb_dat_i[10:0];
end
//enable flags for channel tracking logic
- 8'h0F: {ch0_epoch_enable,ch0_slew_enable,ch0_prn_key_enable,ch0_prn_key_enable} <= wb_dat_i[3:0];
+ 8'h0F: {ch0_epoch_enable,ch0_slew_enable,ch0_prn_key_enable} <= wb_dat_i[2:0];
/* status */
8'hE4: begin // clear status flag
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8 cores/namuru/rtl/namuru_code_gen2.v
@@ -76,12 +76,12 @@ module code_gen (clk, rstn, tic_enable, hc_enable, prn_key_enable, prn_key, code
defparam sr.lpm_width= 3; */
reg [2:0] shift_temp;
always @(posedge clk) begin
- if (prn_key_enable)
+ if (prn_key_enable)
shift_temp <= 3'b0;
- else
- shift_temp <= {shift_temp[1:0], ca_code};
+ else if (hc_enable)
+ shift_temp <= {shift_temp[1:0], ca_code};
end
- assign srq = shift_temp[2];
+ assign srq = shift_temp;
// The G1 shift register
//----------------------

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