Showing with 16 additions and 231 deletions.
  1. +2 −2 cores/namuru/rtl/namuru_carrier_nco.v
  2. +5 −5 cores/namuru/rtl/namuru_code_nco.v
  3. +0 −214 cores/namuru/rtl/namuru_ctlif.v
  4. +9 −10 cores/namuru/rtl/namuru_time_base.v
4 changes: 2 additions & 2 deletions cores/namuru/rtl/namuru_carrier_nco.v
View file
Expand Up @@ -24,7 +24,7 @@
I: -1 +1 +2 +2 +1 -1 -2 -2
Q: +2 +2 +1 -1 -2 -2 -1 +1
The nominal center frequency for the GP2015 is:
The nominal center frequency for the SiGE 4162 in real mode is:
IF = 2.556 MHz
Clk = 16.384 MHz
fControl = 2^N * IF / Clk
Expand All @@ -33,7 +33,7 @@
Resolution:
fControl increment value = 0.167510016 Hz
Put another way:
16mHz is the smallest change in carrier frequency possible
167mHz is the smallest change in carrier frequency possible
with this NCO.
The carrier phase and carrier cycle count are latched into
Expand Down
10 changes: 5 additions & 5 deletions cores/namuru/rtl/namuru_code_nco.v
View file
Expand Up @@ -28,18 +28,18 @@
where:
f = the required frequency
N = 29 (bit width of the phase accumulator)
clk = the system clock (= 40MHz)
clk = the system clock (= 16.384MHz)
fControl = the 28 bit (unsigned) control word
To generate the C/A code at f, the NCO must be set to run
at 2f, therefore:
code_frequency = 0.5 * fControl * clk/2^N
For a system clock running @ clk = 40 MHz:
fControl = code_frequency * 2^29 / 20[Mhz]
For a system clock running @ clk = 16.384 MHz:
fControl = code_frequency * 2^29 / 8.192[Mhz]
For code_frequency = 1.023MHz
fControl = 0x1A30552
fControl = 0x3FF0000
*/
/*
Copyright (C) 2007 Peter Mumford
Expand Down Expand Up @@ -99,4 +99,4 @@ endmodule // code_nco





214 changes: 0 additions & 214 deletions cores/namuru/rtl/namuru_ctlif.v
View file

This file was deleted.

19 changes: 9 additions & 10 deletions cores/namuru/rtl/namuru_time_base.v
View file
Expand Up @@ -26,7 +26,7 @@
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/

module time_base (clk, rstn, tic_divide, accum_divide, sample_clk, pre_tic_enable, tic_enable, accum_enable, accum_sample_enable, tic_count, accum_count);
module time_base (clk, rstn, tic_divide, accum_divide, sample_clk, pre_tic_enable, tic_enable, accum_enable, tic_count, accum_count);


input clk, rstn;
Expand All @@ -36,7 +36,6 @@ module time_base (clk, rstn, tic_divide, accum_divide, sample_clk, pre_tic_enabl
output pre_tic_enable; // to code_nco's
output tic_enable; // to code_gen's
output accum_enable; // accumulation interrupt
output accum_sample_enable; // accumulators sampling enable (40/7MHz)
output [23:0] tic_count; // the value of the TIC counter
output [23:0] accum_count; // the value of the accum counter

Expand All @@ -59,15 +58,15 @@ module time_base (clk, rstn, tic_divide, accum_divide, sample_clk, pre_tic_enabl
*/

//assign sample_clk = (sc_q == 0)? 1:0;
assign accum_sample_enable = (sc_q == 3)? 1:0; // accumulator sample pulse
//assign accum_sample_enable = (sc_q == 3)? 1:0; // accumulator sample pulse

//--------------------------------------------------
// generate the tic_enable
//
// tic period = (tic_divide + 1) * Clk period
// If clocked by GP2015 40HHz:
// tic period = (tic_divide + 1) / 40MHz
// For default tic period (0.1s) tic_divide = 0x3D08FF
// If clocked by SiGE 4162 Realmode 16.384Mhz :
// tic period = (tic_divide + 1) / 16.384 Mhz
// For default tic period (0.1s) tic_divide = 0x18ffff
//----------------------------------------------------
/* lpm_counter te(
.clock(clk),
Expand All @@ -84,7 +83,7 @@ module time_base (clk, rstn, tic_divide, accum_divide, sample_clk, pre_tic_enabl
if(rstn)
tmp_count_te <= 24'b111111111111111111111111;
else if (pre_tic_enable)
tmp_count_te <= accum_divide;
tmp_count_te <= tic_divide;
else
tmp_count_te <= tmp_count_te - 1'b1;
end
Expand Down Expand Up @@ -122,10 +121,10 @@ module time_base (clk, rstn, tic_divide, accum_divide, sample_clk, pre_tic_enabl
// The accumulators are asynchronous to each other and have a
// dump period of nominally 1ms.
//
// ACCUM_INT period = (accum_divide + 1) / 40MHz
// ACCUM_INT period = (accum_divide + 1) / 16.384MHz
// For 0.5 ms accumulator interrupt
// accum_divide = 40000000 * 0.0005 - 1
// accum_divide = 0x4E1F
// accum_divide = 16.384x10^6 * 0.0005 - 1
// accum_divide = 0x1FFF
//----------------------------------------------------------
/* lpm_counter ae(
.clock(clk),
Expand Down